1 /* 2 * Driver for C-Media CMI8338 and 8738 PCI soundcards. 3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 /* Does not work. Warning may block system in capture mode */ 21 /* #define USE_VAR48KRATE */ 22 23 #include <sound/driver.h> 24 #include <asm/io.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/init.h> 28 #include <linux/pci.h> 29 #include <linux/slab.h> 30 #include <linux/gameport.h> 31 #include <linux/moduleparam.h> 32 #include <sound/core.h> 33 #include <sound/info.h> 34 #include <sound/control.h> 35 #include <sound/pcm.h> 36 #include <sound/rawmidi.h> 37 #include <sound/mpu401.h> 38 #include <sound/opl3.h> 39 #include <sound/sb.h> 40 #include <sound/asoundef.h> 41 #include <sound/initval.h> 42 43 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); 44 MODULE_DESCRIPTION("C-Media CMI8x38 PCI"); 45 MODULE_LICENSE("GPL"); 46 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738}," 47 "{C-Media,CMI8738B}," 48 "{C-Media,CMI8338A}," 49 "{C-Media,CMI8338B}}"); 50 51 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 52 #define SUPPORT_JOYSTICK 1 53 #endif 54 55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 57 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ 58 static long mpu_port[SNDRV_CARDS]; 59 static long fm_port[SNDRV_CARDS]; 60 static int soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1}; 61 #ifdef SUPPORT_JOYSTICK 62 static int joystick_port[SNDRV_CARDS]; 63 #endif 64 65 module_param_array(index, int, NULL, 0444); 66 MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard."); 67 module_param_array(id, charp, NULL, 0444); 68 MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard."); 69 module_param_array(enable, bool, NULL, 0444); 70 MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard."); 71 module_param_array(mpu_port, long, NULL, 0444); 72 MODULE_PARM_DESC(mpu_port, "MPU-401 port."); 73 module_param_array(fm_port, long, NULL, 0444); 74 MODULE_PARM_DESC(fm_port, "FM port."); 75 module_param_array(soft_ac3, bool, NULL, 0444); 76 MODULE_PARM_DESC(soft_ac3, "Sofware-conversion of raw SPDIF packets (model 033 only)."); 77 #ifdef SUPPORT_JOYSTICK 78 module_param_array(joystick_port, int, NULL, 0444); 79 MODULE_PARM_DESC(joystick_port, "Joystick port address."); 80 #endif 81 82 /* 83 * CM8x38 registers definition 84 */ 85 86 #define CM_REG_FUNCTRL0 0x00 87 #define CM_RST_CH1 0x00080000 88 #define CM_RST_CH0 0x00040000 89 #define CM_CHEN1 0x00020000 /* ch1: enable */ 90 #define CM_CHEN0 0x00010000 /* ch0: enable */ 91 #define CM_PAUSE1 0x00000008 /* ch1: pause */ 92 #define CM_PAUSE0 0x00000004 /* ch0: pause */ 93 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */ 94 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */ 95 96 #define CM_REG_FUNCTRL1 0x04 97 #define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */ 98 #define CM_ASFC_SHIFT 13 99 #define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */ 100 #define CM_DSFC_SHIFT 10 101 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */ 102 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */ 103 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */ 104 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */ 105 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */ 106 #define CM_BREQ 0x00000010 /* bus master enabled */ 107 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */ 108 #define CM_UART_EN 0x00000004 /* UART */ 109 #define CM_JYSTK_EN 0x00000002 /* joy stick */ 110 111 #define CM_REG_CHFORMAT 0x08 112 113 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */ 114 #define CM_CHB3D 0x20000000 /* 4 channels */ 115 116 #define CM_CHIP_MASK1 0x1f000000 117 #define CM_CHIP_037 0x01000000 118 119 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */ 120 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */ 121 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */ 122 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */ 123 124 #define CM_ADCBITLEN_MASK 0x0000C000 125 #define CM_ADCBITLEN_16 0x00000000 126 #define CM_ADCBITLEN_15 0x00004000 127 #define CM_ADCBITLEN_14 0x00008000 128 #define CM_ADCBITLEN_13 0x0000C000 129 130 #define CM_ADCDACLEN_MASK 0x00003000 131 #define CM_ADCDACLEN_060 0x00000000 132 #define CM_ADCDACLEN_066 0x00001000 133 #define CM_ADCDACLEN_130 0x00002000 134 #define CM_ADCDACLEN_280 0x00003000 135 136 #define CM_CH1_SRATE_176K 0x00000800 137 #define CM_CH1_SRATE_88K 0x00000400 138 #define CM_CH0_SRATE_176K 0x00000200 139 #define CM_CH0_SRATE_88K 0x00000100 140 141 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */ 142 143 #define CM_CH1FMT_MASK 0x0000000C 144 #define CM_CH1FMT_SHIFT 2 145 #define CM_CH0FMT_MASK 0x00000003 146 #define CM_CH0FMT_SHIFT 0 147 148 #define CM_REG_INT_HLDCLR 0x0C 149 #define CM_CHIP_MASK2 0xff000000 150 #define CM_CHIP_039 0x04000000 151 #define CM_CHIP_039_6CH 0x01000000 152 #define CM_CHIP_055 0x08000000 153 #define CM_CHIP_8768 0x20000000 154 #define CM_TDMA_INT_EN 0x00040000 155 #define CM_CH1_INT_EN 0x00020000 156 #define CM_CH0_INT_EN 0x00010000 157 #define CM_INT_HOLD 0x00000002 158 #define CM_INT_CLEAR 0x00000001 159 160 #define CM_REG_INT_STATUS 0x10 161 #define CM_INTR 0x80000000 162 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */ 163 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */ 164 #define CM_UARTINT 0x00010000 165 #define CM_LTDMAINT 0x00008000 166 #define CM_HTDMAINT 0x00004000 167 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */ 168 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */ 169 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */ 170 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */ 171 #define CM_CH1BUSY 0x00000008 172 #define CM_CH0BUSY 0x00000004 173 #define CM_CHINT1 0x00000002 174 #define CM_CHINT0 0x00000001 175 176 #define CM_REG_LEGACY_CTRL 0x14 177 #define CM_NXCHG 0x80000000 /* h/w multi channels? */ 178 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */ 179 #define CM_VMPU_330 0x00000000 180 #define CM_VMPU_320 0x20000000 181 #define CM_VMPU_310 0x40000000 182 #define CM_VMPU_300 0x60000000 183 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */ 184 #define CM_VSBSEL_220 0x00000000 185 #define CM_VSBSEL_240 0x04000000 186 #define CM_VSBSEL_260 0x08000000 187 #define CM_VSBSEL_280 0x0C000000 188 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */ 189 #define CM_FMSEL_388 0x00000000 190 #define CM_FMSEL_3C8 0x01000000 191 #define CM_FMSEL_3E0 0x02000000 192 #define CM_FMSEL_3E8 0x03000000 193 #define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */ 194 #define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */ 195 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */ 196 #define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */ 197 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */ 198 #define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */ 199 200 #define CM_REG_MISC_CTRL 0x18 201 #define CM_PWD 0x80000000 202 #define CM_RESET 0x40000000 203 #define CM_SFIL_MASK 0x30000000 204 #define CM_TXVX 0x08000000 205 #define CM_N4SPK3D 0x04000000 /* 4ch output */ 206 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */ 207 #define CM_SPDIF48K 0x01000000 /* write */ 208 #define CM_SPATUS48K 0x01000000 /* read */ 209 #define CM_ENDBDAC 0x00800000 /* enable dual dac */ 210 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */ 211 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */ 212 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */ 213 #define CM_FM_EN 0x00080000 /* enalbe FM */ 214 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */ 215 #define CM_VIDWPDSB 0x00010000 216 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */ 217 #define CM_MASK_EN 0x00004000 218 #define CM_VIDWPPRT 0x00002000 219 #define CM_SFILENB 0x00001000 220 #define CM_MMODE_MASK 0x00000E00 221 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */ 222 #define CM_ENCENTER 0x00000080 223 #define CM_FLINKON 0x00000040 224 #define CM_FLINKOFF 0x00000020 225 #define CM_MIDSMP 0x00000010 226 #define CM_UPDDMA_MASK 0x0000000C 227 #define CM_TWAIT_MASK 0x00000003 228 229 /* byte */ 230 #define CM_REG_MIXER0 0x20 231 232 #define CM_REG_SB16_DATA 0x22 233 #define CM_REG_SB16_ADDR 0x23 234 235 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */ 236 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */ 237 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */ 238 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */ 239 240 #define CM_REG_MIXER1 0x24 241 #define CM_FMMUTE 0x80 /* mute FM */ 242 #define CM_FMMUTE_SHIFT 7 243 #define CM_WSMUTE 0x40 /* mute PCM */ 244 #define CM_WSMUTE_SHIFT 6 245 #define CM_SPK4 0x20 /* lin-in -> rear line out */ 246 #define CM_SPK4_SHIFT 5 247 #define CM_REAR2FRONT 0x10 /* exchange rear/front */ 248 #define CM_REAR2FRONT_SHIFT 4 249 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */ 250 #define CM_WAVEINL_SHIFT 3 251 #define CM_WAVEINR 0x04 /* digical wave rec. right */ 252 #define CM_WAVEINR_SHIFT 2 253 #define CM_X3DEN 0x02 /* 3D surround enable */ 254 #define CM_X3DEN_SHIFT 1 255 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */ 256 #define CM_CDPLAY_SHIFT 0 257 258 #define CM_REG_MIXER2 0x25 259 #define CM_RAUXREN 0x80 /* AUX right capture */ 260 #define CM_RAUXREN_SHIFT 7 261 #define CM_RAUXLEN 0x40 /* AUX left capture */ 262 #define CM_RAUXLEN_SHIFT 6 263 #define CM_VAUXRM 0x20 /* AUX right mute */ 264 #define CM_VAUXRM_SHIFT 5 265 #define CM_VAUXLM 0x10 /* AUX left mute */ 266 #define CM_VAUXLM_SHIFT 4 267 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */ 268 #define CM_VADMIC_SHIFT 1 269 #define CM_MICGAINZ 0x01 /* mic boost */ 270 #define CM_MICGAINZ_SHIFT 0 271 272 #define CM_REG_AUX_VOL 0x26 273 #define CM_VAUXL_MASK 0xf0 274 #define CM_VAUXR_MASK 0x0f 275 276 #define CM_REG_MISC 0x27 277 #define CM_XGPO1 0x20 278 // #define CM_XGPBIO 0x04 279 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */ 280 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */ 281 #define CM_SPDVALID 0x02 /* spdif input valid check */ 282 #define CM_DMAUTO 0x01 283 284 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */ 285 /* 286 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738 287 * or identical with AC97 codec? 288 */ 289 #define CM_REG_EXTERN_CODEC CM_REG_AC97 290 291 /* 292 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6) 293 */ 294 #define CM_REG_MPU_PCI 0x40 295 296 /* 297 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6) 298 */ 299 #define CM_REG_FM_PCI 0x50 300 301 /* 302 * access from SB-mixer port 303 */ 304 #define CM_REG_EXTENT_IND 0xf0 305 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */ 306 #define CM_VPHONE_SHIFT 5 307 #define CM_VPHOM 0x10 /* Phone mute control */ 308 #define CM_VSPKM 0x08 /* Speaker mute control, default high */ 309 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */ 310 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */ 311 #define CM_VADMIC3 0x01 /* Mic record boost */ 312 313 /* 314 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738): 315 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL 316 * unit (readonly?). 317 */ 318 #define CM_REG_PLL 0xf8 319 320 /* 321 * extended registers 322 */ 323 #define CM_REG_CH0_FRAME1 0x80 /* base address */ 324 #define CM_REG_CH0_FRAME2 0x84 325 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */ 326 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */ 327 #define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */ 328 #define CM_CHB3D8C 0x20 /* 7.1 channels support */ 329 #define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */ 330 #define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */ 331 #define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */ 332 #define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */ 333 #define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */ 334 335 /* 336 * size of i/o region 337 */ 338 #define CM_EXTENT_CODEC 0x100 339 #define CM_EXTENT_MIDI 0x2 340 #define CM_EXTENT_SYNTH 0x4 341 342 343 /* 344 * channels for playback / capture 345 */ 346 #define CM_CH_PLAY 0 347 #define CM_CH_CAPT 1 348 349 /* 350 * flags to check device open/close 351 */ 352 #define CM_OPEN_NONE 0 353 #define CM_OPEN_CH_MASK 0x01 354 #define CM_OPEN_DAC 0x10 355 #define CM_OPEN_ADC 0x20 356 #define CM_OPEN_SPDIF 0x40 357 #define CM_OPEN_MCHAN 0x80 358 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC) 359 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC) 360 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN) 361 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC) 362 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF) 363 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF) 364 365 366 #if CM_CH_PLAY == 1 367 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K 368 #define CM_PLAYBACK_SPDF CM_SPDF_1 369 #define CM_CAPTURE_SPDF CM_SPDF_0 370 #else 371 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K 372 #define CM_PLAYBACK_SPDF CM_SPDF_0 373 #define CM_CAPTURE_SPDF CM_SPDF_1 374 #endif 375 376 377 /* 378 * driver data 379 */ 380 381 typedef struct snd_stru_cmipci cmipci_t; 382 typedef struct snd_stru_cmipci_pcm cmipci_pcm_t; 383 384 struct snd_stru_cmipci_pcm { 385 snd_pcm_substream_t *substream; 386 int running; /* dac/adc running? */ 387 unsigned int dma_size; /* in frames */ 388 unsigned int period_size; /* in frames */ 389 unsigned int offset; /* physical address of the buffer */ 390 unsigned int fmt; /* format bits */ 391 int ch; /* channel (0/1) */ 392 unsigned int is_dac; /* is dac? */ 393 int bytes_per_frame; 394 int shift; 395 }; 396 397 /* mixer elements toggled/resumed during ac3 playback */ 398 struct cmipci_mixer_auto_switches { 399 const char *name; /* switch to toggle */ 400 int toggle_on; /* value to change when ac3 mode */ 401 }; 402 static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = { 403 {"PCM Playback Switch", 0}, 404 {"IEC958 Output Switch", 1}, 405 {"IEC958 Mix Analog", 0}, 406 // {"IEC958 Out To DAC", 1}, // no longer used 407 {"IEC958 Loop", 0}, 408 }; 409 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer) 410 411 struct snd_stru_cmipci { 412 snd_card_t *card; 413 414 struct pci_dev *pci; 415 unsigned int device; /* device ID */ 416 int irq; 417 418 unsigned long iobase; 419 unsigned int ctrl; /* FUNCTRL0 current value */ 420 421 snd_pcm_t *pcm; /* DAC/ADC PCM */ 422 snd_pcm_t *pcm2; /* 2nd DAC */ 423 snd_pcm_t *pcm_spdif; /* SPDIF */ 424 425 int chip_version; 426 int max_channels; 427 unsigned int has_dual_dac: 1; 428 unsigned int can_ac3_sw: 1; 429 unsigned int can_ac3_hw: 1; 430 unsigned int can_multi_ch: 1; 431 unsigned int do_soft_ac3: 1; 432 433 unsigned int spdif_playback_avail: 1; /* spdif ready? */ 434 unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */ 435 int spdif_counter; /* for software AC3 */ 436 437 unsigned int dig_status; 438 unsigned int dig_pcm_status; 439 440 snd_pcm_hardware_t *hw_info[3]; /* for playbacks */ 441 442 int opened[2]; /* open mode */ 443 struct semaphore open_mutex; 444 445 unsigned int mixer_insensitive: 1; 446 snd_kcontrol_t *mixer_res_ctl[CM_SAVED_MIXERS]; 447 int mixer_res_status[CM_SAVED_MIXERS]; 448 449 opl3_t *opl3; 450 snd_hwdep_t *opl3hwdep; 451 452 cmipci_pcm_t channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */ 453 454 /* external MIDI */ 455 snd_rawmidi_t *rmidi; 456 457 #ifdef SUPPORT_JOYSTICK 458 struct gameport *gameport; 459 #endif 460 461 spinlock_t reg_lock; 462 }; 463 464 465 /* read/write operations for dword register */ 466 static inline void snd_cmipci_write(cmipci_t *cm, unsigned int cmd, unsigned int data) 467 { 468 outl(data, cm->iobase + cmd); 469 } 470 471 static inline unsigned int snd_cmipci_read(cmipci_t *cm, unsigned int cmd) 472 { 473 return inl(cm->iobase + cmd); 474 } 475 476 /* read/write operations for word register */ 477 static inline void snd_cmipci_write_w(cmipci_t *cm, unsigned int cmd, unsigned short data) 478 { 479 outw(data, cm->iobase + cmd); 480 } 481 482 static inline unsigned short snd_cmipci_read_w(cmipci_t *cm, unsigned int cmd) 483 { 484 return inw(cm->iobase + cmd); 485 } 486 487 /* read/write operations for byte register */ 488 static inline void snd_cmipci_write_b(cmipci_t *cm, unsigned int cmd, unsigned char data) 489 { 490 outb(data, cm->iobase + cmd); 491 } 492 493 static inline unsigned char snd_cmipci_read_b(cmipci_t *cm, unsigned int cmd) 494 { 495 return inb(cm->iobase + cmd); 496 } 497 498 /* bit operations for dword register */ 499 static int snd_cmipci_set_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag) 500 { 501 unsigned int val, oval; 502 val = oval = inl(cm->iobase + cmd); 503 val |= flag; 504 if (val == oval) 505 return 0; 506 outl(val, cm->iobase + cmd); 507 return 1; 508 } 509 510 static int snd_cmipci_clear_bit(cmipci_t *cm, unsigned int cmd, unsigned int flag) 511 { 512 unsigned int val, oval; 513 val = oval = inl(cm->iobase + cmd); 514 val &= ~flag; 515 if (val == oval) 516 return 0; 517 outl(val, cm->iobase + cmd); 518 return 1; 519 } 520 521 /* bit operations for byte register */ 522 static int snd_cmipci_set_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag) 523 { 524 unsigned char val, oval; 525 val = oval = inb(cm->iobase + cmd); 526 val |= flag; 527 if (val == oval) 528 return 0; 529 outb(val, cm->iobase + cmd); 530 return 1; 531 } 532 533 static int snd_cmipci_clear_bit_b(cmipci_t *cm, unsigned int cmd, unsigned char flag) 534 { 535 unsigned char val, oval; 536 val = oval = inb(cm->iobase + cmd); 537 val &= ~flag; 538 if (val == oval) 539 return 0; 540 outb(val, cm->iobase + cmd); 541 return 1; 542 } 543 544 545 /* 546 * PCM interface 547 */ 548 549 /* 550 * calculate frequency 551 */ 552 553 static unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 }; 554 555 static unsigned int snd_cmipci_rate_freq(unsigned int rate) 556 { 557 unsigned int i; 558 for (i = 0; i < ARRAY_SIZE(rates); i++) { 559 if (rates[i] == rate) 560 return i; 561 } 562 snd_BUG(); 563 return 0; 564 } 565 566 #ifdef USE_VAR48KRATE 567 /* 568 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???) 569 * does it this way .. maybe not. Never get any information from C-Media about 570 * that <werner@suse.de>. 571 */ 572 static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n) 573 { 574 unsigned int delta, tolerance; 575 int xm, xn, xr; 576 577 for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5)) 578 rate <<= 1; 579 *n = -1; 580 if (*r > 0xff) 581 goto out; 582 tolerance = rate*CM_TOLERANCE_RATE; 583 584 for (xn = (1+2); xn < (0x1f+2); xn++) { 585 for (xm = (1+2); xm < (0xff+2); xm++) { 586 xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn; 587 588 if (xr < rate) 589 delta = rate - xr; 590 else 591 delta = xr - rate; 592 593 /* 594 * If we found one, remember this, 595 * and try to find a closer one 596 */ 597 if (delta < tolerance) { 598 tolerance = delta; 599 *m = xm - 2; 600 *n = xn - 2; 601 } 602 } 603 } 604 out: 605 return (*n > -1); 606 } 607 608 /* 609 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff 610 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen 611 * at the register CM_REG_FUNCTRL1 (0x04). 612 * Problem: other ways are also possible (any information about that?) 613 */ 614 static void snd_cmipci_set_pll(cmipci_t *cm, unsigned int rate, unsigned int slot) 615 { 616 unsigned int reg = CM_REG_PLL + slot; 617 /* 618 * Guess that this programs at reg. 0x04 the pos 15:13/12:10 619 * for DSFC/ASFC (000 upto 111). 620 */ 621 622 /* FIXME: Init (Do we've to set an other register first before programming?) */ 623 624 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */ 625 snd_cmipci_write_b(cm, reg, rate>>8); 626 snd_cmipci_write_b(cm, reg, rate&0xff); 627 628 /* FIXME: Setup (Do we've to set an other register first to enable this?) */ 629 } 630 #endif /* USE_VAR48KRATE */ 631 632 static int snd_cmipci_hw_params(snd_pcm_substream_t * substream, 633 snd_pcm_hw_params_t * hw_params) 634 { 635 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 636 } 637 638 static int snd_cmipci_playback2_hw_params(snd_pcm_substream_t * substream, 639 snd_pcm_hw_params_t * hw_params) 640 { 641 cmipci_t *cm = snd_pcm_substream_chip(substream); 642 if (params_channels(hw_params) > 2) { 643 down(&cm->open_mutex); 644 if (cm->opened[CM_CH_PLAY]) { 645 up(&cm->open_mutex); 646 return -EBUSY; 647 } 648 /* reserve the channel A */ 649 cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI; 650 up(&cm->open_mutex); 651 } 652 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 653 } 654 655 static void snd_cmipci_ch_reset(cmipci_t *cm, int ch) 656 { 657 int reset = CM_RST_CH0 << (cm->channel[ch].ch); 658 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); 659 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); 660 udelay(10); 661 } 662 663 static int snd_cmipci_hw_free(snd_pcm_substream_t * substream) 664 { 665 return snd_pcm_lib_free_pages(substream); 666 } 667 668 669 /* 670 */ 671 672 static unsigned int hw_channels[] = {1, 2, 4, 5, 6, 8}; 673 static snd_pcm_hw_constraint_list_t hw_constraints_channels_4 = { 674 .count = 3, 675 .list = hw_channels, 676 .mask = 0, 677 }; 678 static snd_pcm_hw_constraint_list_t hw_constraints_channels_6 = { 679 .count = 5, 680 .list = hw_channels, 681 .mask = 0, 682 }; 683 static snd_pcm_hw_constraint_list_t hw_constraints_channels_8 = { 684 .count = 6, 685 .list = hw_channels, 686 .mask = 0, 687 }; 688 689 static int set_dac_channels(cmipci_t *cm, cmipci_pcm_t *rec, int channels) 690 { 691 if (channels > 2) { 692 if (! cm->can_multi_ch) 693 return -EINVAL; 694 if (rec->fmt != 0x03) /* stereo 16bit only */ 695 return -EINVAL; 696 697 spin_lock_irq(&cm->reg_lock); 698 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); 699 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 700 if (channels > 4) { 701 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 702 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 703 } else { 704 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 705 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 706 } 707 if (channels >= 6) { 708 snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 709 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); 710 } else { 711 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 712 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); 713 } 714 if (cm->chip_version == 68) { 715 if (channels == 8) { 716 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C); 717 } else { 718 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL_8768, CM_CHB3D8C); 719 } 720 } 721 spin_unlock_irq(&cm->reg_lock); 722 723 } else { 724 if (cm->can_multi_ch) { 725 spin_lock_irq(&cm->reg_lock); 726 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG); 727 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D); 728 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C); 729 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C); 730 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENCENTER); 731 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 732 spin_unlock_irq(&cm->reg_lock); 733 } 734 } 735 return 0; 736 } 737 738 739 /* 740 * prepare playback/capture channel 741 * channel to be used must have been set in rec->ch. 742 */ 743 static int snd_cmipci_pcm_prepare(cmipci_t *cm, cmipci_pcm_t *rec, 744 snd_pcm_substream_t *substream) 745 { 746 unsigned int reg, freq, val; 747 snd_pcm_runtime_t *runtime = substream->runtime; 748 749 rec->fmt = 0; 750 rec->shift = 0; 751 if (snd_pcm_format_width(runtime->format) >= 16) { 752 rec->fmt |= 0x02; 753 if (snd_pcm_format_width(runtime->format) > 16) 754 rec->shift++; /* 24/32bit */ 755 } 756 if (runtime->channels > 1) 757 rec->fmt |= 0x01; 758 if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) { 759 snd_printd("cannot set dac channels\n"); 760 return -EINVAL; 761 } 762 763 rec->offset = runtime->dma_addr; 764 /* buffer and period sizes in frame */ 765 rec->dma_size = runtime->buffer_size << rec->shift; 766 rec->period_size = runtime->period_size << rec->shift; 767 if (runtime->channels > 2) { 768 /* multi-channels */ 769 rec->dma_size = (rec->dma_size * runtime->channels) / 2; 770 rec->period_size = (rec->period_size * runtime->channels) / 2; 771 } 772 773 spin_lock_irq(&cm->reg_lock); 774 775 /* set buffer address */ 776 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; 777 snd_cmipci_write(cm, reg, rec->offset); 778 /* program sample counts */ 779 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; 780 snd_cmipci_write_w(cm, reg, rec->dma_size - 1); 781 snd_cmipci_write_w(cm, reg + 2, rec->period_size - 1); 782 783 /* set adc/dac flag */ 784 val = rec->ch ? CM_CHADC1 : CM_CHADC0; 785 if (rec->is_dac) 786 cm->ctrl &= ~val; 787 else 788 cm->ctrl |= val; 789 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 790 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); 791 792 /* set sample rate */ 793 freq = snd_cmipci_rate_freq(runtime->rate); 794 val = snd_cmipci_read(cm, CM_REG_FUNCTRL1); 795 if (rec->ch) { 796 val &= ~CM_ASFC_MASK; 797 val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK; 798 } else { 799 val &= ~CM_DSFC_MASK; 800 val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK; 801 } 802 snd_cmipci_write(cm, CM_REG_FUNCTRL1, val); 803 //snd_printd("cmipci: functrl1 = %08x\n", val); 804 805 /* set format */ 806 val = snd_cmipci_read(cm, CM_REG_CHFORMAT); 807 if (rec->ch) { 808 val &= ~CM_CH1FMT_MASK; 809 val |= rec->fmt << CM_CH1FMT_SHIFT; 810 } else { 811 val &= ~CM_CH0FMT_MASK; 812 val |= rec->fmt << CM_CH0FMT_SHIFT; 813 } 814 snd_cmipci_write(cm, CM_REG_CHFORMAT, val); 815 //snd_printd("cmipci: chformat = %08x\n", val); 816 817 rec->running = 0; 818 spin_unlock_irq(&cm->reg_lock); 819 820 return 0; 821 } 822 823 /* 824 * PCM trigger/stop 825 */ 826 static int snd_cmipci_pcm_trigger(cmipci_t *cm, cmipci_pcm_t *rec, 827 snd_pcm_substream_t *substream, int cmd) 828 { 829 unsigned int inthld, chen, reset, pause; 830 int result = 0; 831 832 inthld = CM_CH0_INT_EN << rec->ch; 833 chen = CM_CHEN0 << rec->ch; 834 reset = CM_RST_CH0 << rec->ch; 835 pause = CM_PAUSE0 << rec->ch; 836 837 spin_lock(&cm->reg_lock); 838 switch (cmd) { 839 case SNDRV_PCM_TRIGGER_START: 840 rec->running = 1; 841 /* set interrupt */ 842 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld); 843 cm->ctrl |= chen; 844 /* enable channel */ 845 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 846 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl); 847 break; 848 case SNDRV_PCM_TRIGGER_STOP: 849 rec->running = 0; 850 /* disable interrupt */ 851 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld); 852 /* reset */ 853 cm->ctrl &= ~chen; 854 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset); 855 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset); 856 break; 857 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 858 cm->ctrl |= pause; 859 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 860 break; 861 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 862 cm->ctrl &= ~pause; 863 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl); 864 break; 865 default: 866 result = -EINVAL; 867 break; 868 } 869 spin_unlock(&cm->reg_lock); 870 return result; 871 } 872 873 /* 874 * return the current pointer 875 */ 876 static snd_pcm_uframes_t snd_cmipci_pcm_pointer(cmipci_t *cm, cmipci_pcm_t *rec, 877 snd_pcm_substream_t *substream) 878 { 879 size_t ptr; 880 unsigned int reg; 881 if (!rec->running) 882 return 0; 883 #if 1 // this seems better.. 884 reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2; 885 ptr = rec->dma_size - (snd_cmipci_read_w(cm, reg) + 1); 886 ptr >>= rec->shift; 887 #else 888 reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1; 889 ptr = snd_cmipci_read(cm, reg) - rec->offset; 890 ptr = bytes_to_frames(substream->runtime, ptr); 891 #endif 892 if (substream->runtime->channels > 2) 893 ptr = (ptr * 2) / substream->runtime->channels; 894 return ptr; 895 } 896 897 /* 898 * playback 899 */ 900 901 static int snd_cmipci_playback_trigger(snd_pcm_substream_t *substream, 902 int cmd) 903 { 904 cmipci_t *cm = snd_pcm_substream_chip(substream); 905 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], substream, cmd); 906 } 907 908 static snd_pcm_uframes_t snd_cmipci_playback_pointer(snd_pcm_substream_t *substream) 909 { 910 cmipci_t *cm = snd_pcm_substream_chip(substream); 911 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream); 912 } 913 914 915 916 /* 917 * capture 918 */ 919 920 static int snd_cmipci_capture_trigger(snd_pcm_substream_t *substream, 921 int cmd) 922 { 923 cmipci_t *cm = snd_pcm_substream_chip(substream); 924 return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], substream, cmd); 925 } 926 927 static snd_pcm_uframes_t snd_cmipci_capture_pointer(snd_pcm_substream_t *substream) 928 { 929 cmipci_t *cm = snd_pcm_substream_chip(substream); 930 return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream); 931 } 932 933 934 /* 935 * hw preparation for spdif 936 */ 937 938 static int snd_cmipci_spdif_default_info(snd_kcontrol_t *kcontrol, 939 snd_ctl_elem_info_t *uinfo) 940 { 941 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 942 uinfo->count = 1; 943 return 0; 944 } 945 946 static int snd_cmipci_spdif_default_get(snd_kcontrol_t *kcontrol, 947 snd_ctl_elem_value_t *ucontrol) 948 { 949 cmipci_t *chip = snd_kcontrol_chip(kcontrol); 950 int i; 951 952 spin_lock_irq(&chip->reg_lock); 953 for (i = 0; i < 4; i++) 954 ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff; 955 spin_unlock_irq(&chip->reg_lock); 956 return 0; 957 } 958 959 static int snd_cmipci_spdif_default_put(snd_kcontrol_t * kcontrol, 960 snd_ctl_elem_value_t * ucontrol) 961 { 962 cmipci_t *chip = snd_kcontrol_chip(kcontrol); 963 int i, change; 964 unsigned int val; 965 966 val = 0; 967 spin_lock_irq(&chip->reg_lock); 968 for (i = 0; i < 4; i++) 969 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); 970 change = val != chip->dig_status; 971 chip->dig_status = val; 972 spin_unlock_irq(&chip->reg_lock); 973 return change; 974 } 975 976 static snd_kcontrol_new_t snd_cmipci_spdif_default __devinitdata = 977 { 978 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 979 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 980 .info = snd_cmipci_spdif_default_info, 981 .get = snd_cmipci_spdif_default_get, 982 .put = snd_cmipci_spdif_default_put 983 }; 984 985 static int snd_cmipci_spdif_mask_info(snd_kcontrol_t *kcontrol, 986 snd_ctl_elem_info_t *uinfo) 987 { 988 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 989 uinfo->count = 1; 990 return 0; 991 } 992 993 static int snd_cmipci_spdif_mask_get(snd_kcontrol_t * kcontrol, 994 snd_ctl_elem_value_t *ucontrol) 995 { 996 ucontrol->value.iec958.status[0] = 0xff; 997 ucontrol->value.iec958.status[1] = 0xff; 998 ucontrol->value.iec958.status[2] = 0xff; 999 ucontrol->value.iec958.status[3] = 0xff; 1000 return 0; 1001 } 1002 1003 static snd_kcontrol_new_t snd_cmipci_spdif_mask __devinitdata = 1004 { 1005 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1006 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1007 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 1008 .info = snd_cmipci_spdif_mask_info, 1009 .get = snd_cmipci_spdif_mask_get, 1010 }; 1011 1012 static int snd_cmipci_spdif_stream_info(snd_kcontrol_t *kcontrol, 1013 snd_ctl_elem_info_t *uinfo) 1014 { 1015 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1016 uinfo->count = 1; 1017 return 0; 1018 } 1019 1020 static int snd_cmipci_spdif_stream_get(snd_kcontrol_t *kcontrol, 1021 snd_ctl_elem_value_t *ucontrol) 1022 { 1023 cmipci_t *chip = snd_kcontrol_chip(kcontrol); 1024 int i; 1025 1026 spin_lock_irq(&chip->reg_lock); 1027 for (i = 0; i < 4; i++) 1028 ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff; 1029 spin_unlock_irq(&chip->reg_lock); 1030 return 0; 1031 } 1032 1033 static int snd_cmipci_spdif_stream_put(snd_kcontrol_t *kcontrol, 1034 snd_ctl_elem_value_t *ucontrol) 1035 { 1036 cmipci_t *chip = snd_kcontrol_chip(kcontrol); 1037 int i, change; 1038 unsigned int val; 1039 1040 val = 0; 1041 spin_lock_irq(&chip->reg_lock); 1042 for (i = 0; i < 4; i++) 1043 val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); 1044 change = val != chip->dig_pcm_status; 1045 chip->dig_pcm_status = val; 1046 spin_unlock_irq(&chip->reg_lock); 1047 return change; 1048 } 1049 1050 static snd_kcontrol_new_t snd_cmipci_spdif_stream __devinitdata = 1051 { 1052 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 1053 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1054 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 1055 .info = snd_cmipci_spdif_stream_info, 1056 .get = snd_cmipci_spdif_stream_get, 1057 .put = snd_cmipci_spdif_stream_put 1058 }; 1059 1060 /* 1061 */ 1062 1063 /* save mixer setting and mute for AC3 playback */ 1064 static int save_mixer_state(cmipci_t *cm) 1065 { 1066 if (! cm->mixer_insensitive) { 1067 snd_ctl_elem_value_t *val; 1068 unsigned int i; 1069 1070 val = kmalloc(sizeof(*val), GFP_ATOMIC); 1071 if (!val) 1072 return -ENOMEM; 1073 for (i = 0; i < CM_SAVED_MIXERS; i++) { 1074 snd_kcontrol_t *ctl = cm->mixer_res_ctl[i]; 1075 if (ctl) { 1076 int event; 1077 memset(val, 0, sizeof(*val)); 1078 ctl->get(ctl, val); 1079 cm->mixer_res_status[i] = val->value.integer.value[0]; 1080 val->value.integer.value[0] = cm_saved_mixer[i].toggle_on; 1081 event = SNDRV_CTL_EVENT_MASK_INFO; 1082 if (cm->mixer_res_status[i] != val->value.integer.value[0]) { 1083 ctl->put(ctl, val); /* toggle */ 1084 event |= SNDRV_CTL_EVENT_MASK_VALUE; 1085 } 1086 ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1087 snd_ctl_notify(cm->card, event, &ctl->id); 1088 } 1089 } 1090 kfree(val); 1091 cm->mixer_insensitive = 1; 1092 } 1093 return 0; 1094 } 1095 1096 1097 /* restore the previously saved mixer status */ 1098 static void restore_mixer_state(cmipci_t *cm) 1099 { 1100 if (cm->mixer_insensitive) { 1101 snd_ctl_elem_value_t *val; 1102 unsigned int i; 1103 1104 val = kmalloc(sizeof(*val), GFP_KERNEL); 1105 if (!val) 1106 return; 1107 cm->mixer_insensitive = 0; /* at first clear this; 1108 otherwise the changes will be ignored */ 1109 for (i = 0; i < CM_SAVED_MIXERS; i++) { 1110 snd_kcontrol_t *ctl = cm->mixer_res_ctl[i]; 1111 if (ctl) { 1112 int event; 1113 1114 memset(val, 0, sizeof(*val)); 1115 ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1116 ctl->get(ctl, val); 1117 event = SNDRV_CTL_EVENT_MASK_INFO; 1118 if (val->value.integer.value[0] != cm->mixer_res_status[i]) { 1119 val->value.integer.value[0] = cm->mixer_res_status[i]; 1120 ctl->put(ctl, val); 1121 event |= SNDRV_CTL_EVENT_MASK_VALUE; 1122 } 1123 snd_ctl_notify(cm->card, event, &ctl->id); 1124 } 1125 } 1126 kfree(val); 1127 } 1128 } 1129 1130 /* spinlock held! */ 1131 static void setup_ac3(cmipci_t *cm, snd_pcm_substream_t *subs, int do_ac3, int rate) 1132 { 1133 if (do_ac3) { 1134 /* AC3EN for 037 */ 1135 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); 1136 /* AC3EN for 039 */ 1137 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); 1138 1139 if (cm->can_ac3_hw) { 1140 /* SPD24SEL for 037, 0x02 */ 1141 /* SPD24SEL for 039, 0x20, but cannot be set */ 1142 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1143 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1144 } else { /* can_ac3_sw */ 1145 /* SPD32SEL for 037 & 039, 0x20 */ 1146 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1147 /* set 176K sample rate to fix 033 HW bug */ 1148 if (cm->chip_version == 33) { 1149 if (rate >= 48000) { 1150 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); 1151 } else { 1152 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); 1153 } 1154 } 1155 } 1156 1157 } else { 1158 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1); 1159 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2); 1160 1161 if (cm->can_ac3_hw) { 1162 /* chip model >= 37 */ 1163 if (snd_pcm_format_width(subs->runtime->format) > 16) { 1164 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1165 snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1166 } else { 1167 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1168 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1169 } 1170 } else { 1171 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL); 1172 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL); 1173 snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K); 1174 } 1175 } 1176 } 1177 1178 static int setup_spdif_playback(cmipci_t *cm, snd_pcm_substream_t *subs, int up, int do_ac3) 1179 { 1180 int rate, err; 1181 1182 rate = subs->runtime->rate; 1183 1184 if (up && do_ac3) 1185 if ((err = save_mixer_state(cm)) < 0) 1186 return err; 1187 1188 spin_lock_irq(&cm->reg_lock); 1189 cm->spdif_playback_avail = up; 1190 if (up) { 1191 /* they are controlled via "IEC958 Output Switch" */ 1192 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ 1193 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ 1194 if (cm->spdif_playback_enabled) 1195 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 1196 setup_ac3(cm, subs, do_ac3, rate); 1197 1198 if (rate == 48000) 1199 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); 1200 else 1201 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97); 1202 1203 } else { 1204 /* they are controlled via "IEC958 Output Switch" */ 1205 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */ 1206 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */ 1207 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 1208 setup_ac3(cm, subs, 0, 0); 1209 } 1210 spin_unlock_irq(&cm->reg_lock); 1211 return 0; 1212 } 1213 1214 1215 /* 1216 * preparation 1217 */ 1218 1219 /* playback - enable spdif only on the certain condition */ 1220 static int snd_cmipci_playback_prepare(snd_pcm_substream_t *substream) 1221 { 1222 cmipci_t *cm = snd_pcm_substream_chip(substream); 1223 int rate = substream->runtime->rate; 1224 int err, do_spdif, do_ac3 = 0; 1225 1226 do_spdif = ((rate == 44100 || rate == 48000) && 1227 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE && 1228 substream->runtime->channels == 2); 1229 if (do_spdif && cm->can_ac3_hw) 1230 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; 1231 if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0) 1232 return err; 1233 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); 1234 } 1235 1236 /* playback (via device #2) - enable spdif always */ 1237 static int snd_cmipci_playback_spdif_prepare(snd_pcm_substream_t *substream) 1238 { 1239 cmipci_t *cm = snd_pcm_substream_chip(substream); 1240 int err, do_ac3; 1241 1242 if (cm->can_ac3_hw) 1243 do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO; 1244 else 1245 do_ac3 = 1; /* doesn't matter */ 1246 if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0) 1247 return err; 1248 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream); 1249 } 1250 1251 static int snd_cmipci_playback_hw_free(snd_pcm_substream_t *substream) 1252 { 1253 cmipci_t *cm = snd_pcm_substream_chip(substream); 1254 setup_spdif_playback(cm, substream, 0, 0); 1255 restore_mixer_state(cm); 1256 return snd_cmipci_hw_free(substream); 1257 } 1258 1259 /* capture */ 1260 static int snd_cmipci_capture_prepare(snd_pcm_substream_t *substream) 1261 { 1262 cmipci_t *cm = snd_pcm_substream_chip(substream); 1263 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); 1264 } 1265 1266 /* capture with spdif (via device #2) */ 1267 static int snd_cmipci_capture_spdif_prepare(snd_pcm_substream_t *substream) 1268 { 1269 cmipci_t *cm = snd_pcm_substream_chip(substream); 1270 1271 spin_lock_irq(&cm->reg_lock); 1272 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); 1273 spin_unlock_irq(&cm->reg_lock); 1274 1275 return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream); 1276 } 1277 1278 static int snd_cmipci_capture_spdif_hw_free(snd_pcm_substream_t *subs) 1279 { 1280 cmipci_t *cm = snd_pcm_substream_chip(subs); 1281 1282 spin_lock_irq(&cm->reg_lock); 1283 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF); 1284 spin_unlock_irq(&cm->reg_lock); 1285 1286 return snd_cmipci_hw_free(subs); 1287 } 1288 1289 1290 /* 1291 * interrupt handler 1292 */ 1293 static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id, struct pt_regs *regs) 1294 { 1295 cmipci_t *cm = dev_id; 1296 unsigned int status, mask = 0; 1297 1298 /* fastpath out, to ease interrupt sharing */ 1299 status = snd_cmipci_read(cm, CM_REG_INT_STATUS); 1300 if (!(status & CM_INTR)) 1301 return IRQ_NONE; 1302 1303 /* acknowledge interrupt */ 1304 spin_lock(&cm->reg_lock); 1305 if (status & CM_CHINT0) 1306 mask |= CM_CH0_INT_EN; 1307 if (status & CM_CHINT1) 1308 mask |= CM_CH1_INT_EN; 1309 snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask); 1310 snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask); 1311 spin_unlock(&cm->reg_lock); 1312 1313 if (cm->rmidi && (status & CM_UARTINT)) 1314 snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data, regs); 1315 1316 if (cm->pcm) { 1317 if ((status & CM_CHINT0) && cm->channel[0].running) 1318 snd_pcm_period_elapsed(cm->channel[0].substream); 1319 if ((status & CM_CHINT1) && cm->channel[1].running) 1320 snd_pcm_period_elapsed(cm->channel[1].substream); 1321 } 1322 return IRQ_HANDLED; 1323 } 1324 1325 /* 1326 * h/w infos 1327 */ 1328 1329 /* playback on channel A */ 1330 static snd_pcm_hardware_t snd_cmipci_playback = 1331 { 1332 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1333 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1334 SNDRV_PCM_INFO_MMAP_VALID), 1335 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1336 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, 1337 .rate_min = 5512, 1338 .rate_max = 48000, 1339 .channels_min = 1, 1340 .channels_max = 2, 1341 .buffer_bytes_max = (128*1024), 1342 .period_bytes_min = 64, 1343 .period_bytes_max = (128*1024), 1344 .periods_min = 2, 1345 .periods_max = 1024, 1346 .fifo_size = 0, 1347 }; 1348 1349 /* capture on channel B */ 1350 static snd_pcm_hardware_t snd_cmipci_capture = 1351 { 1352 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1353 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1354 SNDRV_PCM_INFO_MMAP_VALID), 1355 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1356 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, 1357 .rate_min = 5512, 1358 .rate_max = 48000, 1359 .channels_min = 1, 1360 .channels_max = 2, 1361 .buffer_bytes_max = (128*1024), 1362 .period_bytes_min = 64, 1363 .period_bytes_max = (128*1024), 1364 .periods_min = 2, 1365 .periods_max = 1024, 1366 .fifo_size = 0, 1367 }; 1368 1369 /* playback on channel B - stereo 16bit only? */ 1370 static snd_pcm_hardware_t snd_cmipci_playback2 = 1371 { 1372 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1373 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1374 SNDRV_PCM_INFO_MMAP_VALID), 1375 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1376 .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000, 1377 .rate_min = 5512, 1378 .rate_max = 48000, 1379 .channels_min = 2, 1380 .channels_max = 2, 1381 .buffer_bytes_max = (128*1024), 1382 .period_bytes_min = 64, 1383 .period_bytes_max = (128*1024), 1384 .periods_min = 2, 1385 .periods_max = 1024, 1386 .fifo_size = 0, 1387 }; 1388 1389 /* spdif playback on channel A */ 1390 static snd_pcm_hardware_t snd_cmipci_playback_spdif = 1391 { 1392 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1393 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1394 SNDRV_PCM_INFO_MMAP_VALID), 1395 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1396 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, 1397 .rate_min = 44100, 1398 .rate_max = 48000, 1399 .channels_min = 2, 1400 .channels_max = 2, 1401 .buffer_bytes_max = (128*1024), 1402 .period_bytes_min = 64, 1403 .period_bytes_max = (128*1024), 1404 .periods_min = 2, 1405 .periods_max = 1024, 1406 .fifo_size = 0, 1407 }; 1408 1409 /* spdif playback on channel A (32bit, IEC958 subframes) */ 1410 static snd_pcm_hardware_t snd_cmipci_playback_iec958_subframe = 1411 { 1412 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1413 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1414 SNDRV_PCM_INFO_MMAP_VALID), 1415 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1416 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, 1417 .rate_min = 44100, 1418 .rate_max = 48000, 1419 .channels_min = 2, 1420 .channels_max = 2, 1421 .buffer_bytes_max = (128*1024), 1422 .period_bytes_min = 64, 1423 .period_bytes_max = (128*1024), 1424 .periods_min = 2, 1425 .periods_max = 1024, 1426 .fifo_size = 0, 1427 }; 1428 1429 /* spdif capture on channel B */ 1430 static snd_pcm_hardware_t snd_cmipci_capture_spdif = 1431 { 1432 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1433 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE | 1434 SNDRV_PCM_INFO_MMAP_VALID), 1435 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1436 .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000, 1437 .rate_min = 44100, 1438 .rate_max = 48000, 1439 .channels_min = 2, 1440 .channels_max = 2, 1441 .buffer_bytes_max = (128*1024), 1442 .period_bytes_min = 64, 1443 .period_bytes_max = (128*1024), 1444 .periods_min = 2, 1445 .periods_max = 1024, 1446 .fifo_size = 0, 1447 }; 1448 1449 /* 1450 * check device open/close 1451 */ 1452 static int open_device_check(cmipci_t *cm, int mode, snd_pcm_substream_t *subs) 1453 { 1454 int ch = mode & CM_OPEN_CH_MASK; 1455 1456 /* FIXME: a file should wait until the device becomes free 1457 * when it's opened on blocking mode. however, since the current 1458 * pcm framework doesn't pass file pointer before actually opened, 1459 * we can't know whether blocking mode or not in open callback.. 1460 */ 1461 down(&cm->open_mutex); 1462 if (cm->opened[ch]) { 1463 up(&cm->open_mutex); 1464 return -EBUSY; 1465 } 1466 cm->opened[ch] = mode; 1467 cm->channel[ch].substream = subs; 1468 if (! (mode & CM_OPEN_DAC)) { 1469 /* disable dual DAC mode */ 1470 cm->channel[ch].is_dac = 0; 1471 spin_lock_irq(&cm->reg_lock); 1472 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); 1473 spin_unlock_irq(&cm->reg_lock); 1474 } 1475 up(&cm->open_mutex); 1476 return 0; 1477 } 1478 1479 static void close_device_check(cmipci_t *cm, int mode) 1480 { 1481 int ch = mode & CM_OPEN_CH_MASK; 1482 1483 down(&cm->open_mutex); 1484 if (cm->opened[ch] == mode) { 1485 if (cm->channel[ch].substream) { 1486 snd_cmipci_ch_reset(cm, ch); 1487 cm->channel[ch].running = 0; 1488 cm->channel[ch].substream = NULL; 1489 } 1490 cm->opened[ch] = 0; 1491 if (! cm->channel[ch].is_dac) { 1492 /* enable dual DAC mode again */ 1493 cm->channel[ch].is_dac = 1; 1494 spin_lock_irq(&cm->reg_lock); 1495 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC); 1496 spin_unlock_irq(&cm->reg_lock); 1497 } 1498 } 1499 up(&cm->open_mutex); 1500 } 1501 1502 /* 1503 */ 1504 1505 static int snd_cmipci_playback_open(snd_pcm_substream_t *substream) 1506 { 1507 cmipci_t *cm = snd_pcm_substream_chip(substream); 1508 snd_pcm_runtime_t *runtime = substream->runtime; 1509 int err; 1510 1511 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0) 1512 return err; 1513 runtime->hw = snd_cmipci_playback; 1514 runtime->hw.channels_max = cm->max_channels; 1515 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1516 cm->dig_pcm_status = cm->dig_status; 1517 return 0; 1518 } 1519 1520 static int snd_cmipci_capture_open(snd_pcm_substream_t *substream) 1521 { 1522 cmipci_t *cm = snd_pcm_substream_chip(substream); 1523 snd_pcm_runtime_t *runtime = substream->runtime; 1524 int err; 1525 1526 if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0) 1527 return err; 1528 runtime->hw = snd_cmipci_capture; 1529 if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording 1530 runtime->hw.rate_min = 41000; 1531 runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000; 1532 } 1533 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1534 return 0; 1535 } 1536 1537 static int snd_cmipci_playback2_open(snd_pcm_substream_t *substream) 1538 { 1539 cmipci_t *cm = snd_pcm_substream_chip(substream); 1540 snd_pcm_runtime_t *runtime = substream->runtime; 1541 int err; 1542 1543 if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */ 1544 return err; 1545 runtime->hw = snd_cmipci_playback2; 1546 down(&cm->open_mutex); 1547 if (! cm->opened[CM_CH_PLAY]) { 1548 if (cm->can_multi_ch) { 1549 runtime->hw.channels_max = cm->max_channels; 1550 if (cm->max_channels == 4) 1551 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4); 1552 else if (cm->max_channels == 6) 1553 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6); 1554 else if (cm->max_channels == 8) 1555 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8); 1556 } 1557 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000); 1558 } 1559 up(&cm->open_mutex); 1560 return 0; 1561 } 1562 1563 static int snd_cmipci_playback_spdif_open(snd_pcm_substream_t *substream) 1564 { 1565 cmipci_t *cm = snd_pcm_substream_chip(substream); 1566 snd_pcm_runtime_t *runtime = substream->runtime; 1567 int err; 1568 1569 if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */ 1570 return err; 1571 if (cm->can_ac3_hw) { 1572 runtime->hw = snd_cmipci_playback_spdif; 1573 if (cm->chip_version >= 37) 1574 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1575 } else { 1576 runtime->hw = snd_cmipci_playback_iec958_subframe; 1577 } 1578 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); 1579 cm->dig_pcm_status = cm->dig_status; 1580 return 0; 1581 } 1582 1583 static int snd_cmipci_capture_spdif_open(snd_pcm_substream_t * substream) 1584 { 1585 cmipci_t *cm = snd_pcm_substream_chip(substream); 1586 snd_pcm_runtime_t *runtime = substream->runtime; 1587 int err; 1588 1589 if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */ 1590 return err; 1591 runtime->hw = snd_cmipci_capture_spdif; 1592 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000); 1593 return 0; 1594 } 1595 1596 1597 /* 1598 */ 1599 1600 static int snd_cmipci_playback_close(snd_pcm_substream_t * substream) 1601 { 1602 cmipci_t *cm = snd_pcm_substream_chip(substream); 1603 close_device_check(cm, CM_OPEN_PLAYBACK); 1604 return 0; 1605 } 1606 1607 static int snd_cmipci_capture_close(snd_pcm_substream_t * substream) 1608 { 1609 cmipci_t *cm = snd_pcm_substream_chip(substream); 1610 close_device_check(cm, CM_OPEN_CAPTURE); 1611 return 0; 1612 } 1613 1614 static int snd_cmipci_playback2_close(snd_pcm_substream_t * substream) 1615 { 1616 cmipci_t *cm = snd_pcm_substream_chip(substream); 1617 close_device_check(cm, CM_OPEN_PLAYBACK2); 1618 close_device_check(cm, CM_OPEN_PLAYBACK_MULTI); 1619 return 0; 1620 } 1621 1622 static int snd_cmipci_playback_spdif_close(snd_pcm_substream_t * substream) 1623 { 1624 cmipci_t *cm = snd_pcm_substream_chip(substream); 1625 close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK); 1626 return 0; 1627 } 1628 1629 static int snd_cmipci_capture_spdif_close(snd_pcm_substream_t * substream) 1630 { 1631 cmipci_t *cm = snd_pcm_substream_chip(substream); 1632 close_device_check(cm, CM_OPEN_SPDIF_CAPTURE); 1633 return 0; 1634 } 1635 1636 1637 /* 1638 */ 1639 1640 static snd_pcm_ops_t snd_cmipci_playback_ops = { 1641 .open = snd_cmipci_playback_open, 1642 .close = snd_cmipci_playback_close, 1643 .ioctl = snd_pcm_lib_ioctl, 1644 .hw_params = snd_cmipci_hw_params, 1645 .hw_free = snd_cmipci_playback_hw_free, 1646 .prepare = snd_cmipci_playback_prepare, 1647 .trigger = snd_cmipci_playback_trigger, 1648 .pointer = snd_cmipci_playback_pointer, 1649 }; 1650 1651 static snd_pcm_ops_t snd_cmipci_capture_ops = { 1652 .open = snd_cmipci_capture_open, 1653 .close = snd_cmipci_capture_close, 1654 .ioctl = snd_pcm_lib_ioctl, 1655 .hw_params = snd_cmipci_hw_params, 1656 .hw_free = snd_cmipci_hw_free, 1657 .prepare = snd_cmipci_capture_prepare, 1658 .trigger = snd_cmipci_capture_trigger, 1659 .pointer = snd_cmipci_capture_pointer, 1660 }; 1661 1662 static snd_pcm_ops_t snd_cmipci_playback2_ops = { 1663 .open = snd_cmipci_playback2_open, 1664 .close = snd_cmipci_playback2_close, 1665 .ioctl = snd_pcm_lib_ioctl, 1666 .hw_params = snd_cmipci_playback2_hw_params, 1667 .hw_free = snd_cmipci_hw_free, 1668 .prepare = snd_cmipci_capture_prepare, /* channel B */ 1669 .trigger = snd_cmipci_capture_trigger, /* channel B */ 1670 .pointer = snd_cmipci_capture_pointer, /* channel B */ 1671 }; 1672 1673 static snd_pcm_ops_t snd_cmipci_playback_spdif_ops = { 1674 .open = snd_cmipci_playback_spdif_open, 1675 .close = snd_cmipci_playback_spdif_close, 1676 .ioctl = snd_pcm_lib_ioctl, 1677 .hw_params = snd_cmipci_hw_params, 1678 .hw_free = snd_cmipci_playback_hw_free, 1679 .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */ 1680 .trigger = snd_cmipci_playback_trigger, 1681 .pointer = snd_cmipci_playback_pointer, 1682 }; 1683 1684 static snd_pcm_ops_t snd_cmipci_capture_spdif_ops = { 1685 .open = snd_cmipci_capture_spdif_open, 1686 .close = snd_cmipci_capture_spdif_close, 1687 .ioctl = snd_pcm_lib_ioctl, 1688 .hw_params = snd_cmipci_hw_params, 1689 .hw_free = snd_cmipci_capture_spdif_hw_free, 1690 .prepare = snd_cmipci_capture_spdif_prepare, 1691 .trigger = snd_cmipci_capture_trigger, 1692 .pointer = snd_cmipci_capture_pointer, 1693 }; 1694 1695 1696 /* 1697 */ 1698 1699 static void snd_cmipci_pcm_free(snd_pcm_t *pcm) 1700 { 1701 snd_pcm_lib_preallocate_free_for_all(pcm); 1702 } 1703 1704 static int __devinit snd_cmipci_pcm_new(cmipci_t *cm, int device) 1705 { 1706 snd_pcm_t *pcm; 1707 int err; 1708 1709 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); 1710 if (err < 0) 1711 return err; 1712 1713 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops); 1714 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops); 1715 1716 pcm->private_data = cm; 1717 pcm->private_free = snd_cmipci_pcm_free; 1718 pcm->info_flags = 0; 1719 strcpy(pcm->name, "C-Media PCI DAC/ADC"); 1720 cm->pcm = pcm; 1721 1722 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1723 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1724 1725 return 0; 1726 } 1727 1728 static int __devinit snd_cmipci_pcm2_new(cmipci_t *cm, int device) 1729 { 1730 snd_pcm_t *pcm; 1731 int err; 1732 1733 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm); 1734 if (err < 0) 1735 return err; 1736 1737 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops); 1738 1739 pcm->private_data = cm; 1740 pcm->private_free = snd_cmipci_pcm_free; 1741 pcm->info_flags = 0; 1742 strcpy(pcm->name, "C-Media PCI 2nd DAC"); 1743 cm->pcm2 = pcm; 1744 1745 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1746 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1747 1748 return 0; 1749 } 1750 1751 static int __devinit snd_cmipci_pcm_spdif_new(cmipci_t *cm, int device) 1752 { 1753 snd_pcm_t *pcm; 1754 int err; 1755 1756 err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm); 1757 if (err < 0) 1758 return err; 1759 1760 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops); 1761 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops); 1762 1763 pcm->private_data = cm; 1764 pcm->private_free = snd_cmipci_pcm_free; 1765 pcm->info_flags = 0; 1766 strcpy(pcm->name, "C-Media PCI IEC958"); 1767 cm->pcm_spdif = pcm; 1768 1769 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1770 snd_dma_pci_data(cm->pci), 64*1024, 128*1024); 1771 1772 return 0; 1773 } 1774 1775 /* 1776 * mixer interface: 1777 * - CM8338/8738 has a compatible mixer interface with SB16, but 1778 * lack of some elements like tone control, i/o gain and AGC. 1779 * - Access to native registers: 1780 * - A 3D switch 1781 * - Output mute switches 1782 */ 1783 1784 static void snd_cmipci_mixer_write(cmipci_t *s, unsigned char idx, unsigned char data) 1785 { 1786 outb(idx, s->iobase + CM_REG_SB16_ADDR); 1787 outb(data, s->iobase + CM_REG_SB16_DATA); 1788 } 1789 1790 static unsigned char snd_cmipci_mixer_read(cmipci_t *s, unsigned char idx) 1791 { 1792 unsigned char v; 1793 1794 outb(idx, s->iobase + CM_REG_SB16_ADDR); 1795 v = inb(s->iobase + CM_REG_SB16_DATA); 1796 return v; 1797 } 1798 1799 /* 1800 * general mixer element 1801 */ 1802 typedef struct cmipci_sb_reg { 1803 unsigned int left_reg, right_reg; 1804 unsigned int left_shift, right_shift; 1805 unsigned int mask; 1806 unsigned int invert: 1; 1807 unsigned int stereo: 1; 1808 } cmipci_sb_reg_t; 1809 1810 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \ 1811 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23)) 1812 1813 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \ 1814 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1815 .info = snd_cmipci_info_volume, \ 1816 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \ 1817 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \ 1818 } 1819 1820 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1) 1821 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0) 1822 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1) 1823 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0) 1824 1825 static void cmipci_sb_reg_decode(cmipci_sb_reg_t *r, unsigned long val) 1826 { 1827 r->left_reg = val & 0xff; 1828 r->right_reg = (val >> 8) & 0xff; 1829 r->left_shift = (val >> 16) & 0x07; 1830 r->right_shift = (val >> 19) & 0x07; 1831 r->invert = (val >> 22) & 1; 1832 r->stereo = (val >> 23) & 1; 1833 r->mask = (val >> 24) & 0xff; 1834 } 1835 1836 static int snd_cmipci_info_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo) 1837 { 1838 cmipci_sb_reg_t reg; 1839 1840 cmipci_sb_reg_decode(®, kcontrol->private_value); 1841 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 1842 uinfo->count = reg.stereo + 1; 1843 uinfo->value.integer.min = 0; 1844 uinfo->value.integer.max = reg.mask; 1845 return 0; 1846 } 1847 1848 static int snd_cmipci_get_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1849 { 1850 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 1851 cmipci_sb_reg_t reg; 1852 int val; 1853 1854 cmipci_sb_reg_decode(®, kcontrol->private_value); 1855 spin_lock_irq(&cm->reg_lock); 1856 val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask; 1857 if (reg.invert) 1858 val = reg.mask - val; 1859 ucontrol->value.integer.value[0] = val; 1860 if (reg.stereo) { 1861 val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask; 1862 if (reg.invert) 1863 val = reg.mask - val; 1864 ucontrol->value.integer.value[1] = val; 1865 } 1866 spin_unlock_irq(&cm->reg_lock); 1867 return 0; 1868 } 1869 1870 static int snd_cmipci_put_volume(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1871 { 1872 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 1873 cmipci_sb_reg_t reg; 1874 int change; 1875 int left, right, oleft, oright; 1876 1877 cmipci_sb_reg_decode(®, kcontrol->private_value); 1878 left = ucontrol->value.integer.value[0] & reg.mask; 1879 if (reg.invert) 1880 left = reg.mask - left; 1881 left <<= reg.left_shift; 1882 if (reg.stereo) { 1883 right = ucontrol->value.integer.value[1] & reg.mask; 1884 if (reg.invert) 1885 right = reg.mask - right; 1886 right <<= reg.right_shift; 1887 } else 1888 right = 0; 1889 spin_lock_irq(&cm->reg_lock); 1890 oleft = snd_cmipci_mixer_read(cm, reg.left_reg); 1891 left |= oleft & ~(reg.mask << reg.left_shift); 1892 change = left != oleft; 1893 if (reg.stereo) { 1894 if (reg.left_reg != reg.right_reg) { 1895 snd_cmipci_mixer_write(cm, reg.left_reg, left); 1896 oright = snd_cmipci_mixer_read(cm, reg.right_reg); 1897 } else 1898 oright = left; 1899 right |= oright & ~(reg.mask << reg.right_shift); 1900 change |= right != oright; 1901 snd_cmipci_mixer_write(cm, reg.right_reg, right); 1902 } else 1903 snd_cmipci_mixer_write(cm, reg.left_reg, left); 1904 spin_unlock_irq(&cm->reg_lock); 1905 return change; 1906 } 1907 1908 /* 1909 * input route (left,right) -> (left,right) 1910 */ 1911 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \ 1912 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1913 .info = snd_cmipci_info_input_sw, \ 1914 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \ 1915 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \ 1916 } 1917 1918 static int snd_cmipci_info_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_info_t * uinfo) 1919 { 1920 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1921 uinfo->count = 4; 1922 uinfo->value.integer.min = 0; 1923 uinfo->value.integer.max = 1; 1924 return 0; 1925 } 1926 1927 static int snd_cmipci_get_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1928 { 1929 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 1930 cmipci_sb_reg_t reg; 1931 int val1, val2; 1932 1933 cmipci_sb_reg_decode(®, kcontrol->private_value); 1934 spin_lock_irq(&cm->reg_lock); 1935 val1 = snd_cmipci_mixer_read(cm, reg.left_reg); 1936 val2 = snd_cmipci_mixer_read(cm, reg.right_reg); 1937 spin_unlock_irq(&cm->reg_lock); 1938 ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1; 1939 ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1; 1940 ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1; 1941 ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1; 1942 return 0; 1943 } 1944 1945 static int snd_cmipci_put_input_sw(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1946 { 1947 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 1948 cmipci_sb_reg_t reg; 1949 int change; 1950 int val1, val2, oval1, oval2; 1951 1952 cmipci_sb_reg_decode(®, kcontrol->private_value); 1953 spin_lock_irq(&cm->reg_lock); 1954 oval1 = snd_cmipci_mixer_read(cm, reg.left_reg); 1955 oval2 = snd_cmipci_mixer_read(cm, reg.right_reg); 1956 val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); 1957 val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift)); 1958 val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift; 1959 val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift; 1960 val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift; 1961 val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift; 1962 change = val1 != oval1 || val2 != oval2; 1963 snd_cmipci_mixer_write(cm, reg.left_reg, val1); 1964 snd_cmipci_mixer_write(cm, reg.right_reg, val2); 1965 spin_unlock_irq(&cm->reg_lock); 1966 return change; 1967 } 1968 1969 /* 1970 * native mixer switches/volumes 1971 */ 1972 1973 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \ 1974 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1975 .info = snd_cmipci_info_native_mixer, \ 1976 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 1977 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \ 1978 } 1979 1980 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \ 1981 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1982 .info = snd_cmipci_info_native_mixer, \ 1983 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 1984 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \ 1985 } 1986 1987 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \ 1988 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1989 .info = snd_cmipci_info_native_mixer, \ 1990 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 1991 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \ 1992 } 1993 1994 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \ 1995 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 1996 .info = snd_cmipci_info_native_mixer, \ 1997 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \ 1998 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \ 1999 } 2000 2001 static int snd_cmipci_info_native_mixer(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo) 2002 { 2003 cmipci_sb_reg_t reg; 2004 2005 cmipci_sb_reg_decode(®, kcontrol->private_value); 2006 uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 2007 uinfo->count = reg.stereo + 1; 2008 uinfo->value.integer.min = 0; 2009 uinfo->value.integer.max = reg.mask; 2010 return 0; 2011 2012 } 2013 2014 static int snd_cmipci_get_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2015 { 2016 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2017 cmipci_sb_reg_t reg; 2018 unsigned char oreg, val; 2019 2020 cmipci_sb_reg_decode(®, kcontrol->private_value); 2021 spin_lock_irq(&cm->reg_lock); 2022 oreg = inb(cm->iobase + reg.left_reg); 2023 val = (oreg >> reg.left_shift) & reg.mask; 2024 if (reg.invert) 2025 val = reg.mask - val; 2026 ucontrol->value.integer.value[0] = val; 2027 if (reg.stereo) { 2028 val = (oreg >> reg.right_shift) & reg.mask; 2029 if (reg.invert) 2030 val = reg.mask - val; 2031 ucontrol->value.integer.value[1] = val; 2032 } 2033 spin_unlock_irq(&cm->reg_lock); 2034 return 0; 2035 } 2036 2037 static int snd_cmipci_put_native_mixer(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 2038 { 2039 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2040 cmipci_sb_reg_t reg; 2041 unsigned char oreg, nreg, val; 2042 2043 cmipci_sb_reg_decode(®, kcontrol->private_value); 2044 spin_lock_irq(&cm->reg_lock); 2045 oreg = inb(cm->iobase + reg.left_reg); 2046 val = ucontrol->value.integer.value[0] & reg.mask; 2047 if (reg.invert) 2048 val = reg.mask - val; 2049 nreg = oreg & ~(reg.mask << reg.left_shift); 2050 nreg |= (val << reg.left_shift); 2051 if (reg.stereo) { 2052 val = ucontrol->value.integer.value[1] & reg.mask; 2053 if (reg.invert) 2054 val = reg.mask - val; 2055 nreg &= ~(reg.mask << reg.right_shift); 2056 nreg |= (val << reg.right_shift); 2057 } 2058 outb(nreg, cm->iobase + reg.left_reg); 2059 spin_unlock_irq(&cm->reg_lock); 2060 return (nreg != oreg); 2061 } 2062 2063 /* 2064 * special case - check mixer sensitivity 2065 */ 2066 static int snd_cmipci_get_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 2067 { 2068 //cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2069 return snd_cmipci_get_native_mixer(kcontrol, ucontrol); 2070 } 2071 2072 static int snd_cmipci_put_native_mixer_sensitive(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 2073 { 2074 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2075 if (cm->mixer_insensitive) { 2076 /* ignored */ 2077 return 0; 2078 } 2079 return snd_cmipci_put_native_mixer(kcontrol, ucontrol); 2080 } 2081 2082 2083 static snd_kcontrol_new_t snd_cmipci_mixers[] __devinitdata = { 2084 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31), 2085 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0), 2086 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31), 2087 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1), 2088 { /* switch with sensitivity */ 2089 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2090 .name = "PCM Playback Switch", 2091 .info = snd_cmipci_info_native_mixer, 2092 .get = snd_cmipci_get_native_mixer_sensitive, 2093 .put = snd_cmipci_put_native_mixer_sensitive, 2094 .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0), 2095 }, 2096 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0), 2097 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31), 2098 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1), 2099 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5), 2100 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31), 2101 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1), 2102 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1), 2103 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31), 2104 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3), 2105 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3), 2106 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31), 2107 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0), 2108 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0), 2109 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3), 2110 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15), 2111 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0), 2112 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0), 2113 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1), 2114 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7), 2115 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7), 2116 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0), 2117 CMIPCI_DOUBLE("PC Speaker Playnack Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0), 2118 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0), 2119 }; 2120 2121 /* 2122 * other switches 2123 */ 2124 2125 typedef struct snd_cmipci_switch_args { 2126 int reg; /* register index */ 2127 unsigned int mask; /* mask bits */ 2128 unsigned int mask_on; /* mask bits to turn on */ 2129 unsigned int is_byte: 1; /* byte access? */ 2130 unsigned int ac3_sensitive: 1; /* access forbidden during non-audio operation? */ 2131 } snd_cmipci_switch_args_t; 2132 2133 static int snd_cmipci_uswitch_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo) 2134 { 2135 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2136 uinfo->count = 1; 2137 uinfo->value.integer.min = 0; 2138 uinfo->value.integer.max = 1; 2139 return 0; 2140 } 2141 2142 static int _snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args) 2143 { 2144 unsigned int val; 2145 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2146 2147 spin_lock_irq(&cm->reg_lock); 2148 if (args->ac3_sensitive && cm->mixer_insensitive) { 2149 ucontrol->value.integer.value[0] = 0; 2150 spin_unlock_irq(&cm->reg_lock); 2151 return 0; 2152 } 2153 if (args->is_byte) 2154 val = inb(cm->iobase + args->reg); 2155 else 2156 val = snd_cmipci_read(cm, args->reg); 2157 ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0; 2158 spin_unlock_irq(&cm->reg_lock); 2159 return 0; 2160 } 2161 2162 static int snd_cmipci_uswitch_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 2163 { 2164 snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value; 2165 snd_assert(args != NULL, return -EINVAL); 2166 return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args); 2167 } 2168 2169 static int _snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol, snd_cmipci_switch_args_t *args) 2170 { 2171 unsigned int val; 2172 int change; 2173 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2174 2175 spin_lock_irq(&cm->reg_lock); 2176 if (args->ac3_sensitive && cm->mixer_insensitive) { 2177 /* ignored */ 2178 spin_unlock_irq(&cm->reg_lock); 2179 return 0; 2180 } 2181 if (args->is_byte) 2182 val = inb(cm->iobase + args->reg); 2183 else 2184 val = snd_cmipci_read(cm, args->reg); 2185 change = (val & args->mask) != (ucontrol->value.integer.value[0] ? args->mask : 0); 2186 if (change) { 2187 val &= ~args->mask; 2188 if (ucontrol->value.integer.value[0]) 2189 val |= args->mask_on; 2190 else 2191 val |= (args->mask & ~args->mask_on); 2192 if (args->is_byte) 2193 outb((unsigned char)val, cm->iobase + args->reg); 2194 else 2195 snd_cmipci_write(cm, args->reg, val); 2196 } 2197 spin_unlock_irq(&cm->reg_lock); 2198 return change; 2199 } 2200 2201 static int snd_cmipci_uswitch_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 2202 { 2203 snd_cmipci_switch_args_t *args = (snd_cmipci_switch_args_t*)kcontrol->private_value; 2204 snd_assert(args != NULL, return -EINVAL); 2205 return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args); 2206 } 2207 2208 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \ 2209 static snd_cmipci_switch_args_t cmipci_switch_arg_##sname = { \ 2210 .reg = xreg, \ 2211 .mask = xmask, \ 2212 .mask_on = xmask_on, \ 2213 .is_byte = xis_byte, \ 2214 .ac3_sensitive = xac3, \ 2215 } 2216 2217 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \ 2218 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3) 2219 2220 #if 0 /* these will be controlled in pcm device */ 2221 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0); 2222 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0); 2223 #endif 2224 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0); 2225 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0); 2226 DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0); 2227 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1); 2228 DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0); 2229 DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0); 2230 DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1); 2231 DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */ 2232 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1); 2233 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1); 2234 DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0); 2235 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */ 2236 DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0); 2237 DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0); 2238 #if CM_CH_PLAY == 1 2239 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */ 2240 #else 2241 DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0); 2242 #endif 2243 DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0); 2244 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0); 2245 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0); 2246 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */ 2247 DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0); 2248 2249 #define DEFINE_SWITCH(sname, stype, sarg) \ 2250 { .name = sname, \ 2251 .iface = stype, \ 2252 .info = snd_cmipci_uswitch_info, \ 2253 .get = snd_cmipci_uswitch_get, \ 2254 .put = snd_cmipci_uswitch_put, \ 2255 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\ 2256 } 2257 2258 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg) 2259 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg) 2260 2261 2262 /* 2263 * callbacks for spdif output switch 2264 * needs toggle two registers.. 2265 */ 2266 static int snd_cmipci_spdout_enable_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 2267 { 2268 int changed; 2269 changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); 2270 changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); 2271 return changed; 2272 } 2273 2274 static int snd_cmipci_spdout_enable_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 2275 { 2276 cmipci_t *chip = snd_kcontrol_chip(kcontrol); 2277 int changed; 2278 changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable); 2279 changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac); 2280 if (changed) { 2281 if (ucontrol->value.integer.value[0]) { 2282 if (chip->spdif_playback_avail) 2283 snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 2284 } else { 2285 if (chip->spdif_playback_avail) 2286 snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF); 2287 } 2288 } 2289 chip->spdif_playback_enabled = ucontrol->value.integer.value[0]; 2290 return changed; 2291 } 2292 2293 2294 static int snd_cmipci_line_in_mode_info(snd_kcontrol_t *kcontrol, 2295 snd_ctl_elem_info_t *uinfo) 2296 { 2297 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2298 static char *texts[3] = { "Line-In", "Rear Output", "Bass Output" }; 2299 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2300 uinfo->count = 1; 2301 uinfo->value.enumerated.items = cm->chip_version >= 39 ? 3 : 2; 2302 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2303 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2304 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2305 return 0; 2306 } 2307 2308 static inline unsigned int get_line_in_mode(cmipci_t *cm) 2309 { 2310 unsigned int val; 2311 if (cm->chip_version >= 39) { 2312 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL); 2313 if (val & CM_LINE_AS_BASS) 2314 return 2; 2315 } 2316 val = snd_cmipci_read_b(cm, CM_REG_MIXER1); 2317 if (val & CM_SPK4) 2318 return 1; 2319 return 0; 2320 } 2321 2322 static int snd_cmipci_line_in_mode_get(snd_kcontrol_t *kcontrol, 2323 snd_ctl_elem_value_t *ucontrol) 2324 { 2325 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2326 2327 spin_lock_irq(&cm->reg_lock); 2328 ucontrol->value.enumerated.item[0] = get_line_in_mode(cm); 2329 spin_unlock_irq(&cm->reg_lock); 2330 return 0; 2331 } 2332 2333 static int snd_cmipci_line_in_mode_put(snd_kcontrol_t *kcontrol, 2334 snd_ctl_elem_value_t *ucontrol) 2335 { 2336 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2337 int change; 2338 2339 spin_lock_irq(&cm->reg_lock); 2340 if (ucontrol->value.enumerated.item[0] == 2) 2341 change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS); 2342 else 2343 change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS); 2344 if (ucontrol->value.enumerated.item[0] == 1) 2345 change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_SPK4); 2346 else 2347 change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_SPK4); 2348 spin_unlock_irq(&cm->reg_lock); 2349 return change; 2350 } 2351 2352 static int snd_cmipci_mic_in_mode_info(snd_kcontrol_t *kcontrol, 2353 snd_ctl_elem_info_t *uinfo) 2354 { 2355 static char *texts[2] = { "Mic-In", "Center/LFE Output" }; 2356 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2357 uinfo->count = 1; 2358 uinfo->value.enumerated.items = 2; 2359 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2360 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2361 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2362 return 0; 2363 } 2364 2365 static int snd_cmipci_mic_in_mode_get(snd_kcontrol_t *kcontrol, 2366 snd_ctl_elem_value_t *ucontrol) 2367 { 2368 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2369 /* same bit as spdi_phase */ 2370 spin_lock_irq(&cm->reg_lock); 2371 ucontrol->value.enumerated.item[0] = 2372 (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0; 2373 spin_unlock_irq(&cm->reg_lock); 2374 return 0; 2375 } 2376 2377 static int snd_cmipci_mic_in_mode_put(snd_kcontrol_t *kcontrol, 2378 snd_ctl_elem_value_t *ucontrol) 2379 { 2380 cmipci_t *cm = snd_kcontrol_chip(kcontrol); 2381 int change; 2382 2383 spin_lock_irq(&cm->reg_lock); 2384 if (ucontrol->value.enumerated.item[0]) 2385 change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); 2386 else 2387 change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE); 2388 spin_unlock_irq(&cm->reg_lock); 2389 return change; 2390 } 2391 2392 /* both for CM8338/8738 */ 2393 static snd_kcontrol_new_t snd_cmipci_mixer_switches[] __devinitdata = { 2394 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch), 2395 { 2396 .name = "Line-In Mode", 2397 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2398 .info = snd_cmipci_line_in_mode_info, 2399 .get = snd_cmipci_line_in_mode_get, 2400 .put = snd_cmipci_line_in_mode_put, 2401 }, 2402 }; 2403 2404 /* for non-multichannel chips */ 2405 static snd_kcontrol_new_t snd_cmipci_nomulti_switch __devinitdata = 2406 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac); 2407 2408 /* only for CM8738 */ 2409 static snd_kcontrol_new_t snd_cmipci_8738_mixer_switches[] __devinitdata = { 2410 #if 0 /* controlled in pcm device */ 2411 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in), 2412 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out), 2413 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac), 2414 #endif 2415 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable), 2416 { .name = "IEC958 Output Switch", 2417 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2418 .info = snd_cmipci_uswitch_info, 2419 .get = snd_cmipci_spdout_enable_get, 2420 .put = snd_cmipci_spdout_enable_put, 2421 }, 2422 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid), 2423 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright), 2424 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v), 2425 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k), 2426 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop), 2427 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor), 2428 }; 2429 2430 /* only for model 033/037 */ 2431 static snd_kcontrol_new_t snd_cmipci_old_mixer_switches[] __devinitdata = { 2432 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out), 2433 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase), 2434 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1), 2435 }; 2436 2437 /* only for model 039 or later */ 2438 static snd_kcontrol_new_t snd_cmipci_extra_mixer_switches[] __devinitdata = { 2439 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2), 2440 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2), 2441 { 2442 .name = "Mic-In Mode", 2443 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2444 .info = snd_cmipci_mic_in_mode_info, 2445 .get = snd_cmipci_mic_in_mode_get, 2446 .put = snd_cmipci_mic_in_mode_put, 2447 } 2448 }; 2449 2450 /* card control switches */ 2451 static snd_kcontrol_new_t snd_cmipci_control_switches[] __devinitdata = { 2452 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */ 2453 DEFINE_CARD_SWITCH("Modem", modem), 2454 }; 2455 2456 2457 static int __devinit snd_cmipci_mixer_new(cmipci_t *cm, int pcm_spdif_device) 2458 { 2459 snd_card_t *card; 2460 snd_kcontrol_new_t *sw; 2461 snd_kcontrol_t *kctl; 2462 unsigned int idx; 2463 int err; 2464 2465 snd_assert(cm != NULL && cm->card != NULL, return -EINVAL); 2466 2467 card = cm->card; 2468 2469 strcpy(card->mixername, "CMedia PCI"); 2470 2471 spin_lock_irq(&cm->reg_lock); 2472 snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */ 2473 spin_unlock_irq(&cm->reg_lock); 2474 2475 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) { 2476 if (cm->chip_version == 68) { // 8768 has no PCM volume 2477 if (!strcmp(snd_cmipci_mixers[idx].name, 2478 "PCM Playback Volume")) 2479 continue; 2480 } 2481 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0) 2482 return err; 2483 } 2484 2485 /* mixer switches */ 2486 sw = snd_cmipci_mixer_switches; 2487 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) { 2488 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2489 if (err < 0) 2490 return err; 2491 } 2492 if (! cm->can_multi_ch) { 2493 err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm)); 2494 if (err < 0) 2495 return err; 2496 } 2497 if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 || 2498 cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) { 2499 sw = snd_cmipci_8738_mixer_switches; 2500 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) { 2501 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2502 if (err < 0) 2503 return err; 2504 } 2505 if (cm->can_ac3_hw) { 2506 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0) 2507 return err; 2508 kctl->id.device = pcm_spdif_device; 2509 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0) 2510 return err; 2511 kctl->id.device = pcm_spdif_device; 2512 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0) 2513 return err; 2514 kctl->id.device = pcm_spdif_device; 2515 } 2516 if (cm->chip_version <= 37) { 2517 sw = snd_cmipci_old_mixer_switches; 2518 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) { 2519 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2520 if (err < 0) 2521 return err; 2522 } 2523 } 2524 } 2525 if (cm->chip_version >= 39) { 2526 sw = snd_cmipci_extra_mixer_switches; 2527 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) { 2528 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2529 if (err < 0) 2530 return err; 2531 } 2532 } 2533 2534 /* card switches */ 2535 sw = snd_cmipci_control_switches; 2536 for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_control_switches); idx++, sw++) { 2537 err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm)); 2538 if (err < 0) 2539 return err; 2540 } 2541 2542 for (idx = 0; idx < CM_SAVED_MIXERS; idx++) { 2543 snd_ctl_elem_id_t id; 2544 snd_kcontrol_t *ctl; 2545 memset(&id, 0, sizeof(id)); 2546 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2547 strcpy(id.name, cm_saved_mixer[idx].name); 2548 if ((ctl = snd_ctl_find_id(cm->card, &id)) != NULL) 2549 cm->mixer_res_ctl[idx] = ctl; 2550 } 2551 2552 return 0; 2553 } 2554 2555 2556 /* 2557 * proc interface 2558 */ 2559 2560 #ifdef CONFIG_PROC_FS 2561 static void snd_cmipci_proc_read(snd_info_entry_t *entry, 2562 snd_info_buffer_t *buffer) 2563 { 2564 cmipci_t *cm = entry->private_data; 2565 int i; 2566 2567 snd_iprintf(buffer, "%s\n\n", cm->card->longname); 2568 for (i = 0; i < 0x40; i++) { 2569 int v = inb(cm->iobase + i); 2570 if (i % 4 == 0) 2571 snd_iprintf(buffer, "%02x: ", i); 2572 snd_iprintf(buffer, "%02x", v); 2573 if (i % 4 == 3) 2574 snd_iprintf(buffer, "\n"); 2575 else 2576 snd_iprintf(buffer, " "); 2577 } 2578 } 2579 2580 static void __devinit snd_cmipci_proc_init(cmipci_t *cm) 2581 { 2582 snd_info_entry_t *entry; 2583 2584 if (! snd_card_proc_new(cm->card, "cmipci", &entry)) 2585 snd_info_set_text_ops(entry, cm, 1024, snd_cmipci_proc_read); 2586 } 2587 #else /* !CONFIG_PROC_FS */ 2588 static inline void snd_cmipci_proc_init(cmipci_t *cm) {} 2589 #endif 2590 2591 2592 static struct pci_device_id snd_cmipci_ids[] = { 2593 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2594 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2595 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2596 {PCI_VENDOR_ID_CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2597 {PCI_VENDOR_ID_AL, PCI_DEVICE_ID_CMEDIA_CM8738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 2598 {0,}, 2599 }; 2600 2601 2602 /* 2603 * check chip version and capabilities 2604 * driver name is modified according to the chip model 2605 */ 2606 static void __devinit query_chip(cmipci_t *cm) 2607 { 2608 unsigned int detect; 2609 2610 /* check reg 0Ch, bit 24-31 */ 2611 detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2; 2612 if (! detect) { 2613 /* check reg 08h, bit 24-28 */ 2614 detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1; 2615 if (! detect) { 2616 cm->chip_version = 33; 2617 cm->max_channels = 2; 2618 if (cm->do_soft_ac3) 2619 cm->can_ac3_sw = 1; 2620 else 2621 cm->can_ac3_hw = 1; 2622 cm->has_dual_dac = 1; 2623 } else { 2624 cm->chip_version = 37; 2625 cm->max_channels = 2; 2626 cm->can_ac3_hw = 1; 2627 cm->has_dual_dac = 1; 2628 } 2629 } else { 2630 /* check reg 0Ch, bit 26 */ 2631 if (detect & CM_CHIP_8768) { 2632 cm->chip_version = 68; 2633 cm->max_channels = 8; 2634 cm->can_ac3_hw = 1; 2635 cm->has_dual_dac = 1; 2636 cm->can_multi_ch = 1; 2637 } else if (detect & CM_CHIP_055) { 2638 cm->chip_version = 55; 2639 cm->max_channels = 6; 2640 cm->can_ac3_hw = 1; 2641 cm->has_dual_dac = 1; 2642 cm->can_multi_ch = 1; 2643 } else if (detect & CM_CHIP_039) { 2644 cm->chip_version = 39; 2645 if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */ 2646 cm->max_channels = 6; 2647 else 2648 cm->max_channels = 4; 2649 cm->can_ac3_hw = 1; 2650 cm->has_dual_dac = 1; 2651 cm->can_multi_ch = 1; 2652 } else { 2653 printk(KERN_ERR "chip %x version not supported\n", detect); 2654 } 2655 } 2656 } 2657 2658 #ifdef SUPPORT_JOYSTICK 2659 static int __devinit snd_cmipci_create_gameport(cmipci_t *cm, int dev) 2660 { 2661 static int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */ 2662 struct gameport *gp; 2663 struct resource *r = NULL; 2664 int i, io_port = 0; 2665 2666 if (joystick_port[dev] == 0) 2667 return -ENODEV; 2668 2669 if (joystick_port[dev] == 1) { /* auto-detect */ 2670 for (i = 0; ports[i]; i++) { 2671 io_port = ports[i]; 2672 r = request_region(io_port, 1, "CMIPCI gameport"); 2673 if (r) 2674 break; 2675 } 2676 } else { 2677 io_port = joystick_port[dev]; 2678 r = request_region(io_port, 1, "CMIPCI gameport"); 2679 } 2680 2681 if (!r) { 2682 printk(KERN_WARNING "cmipci: cannot reserve joystick ports\n"); 2683 return -EBUSY; 2684 } 2685 2686 cm->gameport = gp = gameport_allocate_port(); 2687 if (!gp) { 2688 printk(KERN_ERR "cmipci: cannot allocate memory for gameport\n"); 2689 release_resource(r); 2690 kfree_nocheck(r); 2691 return -ENOMEM; 2692 } 2693 gameport_set_name(gp, "C-Media Gameport"); 2694 gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci)); 2695 gameport_set_dev_parent(gp, &cm->pci->dev); 2696 gp->io = io_port; 2697 gameport_set_port_data(gp, r); 2698 2699 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 2700 2701 gameport_register_port(cm->gameport); 2702 2703 return 0; 2704 } 2705 2706 static void snd_cmipci_free_gameport(cmipci_t *cm) 2707 { 2708 if (cm->gameport) { 2709 struct resource *r = gameport_get_port_data(cm->gameport); 2710 2711 gameport_unregister_port(cm->gameport); 2712 cm->gameport = NULL; 2713 2714 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 2715 release_resource(r); 2716 kfree_nocheck(r); 2717 } 2718 } 2719 #else 2720 static inline int snd_cmipci_create_gameport(cmipci_t *cm, int dev) { return -ENOSYS; } 2721 static inline void snd_cmipci_free_gameport(cmipci_t *cm) { } 2722 #endif 2723 2724 static int snd_cmipci_free(cmipci_t *cm) 2725 { 2726 if (cm->irq >= 0) { 2727 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2728 snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); 2729 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ 2730 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 2731 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 2732 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ 2733 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); 2734 2735 /* reset mixer */ 2736 snd_cmipci_mixer_write(cm, 0, 0); 2737 2738 synchronize_irq(cm->irq); 2739 2740 free_irq(cm->irq, (void *)cm); 2741 } 2742 2743 snd_cmipci_free_gameport(cm); 2744 pci_release_regions(cm->pci); 2745 pci_disable_device(cm->pci); 2746 kfree(cm); 2747 return 0; 2748 } 2749 2750 static int snd_cmipci_dev_free(snd_device_t *device) 2751 { 2752 cmipci_t *cm = device->device_data; 2753 return snd_cmipci_free(cm); 2754 } 2755 2756 static int __devinit snd_cmipci_create(snd_card_t *card, struct pci_dev *pci, 2757 int dev, cmipci_t **rcmipci) 2758 { 2759 cmipci_t *cm; 2760 int err; 2761 static snd_device_ops_t ops = { 2762 .dev_free = snd_cmipci_dev_free, 2763 }; 2764 unsigned int val = 0; 2765 long iomidi = mpu_port[dev]; 2766 long iosynth = fm_port[dev]; 2767 int pcm_index, pcm_spdif_index; 2768 static struct pci_device_id intel_82437vx[] = { 2769 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) }, 2770 { }, 2771 }; 2772 2773 *rcmipci = NULL; 2774 2775 if ((err = pci_enable_device(pci)) < 0) 2776 return err; 2777 2778 cm = kzalloc(sizeof(*cm), GFP_KERNEL); 2779 if (cm == NULL) { 2780 pci_disable_device(pci); 2781 return -ENOMEM; 2782 } 2783 2784 spin_lock_init(&cm->reg_lock); 2785 init_MUTEX(&cm->open_mutex); 2786 cm->device = pci->device; 2787 cm->card = card; 2788 cm->pci = pci; 2789 cm->irq = -1; 2790 cm->channel[0].ch = 0; 2791 cm->channel[1].ch = 1; 2792 cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */ 2793 2794 if ((err = pci_request_regions(pci, card->driver)) < 0) { 2795 kfree(cm); 2796 pci_disable_device(pci); 2797 return err; 2798 } 2799 cm->iobase = pci_resource_start(pci, 0); 2800 2801 if (request_irq(pci->irq, snd_cmipci_interrupt, SA_INTERRUPT|SA_SHIRQ, card->driver, (void *)cm)) { 2802 snd_printk("unable to grab IRQ %d\n", pci->irq); 2803 snd_cmipci_free(cm); 2804 return -EBUSY; 2805 } 2806 cm->irq = pci->irq; 2807 2808 pci_set_master(cm->pci); 2809 2810 /* 2811 * check chip version, max channels and capabilities 2812 */ 2813 2814 cm->chip_version = 0; 2815 cm->max_channels = 2; 2816 cm->do_soft_ac3 = soft_ac3[dev]; 2817 2818 if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A && 2819 pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B) 2820 query_chip(cm); 2821 /* added -MCx suffix for chip supporting multi-channels */ 2822 if (cm->can_multi_ch) 2823 sprintf(cm->card->driver + strlen(cm->card->driver), 2824 "-MC%d", cm->max_channels); 2825 else if (cm->can_ac3_sw) 2826 strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC"); 2827 2828 cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF; 2829 cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF; 2830 2831 #if CM_CH_PLAY == 1 2832 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */ 2833 #else 2834 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */ 2835 #endif 2836 2837 /* initialize codec registers */ 2838 snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */ 2839 snd_cmipci_ch_reset(cm, CM_CH_PLAY); 2840 snd_cmipci_ch_reset(cm, CM_CH_CAPT); 2841 snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */ 2842 snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0); 2843 2844 snd_cmipci_write(cm, CM_REG_CHFORMAT, 0); 2845 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D); 2846 #if CM_CH_PLAY == 1 2847 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 2848 #else 2849 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC); 2850 #endif 2851 /* Set Bus Master Request */ 2852 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ); 2853 2854 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */ 2855 switch (pci->device) { 2856 case PCI_DEVICE_ID_CMEDIA_CM8738: 2857 case PCI_DEVICE_ID_CMEDIA_CM8738B: 2858 if (!pci_dev_present(intel_82437vx)) 2859 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX); 2860 break; 2861 default: 2862 break; 2863 } 2864 2865 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) { 2866 snd_cmipci_free(cm); 2867 return err; 2868 } 2869 2870 /* set MPU address */ 2871 switch (iomidi) { 2872 case 0x320: val = CM_VMPU_320; break; 2873 case 0x310: val = CM_VMPU_310; break; 2874 case 0x300: val = CM_VMPU_300; break; 2875 case 0x330: val = CM_VMPU_330; break; 2876 default: 2877 iomidi = 0; break; 2878 } 2879 if (iomidi > 0) { 2880 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); 2881 /* enable UART */ 2882 snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN); 2883 } 2884 2885 /* set FM address */ 2886 val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK; 2887 switch (iosynth) { 2888 case 0x3E8: val |= CM_FMSEL_3E8; break; 2889 case 0x3E0: val |= CM_FMSEL_3E0; break; 2890 case 0x3C8: val |= CM_FMSEL_3C8; break; 2891 case 0x388: val |= CM_FMSEL_388; break; 2892 default: 2893 iosynth = 0; break; 2894 } 2895 if (iosynth > 0) { 2896 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val); 2897 /* enable FM */ 2898 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2899 2900 if (snd_opl3_create(card, iosynth, iosynth + 2, 2901 OPL3_HW_OPL3, 0, &cm->opl3) < 0) { 2902 printk(KERN_ERR "cmipci: no OPL device at 0x%lx, skipping...\n", iosynth); 2903 iosynth = 0; 2904 } else { 2905 if ((err = snd_opl3_hwdep_new(cm->opl3, 0, 1, &cm->opl3hwdep)) < 0) { 2906 printk(KERN_ERR "cmipci: cannot create OPL3 hwdep\n"); 2907 return err; 2908 } 2909 } 2910 } 2911 if (! iosynth) { 2912 /* disable FM */ 2913 snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val & ~CM_FMSEL_MASK); 2914 snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN); 2915 } 2916 2917 /* reset mixer */ 2918 snd_cmipci_mixer_write(cm, 0, 0); 2919 2920 snd_cmipci_proc_init(cm); 2921 2922 /* create pcm devices */ 2923 pcm_index = pcm_spdif_index = 0; 2924 if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0) 2925 return err; 2926 pcm_index++; 2927 if (cm->has_dual_dac) { 2928 if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0) 2929 return err; 2930 pcm_index++; 2931 } 2932 if (cm->can_ac3_hw || cm->can_ac3_sw) { 2933 pcm_spdif_index = pcm_index; 2934 if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0) 2935 return err; 2936 } 2937 2938 /* create mixer interface & switches */ 2939 if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0) 2940 return err; 2941 2942 if (iomidi > 0) { 2943 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI, 2944 iomidi, 0, 2945 cm->irq, 0, &cm->rmidi)) < 0) { 2946 printk(KERN_ERR "cmipci: no UART401 device at 0x%lx\n", iomidi); 2947 } 2948 } 2949 2950 #ifdef USE_VAR48KRATE 2951 for (val = 0; val < ARRAY_SIZE(rates); val++) 2952 snd_cmipci_set_pll(cm, rates[val], val); 2953 2954 /* 2955 * (Re-)Enable external switch spdo_48k 2956 */ 2957 snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97); 2958 #endif /* USE_VAR48KRATE */ 2959 2960 if (snd_cmipci_create_gameport(cm, dev) < 0) 2961 snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN); 2962 2963 snd_card_set_dev(card, &pci->dev); 2964 2965 *rcmipci = cm; 2966 return 0; 2967 } 2968 2969 /* 2970 */ 2971 2972 MODULE_DEVICE_TABLE(pci, snd_cmipci_ids); 2973 2974 static int __devinit snd_cmipci_probe(struct pci_dev *pci, 2975 const struct pci_device_id *pci_id) 2976 { 2977 static int dev; 2978 snd_card_t *card; 2979 cmipci_t *cm; 2980 int err; 2981 2982 if (dev >= SNDRV_CARDS) 2983 return -ENODEV; 2984 if (! enable[dev]) { 2985 dev++; 2986 return -ENOENT; 2987 } 2988 2989 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 2990 if (card == NULL) 2991 return -ENOMEM; 2992 2993 switch (pci->device) { 2994 case PCI_DEVICE_ID_CMEDIA_CM8738: 2995 case PCI_DEVICE_ID_CMEDIA_CM8738B: 2996 strcpy(card->driver, "CMI8738"); 2997 break; 2998 case PCI_DEVICE_ID_CMEDIA_CM8338A: 2999 case PCI_DEVICE_ID_CMEDIA_CM8338B: 3000 strcpy(card->driver, "CMI8338"); 3001 break; 3002 default: 3003 strcpy(card->driver, "CMIPCI"); 3004 break; 3005 } 3006 3007 if ((err = snd_cmipci_create(card, pci, dev, &cm)) < 0) { 3008 snd_card_free(card); 3009 return err; 3010 } 3011 3012 sprintf(card->shortname, "C-Media PCI %s", card->driver); 3013 sprintf(card->longname, "%s (model %d) at 0x%lx, irq %i", 3014 card->shortname, 3015 cm->chip_version, 3016 cm->iobase, 3017 cm->irq); 3018 3019 //snd_printd("%s is detected\n", card->longname); 3020 3021 if ((err = snd_card_register(card)) < 0) { 3022 snd_card_free(card); 3023 return err; 3024 } 3025 pci_set_drvdata(pci, card); 3026 dev++; 3027 return 0; 3028 3029 } 3030 3031 static void __devexit snd_cmipci_remove(struct pci_dev *pci) 3032 { 3033 snd_card_free(pci_get_drvdata(pci)); 3034 pci_set_drvdata(pci, NULL); 3035 } 3036 3037 3038 static struct pci_driver driver = { 3039 .name = "C-Media PCI", 3040 .owner = THIS_MODULE, 3041 .id_table = snd_cmipci_ids, 3042 .probe = snd_cmipci_probe, 3043 .remove = __devexit_p(snd_cmipci_remove), 3044 }; 3045 3046 static int __init alsa_card_cmipci_init(void) 3047 { 3048 return pci_register_driver(&driver); 3049 } 3050 3051 static void __exit alsa_card_cmipci_exit(void) 3052 { 3053 pci_unregister_driver(&driver); 3054 } 3055 3056 module_init(alsa_card_cmipci_init) 3057 module_exit(alsa_card_cmipci_exit) 3058