1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168). 3 * Copyright (C) 2002, 2005 - 2011 by Andreas Mohr <andi AT lisas.de> 4 * 5 * Framework borrowed from Bart Hartgers's als4000.c. 6 * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801), 7 * found in a Fujitsu-Siemens PC ("Cordant", aluminum case). 8 * Other versions are: 9 * PCI168 A(W), sub ID 1800 10 * PCI168 A/AP, sub ID 8000 11 * Please give me feedback in case you try my driver with one of these!! 12 * 13 * Keywords: Windows XP Vista 168nt4-125.zip 168win95-125.zip PCI 168 download 14 * (XP/Vista do not support this card at all but every Linux distribution 15 * has very good support out of the box; 16 * just to make sure that the right people hit this and get to know that, 17 * despite the high level of Internet ignorance - as usual :-P - 18 * about very good support for this card - on Linux!) 19 * 20 * NOTES 21 * Since Aztech does not provide any chipset documentation, 22 * even on repeated request to various addresses, 23 * and the answer that was finally given was negative 24 * (and I was stupid enough to manage to get hold of a PCI168 soundcard 25 * in the first place >:-P}), 26 * I was forced to base this driver on reverse engineering 27 * (3 weeks' worth of evenings filled with driver work). 28 * (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros) 29 * 30 * It is quite likely that the AZF3328 chip is the PCI cousin of the 31 * AZF3318 ("azt1020 pnp", "MM Pro 16") ISA chip, given very similar specs. 32 * 33 * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name 34 * for compatibility reasons) from Azfin (joint-venture of Aztech and Fincitec, 35 * Fincitec acquired by National Semiconductor in 2002, together with the 36 * Fincitec-related company ARSmikro) has the following features: 37 * 38 * - compatibility & compliance: 39 * - Microsoft PC 97 ("PC 97 Hardware Design Guide", 40 * http://www.microsoft.com/whdc/archive/pcguides.mspx) 41 * - Microsoft PC 98 Baseline Audio 42 * - MPU401 UART 43 * - Sound Blaster Emulation (DOS Box) 44 * - builtin AC97 conformant codec (SNR over 80dB) 45 * Note that "conformant" != "compliant"!! this chip's mixer register layout 46 * *differs* from the standard AC97 layout: 47 * they chose to not implement the headphone register (which is not a 48 * problem since it's merely optional), yet when doing this, they committed 49 * the grave sin of letting other registers follow immediately instead of 50 * keeping a headphone dummy register, thereby shifting the mixer register 51 * addresses illegally. So far unfortunately it looks like the very flexible 52 * ALSA AC97 support is still not enough to easily compensate for such a 53 * grave layout violation despite all tweaks and quirks mechanisms it offers. 54 * Well, not quite: now ac97 layer is much improved (bus-specific ops!), 55 * thus I was able to implement support - it's actually working quite well. 56 * An interesting item might be Aztech AMR 2800-W, since it's an AC97 57 * modem card which might reveal the Aztech-specific codec ID which 58 * we might want to pretend, too. Dito PCI168's brother, PCI368, 59 * where the advertising datasheet says it's AC97-based and has a 60 * Digital Enhanced Game Port. 61 * - builtin genuine OPL3 - verified to work fine, 20080506 62 * - full duplex 16bit playback/record at independent sampling rate 63 * - MPU401 (+ legacy address support, claimed by one official spec sheet) 64 * FIXME: how to enable legacy addr?? 65 * - game port (legacy address support) 66 * - builtin DirectInput support, helps reduce CPU overhead (interrupt-driven 67 * features supported). - See common term "Digital Enhanced Game Port"... 68 * (probably DirectInput 3.0 spec - confirm) 69 * - builtin 3D enhancement (said to be YAMAHA Ymersion) 70 * - built-in General DirectX timer having a 20 bits counter 71 * with 1us resolution (see below!) 72 * - I2S serial output port for external DAC 73 * [FIXME: 3.3V or 5V level? maximum rate is 66.2kHz right?] 74 * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI 75 * - supports hardware volume control 76 * - single chip low cost solution (128 pin QFP) 77 * - supports programmable Sub-vendor and Sub-system ID [24C02 SEEPROM chip] 78 * required for Microsoft's logo compliance (FIXME: where?) 79 * At least the Trident 4D Wave DX has one bit somewhere 80 * to enable writes to PCI subsystem VID registers, that should be it. 81 * This might easily be in extended PCI reg space, since PCI168 also has 82 * some custom data starting at 0x80. What kind of config settings 83 * are located in our extended PCI space anyway?? 84 * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms 85 * [TDA1517P chip] 86 * 87 * Note that this driver now is actually *better* than the Windows driver, 88 * since it additionally supports the card's 1MHz DirectX timer - just try 89 * the following snd-seq module parameters etc.: 90 * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0 91 * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0 92 * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000 93 * - "timidity -iAv -B2,8 -Os -EFreverb=0" 94 * - "pmidi -p 128:0 jazz.mid" 95 * 96 * OPL3 hardware playback testing, try something like: 97 * cat /proc/asound/hwdep 98 * and 99 * aconnect -o 100 * Then use 101 * sbiload -Dhw:x,y --opl3 /usr/share/sounds/opl3/std.o3 ......./drums.o3 102 * where x,y is the xx-yy number as given in hwdep. 103 * Then try 104 * pmidi -p a:b jazz.mid 105 * where a:b is the client number plus 0 usually, as given by aconnect above. 106 * Oh, and make sure to unmute the FM mixer control (doh!) 107 * NOTE: power use during OPL3 playback is _VERY_ high (70W --> 90W!) 108 * despite no CPU activity, possibly due to hindering ACPI idling somehow. 109 * Shouldn't be a problem of the AZF3328 chip itself, I'd hope. 110 * Higher PCM / FM mixer levels seem to conflict (causes crackling), 111 * at least sometimes. Maybe even use with hardware sequencer timer above :) 112 * adplay/adplug-utils might soon offer hardware-based OPL3 playback, too. 113 * 114 * Certain PCI versions of this card are susceptible to DMA traffic underruns 115 * in some systems (resulting in sound crackling/clicking/popping), 116 * probably because they don't have a DMA FIFO buffer or so. 117 * Overview (PCI ID/PCI subID/PCI rev.): 118 * - no DMA crackling on SiS735: 0x50DC/0x1801/16 119 * - unknown performance: 0x50DC/0x1801/10 120 * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler) 121 * 122 * Crackling happens with VIA chipsets or, in my case, an SiS735, which is 123 * supposed to be very fast and supposed to get rid of crackling much 124 * better than a VIA, yet ironically I still get crackling, like many other 125 * people with the same chipset. 126 * Possible remedies: 127 * - use speaker (amplifier) output instead of headphone output 128 * (in case crackling is due to overloaded output clipping) 129 * - plug card into a different PCI slot, preferably one that isn't shared 130 * too much (this helps a lot, but not completely!) 131 * - get rid of PCI VGA card, use AGP instead 132 * - upgrade or downgrade BIOS 133 * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX) 134 * Not too helpful. 135 * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS 136 * 137 * BUGS 138 * - full-duplex might *still* be problematic, however a recent test was fine 139 * - (non-bug) "Bass/Treble or 3D settings don't work" - they do get evaluated 140 * if you set PCM output switch to "pre 3D" instead of "post 3D". 141 * If this can't be set, then get a mixer application that Isn't Stupid (tm) 142 * (e.g. kmix, gamix) - unfortunately several are!! 143 * - locking is not entirely clean, especially the audio stream activity 144 * ints --> may be racy 145 * - an _unconnected_ secondary joystick at the gameport will be reported 146 * to be "active" (floating values, not precisely -1) due to the way we need 147 * to read the Digital Enhanced Game Port. Not sure whether it is fixable. 148 * 149 * TODO 150 * - use PCI_VDEVICE 151 * - verify driver status on x86_64 152 * - test multi-card driver operation 153 * - (ab)use 1MHz DirectX timer as kernel clocksource 154 * - test MPU401 MIDI playback etc. 155 * - add more power micro-management (disable various units of the card 156 * as long as they're unused, to improve audio quality and save power). 157 * However this requires more I/O ports which I haven't figured out yet 158 * and which thus might not even exist... 159 * The standard suspend/resume functionality could probably make use of 160 * some improvement, too... 161 * - figure out what all unknown port bits are responsible for 162 * - figure out some cleverly evil scheme to possibly make ALSA AC97 code 163 * fully accept our quite incompatible ""AC97"" mixer and thus save some 164 * code (but I'm not too optimistic that doing this is possible at all) 165 * - use MMIO (memory-mapped I/O)? Slightly faster access, e.g. for gameport. 166 */ 167 168 #include <linux/io.h> 169 #include <linux/init.h> 170 #include <linux/bug.h> /* WARN_ONCE */ 171 #include <linux/pci.h> 172 #include <linux/delay.h> 173 #include <linux/slab.h> 174 #include <linux/gameport.h> 175 #include <linux/module.h> 176 #include <linux/dma-mapping.h> 177 #include <sound/core.h> 178 #include <sound/control.h> 179 #include <sound/pcm.h> 180 #include <sound/rawmidi.h> 181 #include <sound/mpu401.h> 182 #include <sound/opl3.h> 183 #include <sound/initval.h> 184 /* 185 * Config switch, to use ALSA's AC97 layer instead of old custom mixer crap. 186 * If the AC97 compatibility parts we needed to implement locally turn out 187 * to work nicely, then remove the old implementation eventually. 188 */ 189 #define AZF_USE_AC97_LAYER 1 190 191 #ifdef AZF_USE_AC97_LAYER 192 #include <sound/ac97_codec.h> 193 #endif 194 #include "azt3328.h" 195 196 MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>"); 197 MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)"); 198 MODULE_LICENSE("GPL"); 199 200 #if IS_REACHABLE(CONFIG_GAMEPORT) 201 #define SUPPORT_GAMEPORT 1 202 #endif 203 204 /* === Debug settings === 205 Further diagnostic functionality than the settings below 206 does not need to be provided, since one can easily write a POSIX shell script 207 to dump the card's I/O ports (those listed in lspci -v -v): 208 dump() 209 { 210 local descr=$1; local addr=$2; local count=$3 211 212 echo "${descr}: ${count} @ ${addr}:" 213 dd if=/dev/port skip=`printf %d ${addr}` count=${count} bs=1 \ 214 2>/dev/null| hexdump -C 215 } 216 and then use something like 217 "dump joy200 0x200 8", "dump mpu388 0x388 4", "dump joy 0xb400 8", 218 "dump codec00 0xa800 32", "dump mixer 0xb800 64", "dump synth 0xbc00 8", 219 possibly within a "while true; do ... sleep 1; done" loop. 220 Tweaking ports could be done using 221 VALSTRING="`printf "%02x" $value`" 222 printf "\x""$VALSTRING"|dd of=/dev/port seek=`printf %d ${addr}` bs=1 \ 223 2>/dev/null 224 */ 225 226 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 227 module_param_array(index, int, NULL, 0444); 228 MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard."); 229 230 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 231 module_param_array(id, charp, NULL, 0444); 232 MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard."); 233 234 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 235 module_param_array(enable, bool, NULL, 0444); 236 MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard."); 237 238 static int seqtimer_scaling = 128; 239 module_param(seqtimer_scaling, int, 0444); 240 MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128."); 241 242 enum snd_azf3328_codec_type { 243 /* warning: fixed indices (also used for bitmask checks!) */ 244 AZF_CODEC_PLAYBACK = 0, 245 AZF_CODEC_CAPTURE = 1, 246 AZF_CODEC_I2S_OUT = 2, 247 }; 248 249 struct snd_azf3328_codec_data { 250 unsigned long io_base; /* keep first! (avoid offset calc) */ 251 unsigned int dma_base; /* helper to avoid an indirection in hotpath */ 252 spinlock_t *lock; /* TODO: convert to our own per-codec lock member */ 253 struct snd_pcm_substream *substream; 254 bool running; 255 enum snd_azf3328_codec_type type; 256 const char *name; 257 }; 258 259 struct snd_azf3328 { 260 /* often-used fields towards beginning, then grouped */ 261 262 unsigned long ctrl_io; /* usually 0xb000, size 128 */ 263 unsigned long game_io; /* usually 0xb400, size 8 */ 264 unsigned long mpu_io; /* usually 0xb800, size 4 */ 265 unsigned long opl3_io; /* usually 0xbc00, size 8 */ 266 unsigned long mixer_io; /* usually 0xc000, size 64 */ 267 268 spinlock_t reg_lock; 269 270 struct snd_timer *timer; 271 272 struct snd_pcm *pcm[3]; 273 274 /* playback, recording and I2S out codecs */ 275 struct snd_azf3328_codec_data codecs[3]; 276 277 #ifdef AZF_USE_AC97_LAYER 278 struct snd_ac97 *ac97; 279 #endif 280 281 struct snd_card *card; 282 struct snd_rawmidi *rmidi; 283 284 #ifdef SUPPORT_GAMEPORT 285 struct gameport *gameport; 286 u16 axes[4]; 287 #endif 288 289 struct pci_dev *pci; 290 int irq; 291 292 /* register 0x6a is write-only, thus need to remember setting. 293 * If we need to add more registers here, then we might try to fold this 294 * into some transparent combined shadow register handling with 295 * CONFIG_PM register storage below, but that's slightly difficult. */ 296 u16 shadow_reg_ctrl_6AH; 297 298 #ifdef CONFIG_PM_SLEEP 299 /* register value containers for power management 300 * Note: not always full I/O range preserved (similar to Win driver!) */ 301 u32 saved_regs_ctrl[AZF_ALIGN(AZF_IO_SIZE_CTRL_PM) / 4]; 302 u32 saved_regs_game[AZF_ALIGN(AZF_IO_SIZE_GAME_PM) / 4]; 303 u32 saved_regs_mpu[AZF_ALIGN(AZF_IO_SIZE_MPU_PM) / 4]; 304 u32 saved_regs_opl3[AZF_ALIGN(AZF_IO_SIZE_OPL3_PM) / 4]; 305 u32 saved_regs_mixer[AZF_ALIGN(AZF_IO_SIZE_MIXER_PM) / 4]; 306 #endif 307 }; 308 309 static const struct pci_device_id snd_azf3328_ids[] = { 310 { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */ 311 { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */ 312 { 0, } 313 }; 314 315 MODULE_DEVICE_TABLE(pci, snd_azf3328_ids); 316 317 318 static int 319 snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set) 320 { 321 /* Well, strictly spoken, the inb/outb sequence isn't atomic 322 and would need locking. However we currently don't care 323 since it potentially complicates matters. */ 324 u8 prev = inb(reg), new; 325 326 new = (do_set) ? (prev|mask) : (prev & ~mask); 327 /* we need to always write the new value no matter whether it differs 328 * or not, since some register bits don't indicate their setting */ 329 outb(new, reg); 330 if (new != prev) 331 return 1; 332 333 return 0; 334 } 335 336 static inline void 337 snd_azf3328_codec_outb(const struct snd_azf3328_codec_data *codec, 338 unsigned reg, 339 u8 value 340 ) 341 { 342 outb(value, codec->io_base + reg); 343 } 344 345 static inline u8 346 snd_azf3328_codec_inb(const struct snd_azf3328_codec_data *codec, unsigned reg) 347 { 348 return inb(codec->io_base + reg); 349 } 350 351 static inline void 352 snd_azf3328_codec_outw(const struct snd_azf3328_codec_data *codec, 353 unsigned reg, 354 u16 value 355 ) 356 { 357 outw(value, codec->io_base + reg); 358 } 359 360 static inline u16 361 snd_azf3328_codec_inw(const struct snd_azf3328_codec_data *codec, unsigned reg) 362 { 363 return inw(codec->io_base + reg); 364 } 365 366 static inline void 367 snd_azf3328_codec_outl(const struct snd_azf3328_codec_data *codec, 368 unsigned reg, 369 u32 value 370 ) 371 { 372 outl(value, codec->io_base + reg); 373 } 374 375 static inline void 376 snd_azf3328_codec_outl_multi(const struct snd_azf3328_codec_data *codec, 377 unsigned reg, const void *buffer, int count 378 ) 379 { 380 unsigned long addr = codec->io_base + reg; 381 if (count) { 382 const u32 *buf = buffer; 383 do { 384 outl(*buf++, addr); 385 addr += 4; 386 } while (--count); 387 } 388 } 389 390 static inline u32 391 snd_azf3328_codec_inl(const struct snd_azf3328_codec_data *codec, unsigned reg) 392 { 393 return inl(codec->io_base + reg); 394 } 395 396 static inline void 397 snd_azf3328_ctrl_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value) 398 { 399 outb(value, chip->ctrl_io + reg); 400 } 401 402 static inline u8 403 snd_azf3328_ctrl_inb(const struct snd_azf3328 *chip, unsigned reg) 404 { 405 return inb(chip->ctrl_io + reg); 406 } 407 408 static inline u16 409 snd_azf3328_ctrl_inw(const struct snd_azf3328 *chip, unsigned reg) 410 { 411 return inw(chip->ctrl_io + reg); 412 } 413 414 static inline void 415 snd_azf3328_ctrl_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) 416 { 417 outw(value, chip->ctrl_io + reg); 418 } 419 420 static inline void 421 snd_azf3328_ctrl_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value) 422 { 423 outl(value, chip->ctrl_io + reg); 424 } 425 426 static inline void 427 snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value) 428 { 429 outb(value, chip->game_io + reg); 430 } 431 432 static inline void 433 snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) 434 { 435 outw(value, chip->game_io + reg); 436 } 437 438 static inline u8 439 snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg) 440 { 441 return inb(chip->game_io + reg); 442 } 443 444 static inline u16 445 snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg) 446 { 447 return inw(chip->game_io + reg); 448 } 449 450 static inline void 451 snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value) 452 { 453 outw(value, chip->mixer_io + reg); 454 } 455 456 static inline u16 457 snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg) 458 { 459 return inw(chip->mixer_io + reg); 460 } 461 462 #define AZF_MUTE_BIT 0x80 463 464 static bool 465 snd_azf3328_mixer_mute_control(const struct snd_azf3328 *chip, 466 unsigned reg, bool do_mute 467 ) 468 { 469 unsigned long portbase = chip->mixer_io + reg + 1; 470 bool updated; 471 472 /* the mute bit is on the *second* (i.e. right) register of a 473 * left/right channel setting */ 474 updated = snd_azf3328_io_reg_setb(portbase, AZF_MUTE_BIT, do_mute); 475 476 /* indicate whether it was muted before */ 477 return (do_mute) ? !updated : updated; 478 } 479 480 static inline bool 481 snd_azf3328_mixer_mute_control_master(const struct snd_azf3328 *chip, 482 bool do_mute 483 ) 484 { 485 return snd_azf3328_mixer_mute_control( 486 chip, 487 IDX_MIXER_PLAY_MASTER, 488 do_mute 489 ); 490 } 491 492 static inline bool 493 snd_azf3328_mixer_mute_control_pcm(const struct snd_azf3328 *chip, 494 bool do_mute 495 ) 496 { 497 return snd_azf3328_mixer_mute_control( 498 chip, 499 IDX_MIXER_WAVEOUT, 500 do_mute 501 ); 502 } 503 504 static inline void 505 snd_azf3328_mixer_reset(const struct snd_azf3328 *chip) 506 { 507 /* reset (close) mixer: 508 * first mute master volume, then reset 509 */ 510 snd_azf3328_mixer_mute_control_master(chip, 1); 511 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000); 512 } 513 514 #ifdef AZF_USE_AC97_LAYER 515 516 static inline void 517 snd_azf3328_mixer_ac97_map_unsupported(const struct snd_azf3328 *chip, 518 unsigned short reg, const char *mode) 519 { 520 /* need to add some more or less clever emulation? */ 521 dev_warn(chip->card->dev, 522 "missing %s emulation for AC97 register 0x%02x!\n", 523 mode, reg); 524 } 525 526 /* 527 * Need to have _special_ AC97 mixer hardware register index mapper, 528 * to compensate for the issue of a rather AC97-incompatible hardware layout. 529 */ 530 #define AZF_REG_MASK 0x3f 531 #define AZF_AC97_REG_UNSUPPORTED 0x8000 532 #define AZF_AC97_REG_REAL_IO_READ 0x4000 533 #define AZF_AC97_REG_REAL_IO_WRITE 0x2000 534 #define AZF_AC97_REG_REAL_IO_RW \ 535 (AZF_AC97_REG_REAL_IO_READ | AZF_AC97_REG_REAL_IO_WRITE) 536 #define AZF_AC97_REG_EMU_IO_READ 0x0400 537 #define AZF_AC97_REG_EMU_IO_WRITE 0x0200 538 #define AZF_AC97_REG_EMU_IO_RW \ 539 (AZF_AC97_REG_EMU_IO_READ | AZF_AC97_REG_EMU_IO_WRITE) 540 static unsigned short 541 snd_azf3328_mixer_ac97_map_reg_idx(unsigned short reg) 542 { 543 static const struct { 544 unsigned short azf_reg; 545 } azf_reg_mapper[] = { 546 /* Especially when taking into consideration 547 * mono/stereo-based sequence of azf vs. AC97 control series, 548 * it's quite obvious that azf simply got rid 549 * of the AC97_HEADPHONE control at its intended offset, 550 * thus shifted _all_ controls by one, 551 * and _then_ simply added it as an FMSYNTH control at the end, 552 * to make up for the offset. 553 * This means we'll have to translate indices here as 554 * needed and then do some tiny AC97 patch action 555 * (snd_ac97_rename_vol_ctl() etc.) - that's it. 556 */ 557 { /* AC97_RESET */ IDX_MIXER_RESET 558 | AZF_AC97_REG_REAL_IO_WRITE 559 | AZF_AC97_REG_EMU_IO_READ }, 560 { /* AC97_MASTER */ IDX_MIXER_PLAY_MASTER }, 561 /* note large shift: AC97_HEADPHONE to IDX_MIXER_FMSYNTH! */ 562 { /* AC97_HEADPHONE */ IDX_MIXER_FMSYNTH }, 563 { /* AC97_MASTER_MONO */ IDX_MIXER_MODEMOUT }, 564 { /* AC97_MASTER_TONE */ IDX_MIXER_BASSTREBLE }, 565 { /* AC97_PC_BEEP */ IDX_MIXER_PCBEEP }, 566 { /* AC97_PHONE */ IDX_MIXER_MODEMIN }, 567 { /* AC97_MIC */ IDX_MIXER_MIC }, 568 { /* AC97_LINE */ IDX_MIXER_LINEIN }, 569 { /* AC97_CD */ IDX_MIXER_CDAUDIO }, 570 { /* AC97_VIDEO */ IDX_MIXER_VIDEO }, 571 { /* AC97_AUX */ IDX_MIXER_AUX }, 572 { /* AC97_PCM */ IDX_MIXER_WAVEOUT }, 573 { /* AC97_REC_SEL */ IDX_MIXER_REC_SELECT }, 574 { /* AC97_REC_GAIN */ IDX_MIXER_REC_VOLUME }, 575 { /* AC97_REC_GAIN_MIC */ AZF_AC97_REG_EMU_IO_RW }, 576 { /* AC97_GENERAL_PURPOSE */ IDX_MIXER_ADVCTL2 }, 577 { /* AC97_3D_CONTROL */ IDX_MIXER_ADVCTL1 }, 578 }; 579 580 unsigned short reg_azf = AZF_AC97_REG_UNSUPPORTED; 581 582 /* azf3328 supports the low-numbered and low-spec:ed range 583 of AC97 regs only */ 584 if (reg <= AC97_3D_CONTROL) { 585 unsigned short reg_idx = reg / 2; 586 reg_azf = azf_reg_mapper[reg_idx].azf_reg; 587 /* a translation-only entry means it's real read/write: */ 588 if (!(reg_azf & ~AZF_REG_MASK)) 589 reg_azf |= AZF_AC97_REG_REAL_IO_RW; 590 } else { 591 switch (reg) { 592 case AC97_POWERDOWN: 593 reg_azf = AZF_AC97_REG_EMU_IO_RW; 594 break; 595 case AC97_EXTENDED_ID: 596 reg_azf = AZF_AC97_REG_EMU_IO_READ; 597 break; 598 case AC97_EXTENDED_STATUS: 599 /* I don't know what the h*ll AC97 layer 600 * would consult this _extended_ register for 601 * given a base-AC97-advertised card, 602 * but let's just emulate it anyway :-P 603 */ 604 reg_azf = AZF_AC97_REG_EMU_IO_RW; 605 break; 606 case AC97_VENDOR_ID1: 607 case AC97_VENDOR_ID2: 608 reg_azf = AZF_AC97_REG_EMU_IO_READ; 609 break; 610 } 611 } 612 return reg_azf; 613 } 614 615 static const unsigned short 616 azf_emulated_ac97_caps = 617 AC97_BC_DEDICATED_MIC | 618 AC97_BC_BASS_TREBLE | 619 /* Headphone is an FM Synth control here */ 620 AC97_BC_HEADPHONE | 621 /* no AC97_BC_LOUDNESS! */ 622 /* mask 0x7c00 is 623 vendor-specific 3D enhancement 624 vendor indicator. 625 Since there actually _is_ an 626 entry for Aztech Labs 627 (13), make damn sure 628 to indicate it. */ 629 (13 << 10); 630 631 static const unsigned short 632 azf_emulated_ac97_powerdown = 633 /* pretend everything to be active */ 634 AC97_PD_ADC_STATUS | 635 AC97_PD_DAC_STATUS | 636 AC97_PD_MIXER_STATUS | 637 AC97_PD_VREF_STATUS; 638 639 /* 640 * Emulated, _inofficial_ vendor ID 641 * (there might be some devices such as the MR 2800-W 642 * which could reveal the real Aztech AC97 ID). 643 * We choose to use "AZT" prefix, and then use 1 to indicate PCI168 644 * (better don't use 0x68 since there's a PCI368 as well). 645 */ 646 static const unsigned int 647 azf_emulated_ac97_vendor_id = 0x415a5401; 648 649 static unsigned short 650 snd_azf3328_mixer_ac97_read(struct snd_ac97 *ac97, unsigned short reg_ac97) 651 { 652 const struct snd_azf3328 *chip = ac97->private_data; 653 unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97); 654 unsigned short reg_val = 0; 655 bool unsupported = false; 656 657 dev_dbg(chip->card->dev, "snd_azf3328_mixer_ac97_read reg_ac97 %u\n", 658 reg_ac97); 659 if (reg_azf & AZF_AC97_REG_UNSUPPORTED) 660 unsupported = true; 661 else { 662 if (reg_azf & AZF_AC97_REG_REAL_IO_READ) 663 reg_val = snd_azf3328_mixer_inw(chip, 664 reg_azf & AZF_REG_MASK); 665 else { 666 /* 667 * Proceed with dummy I/O read, 668 * to ensure compatible timing where this may matter. 669 * (ALSA AC97 layer usually doesn't call I/O functions 670 * due to intelligent I/O caching anyway) 671 * Choose a mixer register that's thoroughly unrelated 672 * to common audio (try to minimize distortion). 673 */ 674 snd_azf3328_mixer_inw(chip, IDX_MIXER_SOMETHING30H); 675 } 676 677 if (reg_azf & AZF_AC97_REG_EMU_IO_READ) { 678 switch (reg_ac97) { 679 case AC97_RESET: 680 reg_val |= azf_emulated_ac97_caps; 681 break; 682 case AC97_POWERDOWN: 683 reg_val |= azf_emulated_ac97_powerdown; 684 break; 685 case AC97_EXTENDED_ID: 686 case AC97_EXTENDED_STATUS: 687 /* AFAICS we simply can't support anything: */ 688 reg_val |= 0; 689 break; 690 case AC97_VENDOR_ID1: 691 reg_val = azf_emulated_ac97_vendor_id >> 16; 692 break; 693 case AC97_VENDOR_ID2: 694 reg_val = azf_emulated_ac97_vendor_id & 0xffff; 695 break; 696 default: 697 unsupported = true; 698 break; 699 } 700 } 701 } 702 if (unsupported) 703 snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "read"); 704 705 return reg_val; 706 } 707 708 static void 709 snd_azf3328_mixer_ac97_write(struct snd_ac97 *ac97, 710 unsigned short reg_ac97, unsigned short val) 711 { 712 const struct snd_azf3328 *chip = ac97->private_data; 713 unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97); 714 bool unsupported = false; 715 716 dev_dbg(chip->card->dev, 717 "snd_azf3328_mixer_ac97_write reg_ac97 %u val %u\n", 718 reg_ac97, val); 719 if (reg_azf & AZF_AC97_REG_UNSUPPORTED) 720 unsupported = true; 721 else { 722 if (reg_azf & AZF_AC97_REG_REAL_IO_WRITE) 723 snd_azf3328_mixer_outw( 724 chip, 725 reg_azf & AZF_REG_MASK, 726 val 727 ); 728 else 729 if (reg_azf & AZF_AC97_REG_EMU_IO_WRITE) { 730 switch (reg_ac97) { 731 case AC97_REC_GAIN_MIC: 732 case AC97_POWERDOWN: 733 case AC97_EXTENDED_STATUS: 734 /* 735 * Silently swallow these writes. 736 * Since for most registers our card doesn't 737 * actually support a comparable feature, 738 * this is exactly what we should do here. 739 * The AC97 layer's I/O caching probably 740 * automatically takes care of all the rest... 741 * (remembers written values etc.) 742 */ 743 break; 744 default: 745 unsupported = true; 746 break; 747 } 748 } 749 } 750 if (unsupported) 751 snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "write"); 752 } 753 754 static int 755 snd_azf3328_mixer_new(struct snd_azf3328 *chip) 756 { 757 struct snd_ac97_bus *bus; 758 struct snd_ac97_template ac97; 759 static const struct snd_ac97_bus_ops ops = { 760 .write = snd_azf3328_mixer_ac97_write, 761 .read = snd_azf3328_mixer_ac97_read, 762 }; 763 int rc; 764 765 memset(&ac97, 0, sizeof(ac97)); 766 ac97.scaps = AC97_SCAP_SKIP_MODEM 767 | AC97_SCAP_AUDIO /* we support audio! */ 768 | AC97_SCAP_NO_SPDIF; 769 ac97.private_data = chip; 770 ac97.pci = chip->pci; 771 772 /* 773 * ALSA's AC97 layer has terrible init crackling issues, 774 * unfortunately, and since it makes use of AC97_RESET, 775 * there's no use trying to mute Master Playback proactively. 776 */ 777 778 rc = snd_ac97_bus(chip->card, 0, &ops, NULL, &bus); 779 if (!rc) 780 rc = snd_ac97_mixer(bus, &ac97, &chip->ac97); 781 /* 782 * Make sure to complain loudly in case of AC97 init failure, 783 * since failure may happen quite often, 784 * due to this card being a very quirky AC97 "lookalike". 785 */ 786 if (rc) 787 dev_err(chip->card->dev, "AC97 init failed, err %d!\n", rc); 788 789 /* If we return an error here, then snd_card_free() should 790 * free up any ac97 codecs that got created, as well as the bus. 791 */ 792 return rc; 793 } 794 #else /* AZF_USE_AC97_LAYER */ 795 static void 796 snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip, 797 unsigned reg, 798 unsigned char dst_vol_left, 799 unsigned char dst_vol_right, 800 int chan_sel, int delay 801 ) 802 { 803 unsigned long portbase = chip->mixer_io + reg; 804 unsigned char curr_vol_left = 0, curr_vol_right = 0; 805 int left_change = 0, right_change = 0; 806 807 if (chan_sel & SET_CHAN_LEFT) { 808 curr_vol_left = inb(portbase + 1); 809 810 /* take care of muting flag contained in left channel */ 811 if (curr_vol_left & AZF_MUTE_BIT) 812 dst_vol_left |= AZF_MUTE_BIT; 813 else 814 dst_vol_left &= ~AZF_MUTE_BIT; 815 816 left_change = (curr_vol_left > dst_vol_left) ? -1 : 1; 817 } 818 819 if (chan_sel & SET_CHAN_RIGHT) { 820 curr_vol_right = inb(portbase + 0); 821 822 right_change = (curr_vol_right > dst_vol_right) ? -1 : 1; 823 } 824 825 do { 826 if (left_change) { 827 if (curr_vol_left != dst_vol_left) { 828 curr_vol_left += left_change; 829 outb(curr_vol_left, portbase + 1); 830 } else 831 left_change = 0; 832 } 833 if (right_change) { 834 if (curr_vol_right != dst_vol_right) { 835 curr_vol_right += right_change; 836 837 /* during volume change, the right channel is crackling 838 * somewhat more than the left channel, unfortunately. 839 * This seems to be a hardware issue. */ 840 outb(curr_vol_right, portbase + 0); 841 } else 842 right_change = 0; 843 } 844 if (delay) 845 mdelay(delay); 846 } while ((left_change) || (right_change)); 847 } 848 849 /* 850 * general mixer element 851 */ 852 struct azf3328_mixer_reg { 853 unsigned reg; 854 unsigned int lchan_shift, rchan_shift; 855 unsigned int mask; 856 unsigned int invert: 1; 857 unsigned int stereo: 1; 858 unsigned int enum_c: 4; 859 }; 860 861 #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \ 862 ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \ 863 (mask << 16) | \ 864 (invert << 24) | \ 865 (stereo << 25) | \ 866 (enum_c << 26)) 867 868 static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val) 869 { 870 r->reg = val & 0xff; 871 r->lchan_shift = (val >> 8) & 0x0f; 872 r->rchan_shift = (val >> 12) & 0x0f; 873 r->mask = (val >> 16) & 0xff; 874 r->invert = (val >> 24) & 1; 875 r->stereo = (val >> 25) & 1; 876 r->enum_c = (val >> 26) & 0x0f; 877 } 878 879 /* 880 * mixer switches/volumes 881 */ 882 883 #define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \ 884 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 885 .info = snd_azf3328_info_mixer, \ 886 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 887 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \ 888 } 889 890 #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \ 891 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 892 .info = snd_azf3328_info_mixer, \ 893 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 894 .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \ 895 } 896 897 #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \ 898 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 899 .info = snd_azf3328_info_mixer, \ 900 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 901 .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \ 902 } 903 904 #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \ 905 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 906 .info = snd_azf3328_info_mixer, \ 907 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \ 908 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \ 909 } 910 911 #define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \ 912 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 913 .info = snd_azf3328_info_mixer_enum, \ 914 .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \ 915 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \ 916 } 917 918 static int 919 snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol, 920 struct snd_ctl_elem_info *uinfo) 921 { 922 struct azf3328_mixer_reg reg; 923 924 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 925 uinfo->type = reg.mask == 1 ? 926 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 927 uinfo->count = reg.stereo + 1; 928 uinfo->value.integer.min = 0; 929 uinfo->value.integer.max = reg.mask; 930 return 0; 931 } 932 933 static int 934 snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol, 935 struct snd_ctl_elem_value *ucontrol) 936 { 937 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 938 struct azf3328_mixer_reg reg; 939 u16 oreg, val; 940 941 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 942 943 oreg = snd_azf3328_mixer_inw(chip, reg.reg); 944 val = (oreg >> reg.lchan_shift) & reg.mask; 945 if (reg.invert) 946 val = reg.mask - val; 947 ucontrol->value.integer.value[0] = val; 948 if (reg.stereo) { 949 val = (oreg >> reg.rchan_shift) & reg.mask; 950 if (reg.invert) 951 val = reg.mask - val; 952 ucontrol->value.integer.value[1] = val; 953 } 954 dev_dbg(chip->card->dev, 955 "get: %02x is %04x -> vol %02lx|%02lx (shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n", 956 reg.reg, oreg, 957 ucontrol->value.integer.value[0], ucontrol->value.integer.value[1], 958 reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo); 959 return 0; 960 } 961 962 static int 963 snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol, 964 struct snd_ctl_elem_value *ucontrol) 965 { 966 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 967 struct azf3328_mixer_reg reg; 968 u16 oreg, nreg, val; 969 970 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 971 oreg = snd_azf3328_mixer_inw(chip, reg.reg); 972 val = ucontrol->value.integer.value[0] & reg.mask; 973 if (reg.invert) 974 val = reg.mask - val; 975 nreg = oreg & ~(reg.mask << reg.lchan_shift); 976 nreg |= (val << reg.lchan_shift); 977 if (reg.stereo) { 978 val = ucontrol->value.integer.value[1] & reg.mask; 979 if (reg.invert) 980 val = reg.mask - val; 981 nreg &= ~(reg.mask << reg.rchan_shift); 982 nreg |= (val << reg.rchan_shift); 983 } 984 if (reg.mask >= 0x07) /* it's a volume control, so better take care */ 985 snd_azf3328_mixer_write_volume_gradually( 986 chip, reg.reg, nreg >> 8, nreg & 0xff, 987 /* just set both channels, doesn't matter */ 988 SET_CHAN_LEFT|SET_CHAN_RIGHT, 989 0); 990 else 991 snd_azf3328_mixer_outw(chip, reg.reg, nreg); 992 993 dev_dbg(chip->card->dev, 994 "put: %02x to %02lx|%02lx, oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n", 995 reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1], 996 oreg, reg.lchan_shift, reg.rchan_shift, 997 nreg, snd_azf3328_mixer_inw(chip, reg.reg)); 998 return (nreg != oreg); 999 } 1000 1001 static int 1002 snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol, 1003 struct snd_ctl_elem_info *uinfo) 1004 { 1005 static const char * const texts1[] = { 1006 "Mic1", "Mic2" 1007 }; 1008 static const char * const texts2[] = { 1009 "Mix", "Mic" 1010 }; 1011 static const char * const texts3[] = { 1012 "Mic", "CD", "Video", "Aux", 1013 "Line", "Mix", "Mix Mono", "Phone" 1014 }; 1015 static const char * const texts4[] = { 1016 "pre 3D", "post 3D" 1017 }; 1018 struct azf3328_mixer_reg reg; 1019 const char * const *p = NULL; 1020 1021 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 1022 if (reg.reg == IDX_MIXER_ADVCTL2) { 1023 switch(reg.lchan_shift) { 1024 case 8: /* modem out sel */ 1025 p = texts1; 1026 break; 1027 case 9: /* mono sel source */ 1028 p = texts2; 1029 break; 1030 case 15: /* PCM Out Path */ 1031 p = texts4; 1032 break; 1033 } 1034 } else if (reg.reg == IDX_MIXER_REC_SELECT) 1035 p = texts3; 1036 1037 return snd_ctl_enum_info(uinfo, 1038 (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1, 1039 reg.enum_c, p); 1040 } 1041 1042 static int 1043 snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol, 1044 struct snd_ctl_elem_value *ucontrol) 1045 { 1046 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 1047 struct azf3328_mixer_reg reg; 1048 unsigned short val; 1049 1050 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 1051 val = snd_azf3328_mixer_inw(chip, reg.reg); 1052 if (reg.reg == IDX_MIXER_REC_SELECT) { 1053 ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1); 1054 ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1); 1055 } else 1056 ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1); 1057 1058 dev_dbg(chip->card->dev, 1059 "get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n", 1060 reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1], 1061 reg.lchan_shift, reg.enum_c); 1062 return 0; 1063 } 1064 1065 static int 1066 snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol, 1067 struct snd_ctl_elem_value *ucontrol) 1068 { 1069 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol); 1070 struct azf3328_mixer_reg reg; 1071 u16 oreg, nreg, val; 1072 1073 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value); 1074 oreg = snd_azf3328_mixer_inw(chip, reg.reg); 1075 val = oreg; 1076 if (reg.reg == IDX_MIXER_REC_SELECT) { 1077 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U || 1078 ucontrol->value.enumerated.item[1] > reg.enum_c - 1U) 1079 return -EINVAL; 1080 val = (ucontrol->value.enumerated.item[0] << 8) | 1081 (ucontrol->value.enumerated.item[1] << 0); 1082 } else { 1083 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U) 1084 return -EINVAL; 1085 val &= ~((reg.enum_c - 1) << reg.lchan_shift); 1086 val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift); 1087 } 1088 snd_azf3328_mixer_outw(chip, reg.reg, val); 1089 nreg = val; 1090 1091 dev_dbg(chip->card->dev, 1092 "put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg); 1093 return (nreg != oreg); 1094 } 1095 1096 static const struct snd_kcontrol_new snd_azf3328_mixer_controls[] = { 1097 AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1), 1098 AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1), 1099 AZF3328_MIXER_SWITCH("PCM Playback Switch", IDX_MIXER_WAVEOUT, 15, 1), 1100 AZF3328_MIXER_VOL_STEREO("PCM Playback Volume", 1101 IDX_MIXER_WAVEOUT, 0x1f, 1), 1102 AZF3328_MIXER_SWITCH("PCM 3D Bypass Playback Switch", 1103 IDX_MIXER_ADVCTL2, 7, 1), 1104 AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1), 1105 AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1), 1106 AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1), 1107 AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1), 1108 AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1), 1109 AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0), 1110 AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0), 1111 AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1), 1112 AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1), 1113 AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0), 1114 AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1), 1115 AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1), 1116 AZF3328_MIXER_SWITCH("Beep Playback Switch", IDX_MIXER_PCBEEP, 15, 1), 1117 AZF3328_MIXER_VOL_SPECIAL("Beep Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1), 1118 AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1), 1119 AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1), 1120 AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1), 1121 AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1), 1122 AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1), 1123 AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1), 1124 AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1), 1125 AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1), 1126 AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8), 1127 AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9), 1128 AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */ 1129 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0), 1130 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0), 1131 AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0), 1132 AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */ 1133 AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */ 1134 #if MIXER_TESTING 1135 AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0), 1136 AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0), 1137 AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0), 1138 AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0), 1139 AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0), 1140 AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0), 1141 AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0), 1142 AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0), 1143 AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0), 1144 AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0), 1145 AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0), 1146 AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0), 1147 AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0), 1148 AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0), 1149 AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0), 1150 AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0), 1151 #endif 1152 }; 1153 1154 static const u16 snd_azf3328_init_values[][2] = { 1155 { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f }, 1156 { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f }, 1157 { IDX_MIXER_BASSTREBLE, 0x0000 }, 1158 { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f }, 1159 { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f }, 1160 { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f }, 1161 { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f }, 1162 { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f }, 1163 { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f }, 1164 { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f }, 1165 { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f }, 1166 { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f }, 1167 { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 }, 1168 }; 1169 1170 static int 1171 snd_azf3328_mixer_new(struct snd_azf3328 *chip) 1172 { 1173 struct snd_card *card; 1174 const struct snd_kcontrol_new *sw; 1175 unsigned int idx; 1176 int err; 1177 1178 if (snd_BUG_ON(!chip || !chip->card)) 1179 return -EINVAL; 1180 1181 card = chip->card; 1182 1183 /* mixer reset */ 1184 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000); 1185 1186 /* mute and zero volume channels */ 1187 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); ++idx) { 1188 snd_azf3328_mixer_outw(chip, 1189 snd_azf3328_init_values[idx][0], 1190 snd_azf3328_init_values[idx][1]); 1191 } 1192 1193 /* add mixer controls */ 1194 sw = snd_azf3328_mixer_controls; 1195 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls); 1196 ++idx, ++sw) { 1197 err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip)); 1198 if (err < 0) 1199 return err; 1200 } 1201 snd_component_add(card, "AZF3328 mixer"); 1202 strcpy(card->mixername, "AZF3328 mixer"); 1203 1204 return 0; 1205 } 1206 #endif /* AZF_USE_AC97_LAYER */ 1207 1208 static void 1209 snd_azf3328_codec_setfmt(struct snd_azf3328_codec_data *codec, 1210 enum azf_freq_t bitrate, 1211 unsigned int format_width, 1212 unsigned int channels 1213 ) 1214 { 1215 unsigned long flags; 1216 u16 val = 0xff00; 1217 u8 freq = 0; 1218 1219 switch (bitrate) { 1220 case AZF_FREQ_4000: freq = SOUNDFORMAT_FREQ_SUSPECTED_4000; break; 1221 case AZF_FREQ_4800: freq = SOUNDFORMAT_FREQ_SUSPECTED_4800; break; 1222 case AZF_FREQ_5512: 1223 /* the AZF3328 names it "5510" for some strange reason */ 1224 freq = SOUNDFORMAT_FREQ_5510; break; 1225 case AZF_FREQ_6620: freq = SOUNDFORMAT_FREQ_6620; break; 1226 case AZF_FREQ_8000: freq = SOUNDFORMAT_FREQ_8000; break; 1227 case AZF_FREQ_9600: freq = SOUNDFORMAT_FREQ_9600; break; 1228 case AZF_FREQ_11025: freq = SOUNDFORMAT_FREQ_11025; break; 1229 case AZF_FREQ_13240: freq = SOUNDFORMAT_FREQ_SUSPECTED_13240; break; 1230 case AZF_FREQ_16000: freq = SOUNDFORMAT_FREQ_16000; break; 1231 case AZF_FREQ_22050: freq = SOUNDFORMAT_FREQ_22050; break; 1232 case AZF_FREQ_32000: freq = SOUNDFORMAT_FREQ_32000; break; 1233 default: 1234 snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate); 1235 fallthrough; 1236 case AZF_FREQ_44100: freq = SOUNDFORMAT_FREQ_44100; break; 1237 case AZF_FREQ_48000: freq = SOUNDFORMAT_FREQ_48000; break; 1238 case AZF_FREQ_66200: freq = SOUNDFORMAT_FREQ_SUSPECTED_66200; break; 1239 } 1240 /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */ 1241 /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */ 1242 /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */ 1243 /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */ 1244 /* val = 0xff05; 5m11.556s (... -> 44100Hz) */ 1245 /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */ 1246 /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */ 1247 /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */ 1248 /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */ 1249 1250 val |= freq; 1251 1252 if (channels == 2) 1253 val |= SOUNDFORMAT_FLAG_2CHANNELS; 1254 1255 if (format_width == 16) 1256 val |= SOUNDFORMAT_FLAG_16BIT; 1257 1258 spin_lock_irqsave(codec->lock, flags); 1259 1260 /* set bitrate/format */ 1261 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_SOUNDFORMAT, val); 1262 1263 /* changing the bitrate/format settings switches off the 1264 * audio output with an annoying click in case of 8/16bit format change 1265 * (maybe shutting down DAC/ADC?), thus immediately 1266 * do some tweaking to reenable it and get rid of the clicking 1267 * (FIXME: yes, it works, but what exactly am I doing here?? :) 1268 * FIXME: does this have some side effects for full-duplex 1269 * or other dramatic side effects? */ 1270 /* do it for non-capture codecs only */ 1271 if (codec->type != AZF_CODEC_CAPTURE) 1272 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1273 snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS) | 1274 DMA_RUN_SOMETHING1 | 1275 DMA_RUN_SOMETHING2 | 1276 SOMETHING_ALMOST_ALWAYS_SET | 1277 DMA_EPILOGUE_SOMETHING | 1278 DMA_SOMETHING_ELSE 1279 ); 1280 1281 spin_unlock_irqrestore(codec->lock, flags); 1282 } 1283 1284 static inline void 1285 snd_azf3328_codec_setfmt_lowpower(struct snd_azf3328_codec_data *codec 1286 ) 1287 { 1288 /* choose lowest frequency for low power consumption. 1289 * While this will cause louder noise due to rather coarse frequency, 1290 * it should never matter since output should always 1291 * get disabled properly when idle anyway. */ 1292 snd_azf3328_codec_setfmt(codec, AZF_FREQ_4000, 8, 1); 1293 } 1294 1295 static void 1296 snd_azf3328_ctrl_reg_6AH_update(struct snd_azf3328 *chip, 1297 unsigned bitmask, 1298 bool enable 1299 ) 1300 { 1301 bool do_mask = !enable; 1302 if (do_mask) 1303 chip->shadow_reg_ctrl_6AH |= bitmask; 1304 else 1305 chip->shadow_reg_ctrl_6AH &= ~bitmask; 1306 dev_dbg(chip->card->dev, 1307 "6AH_update mask 0x%04x do_mask %d: val 0x%04x\n", 1308 bitmask, do_mask, chip->shadow_reg_ctrl_6AH); 1309 snd_azf3328_ctrl_outw(chip, IDX_IO_6AH, chip->shadow_reg_ctrl_6AH); 1310 } 1311 1312 static inline void 1313 snd_azf3328_ctrl_enable_codecs(struct snd_azf3328 *chip, bool enable) 1314 { 1315 dev_dbg(chip->card->dev, "codec_enable %d\n", enable); 1316 /* no idea what exactly is being done here, but I strongly assume it's 1317 * PM related */ 1318 snd_azf3328_ctrl_reg_6AH_update( 1319 chip, IO_6A_PAUSE_PLAYBACK_BIT8, enable 1320 ); 1321 } 1322 1323 static void 1324 snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip, 1325 enum snd_azf3328_codec_type codec_type, 1326 bool enable 1327 ) 1328 { 1329 struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type]; 1330 bool need_change = (codec->running != enable); 1331 1332 dev_dbg(chip->card->dev, 1333 "codec_activity: %s codec, enable %d, need_change %d\n", 1334 codec->name, enable, need_change 1335 ); 1336 if (need_change) { 1337 static const struct { 1338 enum snd_azf3328_codec_type other1; 1339 enum snd_azf3328_codec_type other2; 1340 } peer_codecs[3] = 1341 { { AZF_CODEC_CAPTURE, AZF_CODEC_I2S_OUT }, 1342 { AZF_CODEC_PLAYBACK, AZF_CODEC_I2S_OUT }, 1343 { AZF_CODEC_PLAYBACK, AZF_CODEC_CAPTURE } }; 1344 bool call_function; 1345 1346 if (enable) 1347 /* if enable codec, call enable_codecs func 1348 to enable codec supply... */ 1349 call_function = 1; 1350 else { 1351 /* ...otherwise call enable_codecs func 1352 (which globally shuts down operation of codecs) 1353 only in case the other codecs are currently 1354 not active either! */ 1355 call_function = 1356 ((!chip->codecs[peer_codecs[codec_type].other1] 1357 .running) 1358 && (!chip->codecs[peer_codecs[codec_type].other2] 1359 .running)); 1360 } 1361 if (call_function) 1362 snd_azf3328_ctrl_enable_codecs(chip, enable); 1363 1364 /* ...and adjust clock, too 1365 * (reduce noise and power consumption) */ 1366 if (!enable) 1367 snd_azf3328_codec_setfmt_lowpower(codec); 1368 codec->running = enable; 1369 } 1370 } 1371 1372 static void 1373 snd_azf3328_codec_setdmaa(struct snd_azf3328 *chip, 1374 struct snd_azf3328_codec_data *codec, 1375 unsigned long addr, 1376 unsigned int period_bytes, 1377 unsigned int buffer_bytes 1378 ) 1379 { 1380 WARN_ONCE(period_bytes & 1, "odd period length!?\n"); 1381 WARN_ONCE(buffer_bytes != 2 * period_bytes, 1382 "missed our input expectations! %u vs. %u\n", 1383 buffer_bytes, period_bytes); 1384 if (!codec->running) { 1385 /* AZF3328 uses a two buffer pointer DMA transfer approach */ 1386 1387 unsigned long flags; 1388 1389 /* width 32bit (prevent overflow): */ 1390 u32 area_length; 1391 struct codec_setup_io { 1392 u32 dma_start_1; 1393 u32 dma_start_2; 1394 u32 dma_lengths; 1395 } __attribute__((packed)) setup_io; 1396 1397 area_length = buffer_bytes/2; 1398 1399 setup_io.dma_start_1 = addr; 1400 setup_io.dma_start_2 = addr+area_length; 1401 1402 dev_dbg(chip->card->dev, 1403 "setdma: buffers %08x[%u] / %08x[%u], %u, %u\n", 1404 setup_io.dma_start_1, area_length, 1405 setup_io.dma_start_2, area_length, 1406 period_bytes, buffer_bytes); 1407 1408 /* Hmm, are we really supposed to decrement this by 1?? 1409 Most definitely certainly not: configuring full length does 1410 work properly (i.e. likely better), and BTW we 1411 violated possibly differing frame sizes with this... 1412 1413 area_length--; |* max. index *| 1414 */ 1415 1416 /* build combined I/O buffer length word */ 1417 setup_io.dma_lengths = (area_length << 16) | (area_length); 1418 1419 spin_lock_irqsave(codec->lock, flags); 1420 snd_azf3328_codec_outl_multi( 1421 codec, IDX_IO_CODEC_DMA_START_1, &setup_io, 3 1422 ); 1423 spin_unlock_irqrestore(codec->lock, flags); 1424 } 1425 } 1426 1427 static int 1428 snd_azf3328_pcm_prepare(struct snd_pcm_substream *substream) 1429 { 1430 struct snd_pcm_runtime *runtime = substream->runtime; 1431 struct snd_azf3328_codec_data *codec = runtime->private_data; 1432 #if 0 1433 unsigned int size = snd_pcm_lib_buffer_bytes(substream); 1434 unsigned int count = snd_pcm_lib_period_bytes(substream); 1435 #endif 1436 1437 codec->dma_base = runtime->dma_addr; 1438 1439 #if 0 1440 snd_azf3328_codec_setfmt(codec, 1441 runtime->rate, 1442 snd_pcm_format_width(runtime->format), 1443 runtime->channels); 1444 snd_azf3328_codec_setdmaa(chip, codec, 1445 runtime->dma_addr, count, size); 1446 #endif 1447 return 0; 1448 } 1449 1450 static int 1451 snd_azf3328_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1452 { 1453 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 1454 struct snd_pcm_runtime *runtime = substream->runtime; 1455 struct snd_azf3328_codec_data *codec = runtime->private_data; 1456 int result = 0; 1457 u16 flags1; 1458 bool previously_muted = false; 1459 bool is_main_mixer_playback_codec = (AZF_CODEC_PLAYBACK == codec->type); 1460 1461 switch (cmd) { 1462 case SNDRV_PCM_TRIGGER_START: 1463 dev_dbg(chip->card->dev, "START PCM %s\n", codec->name); 1464 1465 if (is_main_mixer_playback_codec) { 1466 /* mute WaveOut (avoid clicking during setup) */ 1467 previously_muted = 1468 snd_azf3328_mixer_mute_control_pcm( 1469 chip, 1 1470 ); 1471 } 1472 1473 snd_azf3328_codec_setfmt(codec, 1474 runtime->rate, 1475 snd_pcm_format_width(runtime->format), 1476 runtime->channels); 1477 1478 spin_lock(codec->lock); 1479 /* first, remember current value: */ 1480 flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS); 1481 1482 /* stop transfer */ 1483 flags1 &= ~DMA_RESUME; 1484 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1485 1486 /* FIXME: clear interrupts or what??? */ 1487 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_IRQTYPE, 0xffff); 1488 spin_unlock(codec->lock); 1489 1490 snd_azf3328_codec_setdmaa(chip, codec, runtime->dma_addr, 1491 snd_pcm_lib_period_bytes(substream), 1492 snd_pcm_lib_buffer_bytes(substream) 1493 ); 1494 1495 spin_lock(codec->lock); 1496 #ifdef WIN9X 1497 /* FIXME: enable playback/recording??? */ 1498 flags1 |= DMA_RUN_SOMETHING1 | DMA_RUN_SOMETHING2; 1499 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1500 1501 /* start transfer again */ 1502 /* FIXME: what is this value (0x0010)??? */ 1503 flags1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING; 1504 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1505 #else /* NT4 */ 1506 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1507 0x0000); 1508 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1509 DMA_RUN_SOMETHING1); 1510 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1511 DMA_RUN_SOMETHING1 | 1512 DMA_RUN_SOMETHING2); 1513 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1514 DMA_RESUME | 1515 SOMETHING_ALMOST_ALWAYS_SET | 1516 DMA_EPILOGUE_SOMETHING | 1517 DMA_SOMETHING_ELSE); 1518 #endif 1519 spin_unlock(codec->lock); 1520 snd_azf3328_ctrl_codec_activity(chip, codec->type, 1); 1521 1522 if (is_main_mixer_playback_codec) { 1523 /* now unmute WaveOut */ 1524 if (!previously_muted) 1525 snd_azf3328_mixer_mute_control_pcm( 1526 chip, 0 1527 ); 1528 } 1529 1530 dev_dbg(chip->card->dev, "PCM STARTED %s\n", codec->name); 1531 break; 1532 case SNDRV_PCM_TRIGGER_RESUME: 1533 dev_dbg(chip->card->dev, "PCM RESUME %s\n", codec->name); 1534 /* resume codec if we were active */ 1535 spin_lock(codec->lock); 1536 if (codec->running) 1537 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1538 snd_azf3328_codec_inw( 1539 codec, IDX_IO_CODEC_DMA_FLAGS 1540 ) | DMA_RESUME 1541 ); 1542 spin_unlock(codec->lock); 1543 break; 1544 case SNDRV_PCM_TRIGGER_STOP: 1545 dev_dbg(chip->card->dev, "PCM STOP %s\n", codec->name); 1546 1547 if (is_main_mixer_playback_codec) { 1548 /* mute WaveOut (avoid clicking during setup) */ 1549 previously_muted = 1550 snd_azf3328_mixer_mute_control_pcm( 1551 chip, 1 1552 ); 1553 } 1554 1555 spin_lock(codec->lock); 1556 /* first, remember current value: */ 1557 flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS); 1558 1559 /* stop transfer */ 1560 flags1 &= ~DMA_RESUME; 1561 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1562 1563 /* hmm, is this really required? we're resetting the same bit 1564 * immediately thereafter... */ 1565 flags1 |= DMA_RUN_SOMETHING1; 1566 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1567 1568 flags1 &= ~DMA_RUN_SOMETHING1; 1569 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1); 1570 spin_unlock(codec->lock); 1571 snd_azf3328_ctrl_codec_activity(chip, codec->type, 0); 1572 1573 if (is_main_mixer_playback_codec) { 1574 /* now unmute WaveOut */ 1575 if (!previously_muted) 1576 snd_azf3328_mixer_mute_control_pcm( 1577 chip, 0 1578 ); 1579 } 1580 1581 dev_dbg(chip->card->dev, "PCM STOPPED %s\n", codec->name); 1582 break; 1583 case SNDRV_PCM_TRIGGER_SUSPEND: 1584 dev_dbg(chip->card->dev, "PCM SUSPEND %s\n", codec->name); 1585 /* make sure codec is stopped */ 1586 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, 1587 snd_azf3328_codec_inw( 1588 codec, IDX_IO_CODEC_DMA_FLAGS 1589 ) & ~DMA_RESUME 1590 ); 1591 break; 1592 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1593 WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n"); 1594 break; 1595 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1596 WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n"); 1597 break; 1598 default: 1599 WARN(1, "FIXME: unknown trigger mode!\n"); 1600 return -EINVAL; 1601 } 1602 1603 return result; 1604 } 1605 1606 static snd_pcm_uframes_t 1607 snd_azf3328_pcm_pointer(struct snd_pcm_substream *substream 1608 ) 1609 { 1610 const struct snd_azf3328_codec_data *codec = 1611 substream->runtime->private_data; 1612 unsigned long result; 1613 snd_pcm_uframes_t frmres; 1614 1615 result = snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_CURRPOS); 1616 1617 /* calculate offset */ 1618 #ifdef QUERY_HARDWARE 1619 result -= snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_START_1); 1620 #else 1621 result -= codec->dma_base; 1622 #endif 1623 frmres = bytes_to_frames( substream->runtime, result); 1624 dev_dbg(substream->pcm->card->dev, "%08li %s @ 0x%8lx, frames %8ld\n", 1625 jiffies, codec->name, result, frmres); 1626 return frmres; 1627 } 1628 1629 /******************************************************************/ 1630 1631 #ifdef SUPPORT_GAMEPORT 1632 static inline void 1633 snd_azf3328_gameport_irq_enable(struct snd_azf3328 *chip, 1634 bool enable 1635 ) 1636 { 1637 snd_azf3328_io_reg_setb( 1638 chip->game_io+IDX_GAME_HWCONFIG, 1639 GAME_HWCFG_IRQ_ENABLE, 1640 enable 1641 ); 1642 } 1643 1644 static inline void 1645 snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip, 1646 bool enable 1647 ) 1648 { 1649 snd_azf3328_io_reg_setb( 1650 chip->game_io+IDX_GAME_HWCONFIG, 1651 GAME_HWCFG_LEGACY_ADDRESS_ENABLE, 1652 enable 1653 ); 1654 } 1655 1656 static void 1657 snd_azf3328_gameport_set_counter_frequency(struct snd_azf3328 *chip, 1658 unsigned int freq_cfg 1659 ) 1660 { 1661 snd_azf3328_io_reg_setb( 1662 chip->game_io+IDX_GAME_HWCONFIG, 1663 0x02, 1664 (freq_cfg & 1) != 0 1665 ); 1666 snd_azf3328_io_reg_setb( 1667 chip->game_io+IDX_GAME_HWCONFIG, 1668 0x04, 1669 (freq_cfg & 2) != 0 1670 ); 1671 } 1672 1673 static inline void 1674 snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, bool enable) 1675 { 1676 snd_azf3328_ctrl_reg_6AH_update( 1677 chip, IO_6A_SOMETHING2_GAMEPORT, enable 1678 ); 1679 } 1680 1681 static inline void 1682 snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip) 1683 { 1684 /* 1685 * skeleton handler only 1686 * (we do not want axis reading in interrupt handler - too much load!) 1687 */ 1688 dev_dbg(chip->card->dev, "gameport irq\n"); 1689 1690 /* this should ACK the gameport IRQ properly, hopefully. */ 1691 snd_azf3328_game_inw(chip, IDX_GAME_AXIS_VALUE); 1692 } 1693 1694 static int 1695 snd_azf3328_gameport_open(struct gameport *gameport, int mode) 1696 { 1697 struct snd_azf3328 *chip = gameport_get_port_data(gameport); 1698 int res; 1699 1700 dev_dbg(chip->card->dev, "gameport_open, mode %d\n", mode); 1701 switch (mode) { 1702 case GAMEPORT_MODE_COOKED: 1703 case GAMEPORT_MODE_RAW: 1704 res = 0; 1705 break; 1706 default: 1707 res = -1; 1708 break; 1709 } 1710 1711 snd_azf3328_gameport_set_counter_frequency(chip, 1712 GAME_HWCFG_ADC_COUNTER_FREQ_STD); 1713 snd_azf3328_gameport_axis_circuit_enable(chip, (res == 0)); 1714 1715 return res; 1716 } 1717 1718 static void 1719 snd_azf3328_gameport_close(struct gameport *gameport) 1720 { 1721 struct snd_azf3328 *chip = gameport_get_port_data(gameport); 1722 1723 dev_dbg(chip->card->dev, "gameport_close\n"); 1724 snd_azf3328_gameport_set_counter_frequency(chip, 1725 GAME_HWCFG_ADC_COUNTER_FREQ_1_200); 1726 snd_azf3328_gameport_axis_circuit_enable(chip, 0); 1727 } 1728 1729 static int 1730 snd_azf3328_gameport_cooked_read(struct gameport *gameport, 1731 int *axes, 1732 int *buttons 1733 ) 1734 { 1735 struct snd_azf3328 *chip = gameport_get_port_data(gameport); 1736 int i; 1737 u8 val; 1738 unsigned long flags; 1739 1740 if (snd_BUG_ON(!chip)) 1741 return 0; 1742 1743 spin_lock_irqsave(&chip->reg_lock, flags); 1744 val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE); 1745 *buttons = (~(val) >> 4) & 0xf; 1746 1747 /* ok, this one is a bit dirty: cooked_read is being polled by a timer, 1748 * thus we're atomic and cannot actively wait in here 1749 * (which would be useful for us since it probably would be better 1750 * to trigger a measurement in here, then wait a short amount of 1751 * time until it's finished, then read values of _this_ measurement). 1752 * 1753 * Thus we simply resort to reading values if they're available already 1754 * and trigger the next measurement. 1755 */ 1756 1757 val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG); 1758 if (val & GAME_AXES_SAMPLING_READY) { 1759 for (i = 0; i < ARRAY_SIZE(chip->axes); ++i) { 1760 /* configure the axis to read */ 1761 val = (i << 4) | 0x0f; 1762 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val); 1763 1764 chip->axes[i] = snd_azf3328_game_inw( 1765 chip, IDX_GAME_AXIS_VALUE 1766 ); 1767 } 1768 } 1769 1770 /* trigger next sampling of axes, to be evaluated the next time we 1771 * enter this function */ 1772 1773 /* for some very, very strange reason we cannot enable 1774 * Measurement Ready monitoring for all axes here, 1775 * at least not when only one joystick connected */ 1776 val = 0x03; /* we're able to monitor axes 1 and 2 only */ 1777 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val); 1778 1779 snd_azf3328_game_outw(chip, IDX_GAME_AXIS_VALUE, 0xffff); 1780 spin_unlock_irqrestore(&chip->reg_lock, flags); 1781 1782 for (i = 0; i < ARRAY_SIZE(chip->axes); i++) { 1783 axes[i] = chip->axes[i]; 1784 if (axes[i] == 0xffff) 1785 axes[i] = -1; 1786 } 1787 1788 dev_dbg(chip->card->dev, "cooked_read: axes %d %d %d %d buttons %d\n", 1789 axes[0], axes[1], axes[2], axes[3], *buttons); 1790 1791 return 0; 1792 } 1793 1794 static int 1795 snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) 1796 { 1797 struct gameport *gp; 1798 1799 chip->gameport = gp = gameport_allocate_port(); 1800 if (!gp) { 1801 dev_err(chip->card->dev, "cannot alloc memory for gameport\n"); 1802 return -ENOMEM; 1803 } 1804 1805 gameport_set_name(gp, "AZF3328 Gameport"); 1806 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 1807 gameport_set_dev_parent(gp, &chip->pci->dev); 1808 gp->io = chip->game_io; 1809 gameport_set_port_data(gp, chip); 1810 1811 gp->open = snd_azf3328_gameport_open; 1812 gp->close = snd_azf3328_gameport_close; 1813 gp->fuzz = 16; /* seems ok */ 1814 gp->cooked_read = snd_azf3328_gameport_cooked_read; 1815 1816 /* DISABLE legacy address: we don't need it! */ 1817 snd_azf3328_gameport_legacy_address_enable(chip, 0); 1818 1819 snd_azf3328_gameport_set_counter_frequency(chip, 1820 GAME_HWCFG_ADC_COUNTER_FREQ_1_200); 1821 snd_azf3328_gameport_axis_circuit_enable(chip, 0); 1822 1823 gameport_register_port(chip->gameport); 1824 1825 return 0; 1826 } 1827 1828 static void 1829 snd_azf3328_gameport_free(struct snd_azf3328 *chip) 1830 { 1831 if (chip->gameport) { 1832 gameport_unregister_port(chip->gameport); 1833 chip->gameport = NULL; 1834 } 1835 snd_azf3328_gameport_irq_enable(chip, 0); 1836 } 1837 #else 1838 static inline int 1839 snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { return -ENOSYS; } 1840 static inline void 1841 snd_azf3328_gameport_free(struct snd_azf3328 *chip) { } 1842 static inline void 1843 snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip) 1844 { 1845 dev_warn(chip->card->dev, "huh, game port IRQ occurred!?\n"); 1846 } 1847 #endif /* SUPPORT_GAMEPORT */ 1848 1849 /******************************************************************/ 1850 1851 static inline void 1852 snd_azf3328_irq_log_unknown_type(struct snd_azf3328 *chip, u8 which) 1853 { 1854 dev_dbg(chip->card->dev, 1855 "unknown IRQ type (%x) occurred, please report!\n", 1856 which); 1857 } 1858 1859 static inline void 1860 snd_azf3328_pcm_interrupt(struct snd_azf3328 *chip, 1861 const struct snd_azf3328_codec_data *first_codec, 1862 u8 status 1863 ) 1864 { 1865 u8 which; 1866 enum snd_azf3328_codec_type codec_type; 1867 const struct snd_azf3328_codec_data *codec = first_codec; 1868 1869 for (codec_type = AZF_CODEC_PLAYBACK; 1870 codec_type <= AZF_CODEC_I2S_OUT; 1871 ++codec_type, ++codec) { 1872 1873 /* skip codec if there's no interrupt for it */ 1874 if (!(status & (1 << codec_type))) 1875 continue; 1876 1877 spin_lock(codec->lock); 1878 which = snd_azf3328_codec_inb(codec, IDX_IO_CODEC_IRQTYPE); 1879 /* ack all IRQ types immediately */ 1880 snd_azf3328_codec_outb(codec, IDX_IO_CODEC_IRQTYPE, which); 1881 spin_unlock(codec->lock); 1882 1883 if (codec->substream) { 1884 snd_pcm_period_elapsed(codec->substream); 1885 dev_dbg(chip->card->dev, "%s period done (#%x), @ %x\n", 1886 codec->name, 1887 which, 1888 snd_azf3328_codec_inl( 1889 codec, IDX_IO_CODEC_DMA_CURRPOS)); 1890 } else 1891 dev_warn(chip->card->dev, "irq handler problem!\n"); 1892 if (which & IRQ_SOMETHING) 1893 snd_azf3328_irq_log_unknown_type(chip, which); 1894 } 1895 } 1896 1897 static irqreturn_t 1898 snd_azf3328_interrupt(int irq, void *dev_id) 1899 { 1900 struct snd_azf3328 *chip = dev_id; 1901 u8 status; 1902 static unsigned long irq_count; 1903 1904 status = snd_azf3328_ctrl_inb(chip, IDX_IO_IRQSTATUS); 1905 1906 /* fast path out, to ease interrupt sharing */ 1907 if (!(status & 1908 (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT 1909 |IRQ_GAMEPORT|IRQ_MPU401|IRQ_TIMER) 1910 )) 1911 return IRQ_NONE; /* must be interrupt for another device */ 1912 1913 dev_dbg(chip->card->dev, 1914 "irq_count %ld! IDX_IO_IRQSTATUS %04x\n", 1915 irq_count++ /* debug-only */, 1916 status); 1917 1918 if (status & IRQ_TIMER) { 1919 /* dev_dbg(chip->card->dev, "timer %ld\n", 1920 snd_azf3328_codec_inl(chip, IDX_IO_TIMER_VALUE) 1921 & TIMER_VALUE_MASK 1922 ); */ 1923 if (chip->timer) 1924 snd_timer_interrupt(chip->timer, chip->timer->sticks); 1925 /* ACK timer */ 1926 spin_lock(&chip->reg_lock); 1927 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07); 1928 spin_unlock(&chip->reg_lock); 1929 dev_dbg(chip->card->dev, "timer IRQ\n"); 1930 } 1931 1932 if (status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT)) 1933 snd_azf3328_pcm_interrupt(chip, chip->codecs, status); 1934 1935 if (status & IRQ_GAMEPORT) 1936 snd_azf3328_gameport_interrupt(chip); 1937 1938 /* MPU401 has less critical IRQ requirements 1939 * than timer and playback/recording, right? */ 1940 if (status & IRQ_MPU401) { 1941 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data); 1942 1943 /* hmm, do we have to ack the IRQ here somehow? 1944 * If so, then I don't know how yet... */ 1945 dev_dbg(chip->card->dev, "MPU401 IRQ\n"); 1946 } 1947 return IRQ_HANDLED; 1948 } 1949 1950 /*****************************************************************/ 1951 1952 /* as long as we think we have identical snd_pcm_hardware parameters 1953 for playback, capture and i2s out, we can use the same physical struct 1954 since the struct is simply being copied into a member. 1955 */ 1956 static const struct snd_pcm_hardware snd_azf3328_hardware = 1957 { 1958 /* FIXME!! Correct? */ 1959 .info = SNDRV_PCM_INFO_MMAP | 1960 SNDRV_PCM_INFO_INTERLEAVED | 1961 SNDRV_PCM_INFO_MMAP_VALID, 1962 .formats = SNDRV_PCM_FMTBIT_S8 | 1963 SNDRV_PCM_FMTBIT_U8 | 1964 SNDRV_PCM_FMTBIT_S16_LE | 1965 SNDRV_PCM_FMTBIT_U16_LE, 1966 .rates = SNDRV_PCM_RATE_5512 | 1967 SNDRV_PCM_RATE_8000_48000 | 1968 SNDRV_PCM_RATE_KNOT, 1969 .rate_min = AZF_FREQ_4000, 1970 .rate_max = AZF_FREQ_66200, 1971 .channels_min = 1, 1972 .channels_max = 2, 1973 .buffer_bytes_max = (64*1024), 1974 .period_bytes_min = 1024, 1975 .period_bytes_max = (32*1024), 1976 /* We simply have two DMA areas (instead of a list of descriptors 1977 such as other cards); I believe that this is a fixed hardware 1978 attribute and there isn't much driver magic to be done to expand it. 1979 Thus indicate that we have at least and at most 2 periods. */ 1980 .periods_min = 2, 1981 .periods_max = 2, 1982 /* FIXME: maybe that card actually has a FIFO? 1983 * Hmm, it seems newer revisions do have one, but we still don't know 1984 * its size... */ 1985 .fifo_size = 0, 1986 }; 1987 1988 1989 static const unsigned int snd_azf3328_fixed_rates[] = { 1990 AZF_FREQ_4000, 1991 AZF_FREQ_4800, 1992 AZF_FREQ_5512, 1993 AZF_FREQ_6620, 1994 AZF_FREQ_8000, 1995 AZF_FREQ_9600, 1996 AZF_FREQ_11025, 1997 AZF_FREQ_13240, 1998 AZF_FREQ_16000, 1999 AZF_FREQ_22050, 2000 AZF_FREQ_32000, 2001 AZF_FREQ_44100, 2002 AZF_FREQ_48000, 2003 AZF_FREQ_66200 2004 }; 2005 2006 static const struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = { 2007 .count = ARRAY_SIZE(snd_azf3328_fixed_rates), 2008 .list = snd_azf3328_fixed_rates, 2009 .mask = 0, 2010 }; 2011 2012 /*****************************************************************/ 2013 2014 static int 2015 snd_azf3328_pcm_open(struct snd_pcm_substream *substream, 2016 enum snd_azf3328_codec_type codec_type 2017 ) 2018 { 2019 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream); 2020 struct snd_pcm_runtime *runtime = substream->runtime; 2021 struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type]; 2022 2023 codec->substream = substream; 2024 2025 /* same parameters for all our codecs - at least we think so... */ 2026 runtime->hw = snd_azf3328_hardware; 2027 2028 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 2029 &snd_azf3328_hw_constraints_rates); 2030 runtime->private_data = codec; 2031 return 0; 2032 } 2033 2034 static int 2035 snd_azf3328_pcm_playback_open(struct snd_pcm_substream *substream) 2036 { 2037 return snd_azf3328_pcm_open(substream, AZF_CODEC_PLAYBACK); 2038 } 2039 2040 static int 2041 snd_azf3328_pcm_capture_open(struct snd_pcm_substream *substream) 2042 { 2043 return snd_azf3328_pcm_open(substream, AZF_CODEC_CAPTURE); 2044 } 2045 2046 static int 2047 snd_azf3328_pcm_i2s_out_open(struct snd_pcm_substream *substream) 2048 { 2049 return snd_azf3328_pcm_open(substream, AZF_CODEC_I2S_OUT); 2050 } 2051 2052 static int 2053 snd_azf3328_pcm_close(struct snd_pcm_substream *substream 2054 ) 2055 { 2056 struct snd_azf3328_codec_data *codec = 2057 substream->runtime->private_data; 2058 2059 codec->substream = NULL; 2060 return 0; 2061 } 2062 2063 /******************************************************************/ 2064 2065 static const struct snd_pcm_ops snd_azf3328_playback_ops = { 2066 .open = snd_azf3328_pcm_playback_open, 2067 .close = snd_azf3328_pcm_close, 2068 .prepare = snd_azf3328_pcm_prepare, 2069 .trigger = snd_azf3328_pcm_trigger, 2070 .pointer = snd_azf3328_pcm_pointer 2071 }; 2072 2073 static const struct snd_pcm_ops snd_azf3328_capture_ops = { 2074 .open = snd_azf3328_pcm_capture_open, 2075 .close = snd_azf3328_pcm_close, 2076 .prepare = snd_azf3328_pcm_prepare, 2077 .trigger = snd_azf3328_pcm_trigger, 2078 .pointer = snd_azf3328_pcm_pointer 2079 }; 2080 2081 static const struct snd_pcm_ops snd_azf3328_i2s_out_ops = { 2082 .open = snd_azf3328_pcm_i2s_out_open, 2083 .close = snd_azf3328_pcm_close, 2084 .prepare = snd_azf3328_pcm_prepare, 2085 .trigger = snd_azf3328_pcm_trigger, 2086 .pointer = snd_azf3328_pcm_pointer 2087 }; 2088 2089 static int 2090 snd_azf3328_pcm(struct snd_azf3328 *chip) 2091 { 2092 /* pcm devices */ 2093 enum { AZF_PCMDEV_STD, AZF_PCMDEV_I2S_OUT, NUM_AZF_PCMDEVS }; 2094 2095 struct snd_pcm *pcm; 2096 int err; 2097 2098 err = snd_pcm_new(chip->card, "AZF3328 DSP", AZF_PCMDEV_STD, 2099 1, 1, &pcm); 2100 if (err < 0) 2101 return err; 2102 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 2103 &snd_azf3328_playback_ops); 2104 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 2105 &snd_azf3328_capture_ops); 2106 2107 pcm->private_data = chip; 2108 pcm->info_flags = 0; 2109 strcpy(pcm->name, chip->card->shortname); 2110 /* same pcm object for playback/capture (see snd_pcm_new() above) */ 2111 chip->pcm[AZF_CODEC_PLAYBACK] = pcm; 2112 chip->pcm[AZF_CODEC_CAPTURE] = pcm; 2113 2114 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 2115 64*1024, 64*1024); 2116 2117 err = snd_pcm_new(chip->card, "AZF3328 I2S OUT", AZF_PCMDEV_I2S_OUT, 2118 1, 0, &pcm); 2119 if (err < 0) 2120 return err; 2121 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 2122 &snd_azf3328_i2s_out_ops); 2123 2124 pcm->private_data = chip; 2125 pcm->info_flags = 0; 2126 strcpy(pcm->name, chip->card->shortname); 2127 chip->pcm[AZF_CODEC_I2S_OUT] = pcm; 2128 2129 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev, 2130 64*1024, 64*1024); 2131 2132 return 0; 2133 } 2134 2135 /******************************************************************/ 2136 2137 /*** NOTE: the physical timer resolution actually is 1024000 ticks per second 2138 *** (probably derived from main crystal via a divider of 24), 2139 *** but announcing those attributes to user-space would make programs 2140 *** configure the timer to a 1 tick value, resulting in an absolutely fatal 2141 *** timer IRQ storm. 2142 *** Thus I chose to announce a down-scaled virtual timer to the outside and 2143 *** calculate real timer countdown values internally. 2144 *** (the scale factor can be set via module parameter "seqtimer_scaling"). 2145 ***/ 2146 2147 static int 2148 snd_azf3328_timer_start(struct snd_timer *timer) 2149 { 2150 struct snd_azf3328 *chip; 2151 unsigned long flags; 2152 unsigned int delay; 2153 2154 chip = snd_timer_chip(timer); 2155 delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK; 2156 if (delay < 49) { 2157 /* uhoh, that's not good, since user-space won't know about 2158 * this timing tweak 2159 * (we need to do it to avoid a lockup, though) */ 2160 2161 dev_dbg(chip->card->dev, "delay was too low (%d)!\n", delay); 2162 delay = 49; /* minimum time is 49 ticks */ 2163 } 2164 dev_dbg(chip->card->dev, "setting timer countdown value %d\n", delay); 2165 delay |= TIMER_COUNTDOWN_ENABLE | TIMER_IRQ_ENABLE; 2166 spin_lock_irqsave(&chip->reg_lock, flags); 2167 snd_azf3328_ctrl_outl(chip, IDX_IO_TIMER_VALUE, delay); 2168 spin_unlock_irqrestore(&chip->reg_lock, flags); 2169 return 0; 2170 } 2171 2172 static int 2173 snd_azf3328_timer_stop(struct snd_timer *timer) 2174 { 2175 struct snd_azf3328 *chip; 2176 unsigned long flags; 2177 2178 chip = snd_timer_chip(timer); 2179 spin_lock_irqsave(&chip->reg_lock, flags); 2180 /* disable timer countdown and interrupt */ 2181 /* Hmm, should we write TIMER_IRQ_ACK here? 2182 YES indeed, otherwise a rogue timer operation - which prompts 2183 ALSA(?) to call repeated stop() in vain, but NOT start() - 2184 will never end (value 0x03 is kept shown in control byte). 2185 Simply manually poking 0x04 _once_ immediately successfully stops 2186 the hardware/ALSA interrupt activity. */ 2187 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x04); 2188 spin_unlock_irqrestore(&chip->reg_lock, flags); 2189 return 0; 2190 } 2191 2192 2193 static int 2194 snd_azf3328_timer_precise_resolution(struct snd_timer *timer, 2195 unsigned long *num, unsigned long *den) 2196 { 2197 *num = 1; 2198 *den = 1024000 / seqtimer_scaling; 2199 return 0; 2200 } 2201 2202 static struct snd_timer_hardware snd_azf3328_timer_hw = { 2203 .flags = SNDRV_TIMER_HW_AUTO, 2204 .resolution = 977, /* 1000000/1024000 = 0.9765625us */ 2205 .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */ 2206 .start = snd_azf3328_timer_start, 2207 .stop = snd_azf3328_timer_stop, 2208 .precise_resolution = snd_azf3328_timer_precise_resolution, 2209 }; 2210 2211 static int 2212 snd_azf3328_timer(struct snd_azf3328 *chip, int device) 2213 { 2214 struct snd_timer *timer = NULL; 2215 struct snd_timer_id tid; 2216 int err; 2217 2218 tid.dev_class = SNDRV_TIMER_CLASS_CARD; 2219 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE; 2220 tid.card = chip->card->number; 2221 tid.device = device; 2222 tid.subdevice = 0; 2223 2224 snd_azf3328_timer_hw.resolution *= seqtimer_scaling; 2225 snd_azf3328_timer_hw.ticks /= seqtimer_scaling; 2226 2227 err = snd_timer_new(chip->card, "AZF3328", &tid, &timer); 2228 if (err < 0) 2229 goto out; 2230 2231 strcpy(timer->name, "AZF3328 timer"); 2232 timer->private_data = chip; 2233 timer->hw = snd_azf3328_timer_hw; 2234 2235 chip->timer = timer; 2236 2237 snd_azf3328_timer_stop(timer); 2238 2239 err = 0; 2240 2241 out: 2242 return err; 2243 } 2244 2245 /******************************************************************/ 2246 2247 static void 2248 snd_azf3328_free(struct snd_card *card) 2249 { 2250 struct snd_azf3328 *chip = card->private_data; 2251 2252 snd_azf3328_mixer_reset(chip); 2253 2254 snd_azf3328_timer_stop(chip->timer); 2255 snd_azf3328_gameport_free(chip); 2256 } 2257 2258 #if 0 2259 /* check whether a bit can be modified */ 2260 static void 2261 snd_azf3328_test_bit(unsigned unsigned reg, int bit) 2262 { 2263 unsigned char val, valoff, valon; 2264 2265 val = inb(reg); 2266 2267 outb(val & ~(1 << bit), reg); 2268 valoff = inb(reg); 2269 2270 outb(val|(1 << bit), reg); 2271 valon = inb(reg); 2272 2273 outb(val, reg); 2274 2275 printk(KERN_DEBUG "reg %04x bit %d: %02x %02x %02x\n", 2276 reg, bit, val, valoff, valon 2277 ); 2278 } 2279 #endif 2280 2281 static inline void 2282 snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip) 2283 { 2284 u16 tmp; 2285 2286 dev_dbg(chip->card->dev, 2287 "ctrl_io 0x%lx, game_io 0x%lx, mpu_io 0x%lx, " 2288 "opl3_io 0x%lx, mixer_io 0x%lx, irq %d\n", 2289 chip->ctrl_io, chip->game_io, chip->mpu_io, 2290 chip->opl3_io, chip->mixer_io, chip->irq); 2291 2292 dev_dbg(chip->card->dev, 2293 "game %02x %02x %02x %02x %02x %02x\n", 2294 snd_azf3328_game_inb(chip, 0), 2295 snd_azf3328_game_inb(chip, 1), 2296 snd_azf3328_game_inb(chip, 2), 2297 snd_azf3328_game_inb(chip, 3), 2298 snd_azf3328_game_inb(chip, 4), 2299 snd_azf3328_game_inb(chip, 5)); 2300 2301 for (tmp = 0; tmp < 0x07; tmp += 1) 2302 dev_dbg(chip->card->dev, 2303 "mpu_io 0x%04x\n", inb(chip->mpu_io + tmp)); 2304 2305 for (tmp = 0; tmp <= 0x07; tmp += 1) 2306 dev_dbg(chip->card->dev, 2307 "0x%02x: game200 0x%04x, game208 0x%04x\n", 2308 tmp, inb(0x200 + tmp), inb(0x208 + tmp)); 2309 2310 for (tmp = 0; tmp <= 0x01; tmp += 1) 2311 dev_dbg(chip->card->dev, 2312 "0x%02x: mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, " 2313 "mpu330 0x%04x opl388 0x%04x opl38c 0x%04x\n", 2314 tmp, 2315 inb(0x300 + tmp), 2316 inb(0x310 + tmp), 2317 inb(0x320 + tmp), 2318 inb(0x330 + tmp), 2319 inb(0x388 + tmp), 2320 inb(0x38c + tmp)); 2321 2322 for (tmp = 0; tmp < AZF_IO_SIZE_CTRL; tmp += 2) 2323 dev_dbg(chip->card->dev, 2324 "ctrl 0x%02x: 0x%04x\n", 2325 tmp, snd_azf3328_ctrl_inw(chip, tmp)); 2326 2327 for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2) 2328 dev_dbg(chip->card->dev, 2329 "mixer 0x%02x: 0x%04x\n", 2330 tmp, snd_azf3328_mixer_inw(chip, tmp)); 2331 } 2332 2333 static int 2334 snd_azf3328_create(struct snd_card *card, 2335 struct pci_dev *pci, 2336 unsigned long device_type) 2337 { 2338 struct snd_azf3328 *chip = card->private_data; 2339 int err; 2340 u8 dma_init; 2341 enum snd_azf3328_codec_type codec_type; 2342 struct snd_azf3328_codec_data *codec_setup; 2343 2344 err = pcim_enable_device(pci); 2345 if (err < 0) 2346 return err; 2347 2348 spin_lock_init(&chip->reg_lock); 2349 chip->card = card; 2350 chip->pci = pci; 2351 chip->irq = -1; 2352 2353 /* check if we can restrict PCI DMA transfers to 24 bits */ 2354 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(24))) { 2355 dev_err(card->dev, 2356 "architecture does not support 24bit PCI busmaster DMA\n" 2357 ); 2358 return -ENXIO; 2359 } 2360 2361 err = pci_request_regions(pci, "Aztech AZF3328"); 2362 if (err < 0) 2363 return err; 2364 2365 chip->ctrl_io = pci_resource_start(pci, 0); 2366 chip->game_io = pci_resource_start(pci, 1); 2367 chip->mpu_io = pci_resource_start(pci, 2); 2368 chip->opl3_io = pci_resource_start(pci, 3); 2369 chip->mixer_io = pci_resource_start(pci, 4); 2370 2371 codec_setup = &chip->codecs[AZF_CODEC_PLAYBACK]; 2372 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_PLAYBACK; 2373 codec_setup->lock = &chip->reg_lock; 2374 codec_setup->type = AZF_CODEC_PLAYBACK; 2375 codec_setup->name = "PLAYBACK"; 2376 2377 codec_setup = &chip->codecs[AZF_CODEC_CAPTURE]; 2378 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_CAPTURE; 2379 codec_setup->lock = &chip->reg_lock; 2380 codec_setup->type = AZF_CODEC_CAPTURE; 2381 codec_setup->name = "CAPTURE"; 2382 2383 codec_setup = &chip->codecs[AZF_CODEC_I2S_OUT]; 2384 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_I2S_OUT; 2385 codec_setup->lock = &chip->reg_lock; 2386 codec_setup->type = AZF_CODEC_I2S_OUT; 2387 codec_setup->name = "I2S_OUT"; 2388 2389 if (devm_request_irq(&pci->dev, pci->irq, snd_azf3328_interrupt, 2390 IRQF_SHARED, KBUILD_MODNAME, chip)) { 2391 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 2392 return -EBUSY; 2393 } 2394 chip->irq = pci->irq; 2395 card->sync_irq = chip->irq; 2396 card->private_free = snd_azf3328_free; 2397 pci_set_master(pci); 2398 2399 snd_azf3328_debug_show_ports(chip); 2400 2401 /* create mixer interface & switches */ 2402 err = snd_azf3328_mixer_new(chip); 2403 if (err < 0) 2404 return err; 2405 2406 /* standard codec init stuff */ 2407 /* default DMA init value */ 2408 dma_init = DMA_RUN_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE; 2409 2410 for (codec_type = AZF_CODEC_PLAYBACK; 2411 codec_type <= AZF_CODEC_I2S_OUT; ++codec_type) { 2412 struct snd_azf3328_codec_data *codec = 2413 &chip->codecs[codec_type]; 2414 2415 /* shutdown codecs to reduce power / noise */ 2416 /* have ...ctrl_codec_activity() act properly */ 2417 codec->running = true; 2418 snd_azf3328_ctrl_codec_activity(chip, codec_type, 0); 2419 2420 spin_lock_irq(codec->lock); 2421 snd_azf3328_codec_outb(codec, IDX_IO_CODEC_DMA_FLAGS, 2422 dma_init); 2423 spin_unlock_irq(codec->lock); 2424 } 2425 2426 return 0; 2427 } 2428 2429 static int 2430 __snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 2431 { 2432 static int dev; 2433 struct snd_card *card; 2434 struct snd_azf3328 *chip; 2435 struct snd_opl3 *opl3; 2436 int err; 2437 2438 if (dev >= SNDRV_CARDS) 2439 return -ENODEV; 2440 if (!enable[dev]) { 2441 dev++; 2442 return -ENOENT; 2443 } 2444 2445 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2446 sizeof(*chip), &card); 2447 if (err < 0) 2448 return err; 2449 chip = card->private_data; 2450 2451 strcpy(card->driver, "AZF3328"); 2452 strcpy(card->shortname, "Aztech AZF3328 (PCI168)"); 2453 2454 err = snd_azf3328_create(card, pci, pci_id->driver_data); 2455 if (err < 0) 2456 return err; 2457 2458 /* chose to use MPU401_HW_AZT2320 ID instead of MPU401_HW_MPU401, 2459 since our hardware ought to be similar, thus use same ID. */ 2460 err = snd_mpu401_uart_new( 2461 card, 0, 2462 MPU401_HW_AZT2320, chip->mpu_io, 2463 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK, 2464 -1, &chip->rmidi 2465 ); 2466 if (err < 0) { 2467 dev_err(card->dev, "no MPU-401 device at 0x%lx?\n", 2468 chip->mpu_io 2469 ); 2470 return err; 2471 } 2472 2473 err = snd_azf3328_timer(chip, 0); 2474 if (err < 0) 2475 return err; 2476 2477 err = snd_azf3328_pcm(chip); 2478 if (err < 0) 2479 return err; 2480 2481 if (snd_opl3_create(card, chip->opl3_io, chip->opl3_io+2, 2482 OPL3_HW_AUTO, 1, &opl3) < 0) { 2483 dev_err(card->dev, "no OPL3 device at 0x%lx-0x%lx?\n", 2484 chip->opl3_io, chip->opl3_io+2 2485 ); 2486 } else { 2487 /* need to use IDs 1, 2 since ID 0 is snd_azf3328_timer above */ 2488 err = snd_opl3_timer_new(opl3, 1, 2); 2489 if (err < 0) 2490 return err; 2491 err = snd_opl3_hwdep_new(opl3, 0, 1, NULL); 2492 if (err < 0) 2493 return err; 2494 opl3->private_data = chip; 2495 } 2496 2497 sprintf(card->longname, "%s at 0x%lx, irq %i", 2498 card->shortname, chip->ctrl_io, chip->irq); 2499 2500 err = snd_card_register(card); 2501 if (err < 0) 2502 return err; 2503 2504 #ifdef MODULE 2505 dev_info(card->dev, 2506 "Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n"); 2507 dev_info(card->dev, 2508 "Hardware was completely undocumented, unfortunately.\n"); 2509 dev_info(card->dev, 2510 "Feel free to contact andi AT lisas.de for bug reports etc.!\n"); 2511 dev_info(card->dev, 2512 "User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n", 2513 1024000 / seqtimer_scaling, seqtimer_scaling); 2514 #endif 2515 2516 snd_azf3328_gameport(chip, dev); 2517 2518 pci_set_drvdata(pci, card); 2519 dev++; 2520 return 0; 2521 } 2522 2523 static int 2524 snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 2525 { 2526 return snd_card_free_on_error(&pci->dev, __snd_azf3328_probe(pci, pci_id)); 2527 } 2528 2529 #ifdef CONFIG_PM_SLEEP 2530 static inline void 2531 snd_azf3328_suspend_regs(const struct snd_azf3328 *chip, 2532 unsigned long io_addr, unsigned count, u32 *saved_regs) 2533 { 2534 unsigned reg; 2535 2536 for (reg = 0; reg < count; ++reg) { 2537 *saved_regs = inl(io_addr); 2538 dev_dbg(chip->card->dev, "suspend: io 0x%04lx: 0x%08x\n", 2539 io_addr, *saved_regs); 2540 ++saved_regs; 2541 io_addr += sizeof(*saved_regs); 2542 } 2543 } 2544 2545 static inline void 2546 snd_azf3328_resume_regs(const struct snd_azf3328 *chip, 2547 const u32 *saved_regs, 2548 unsigned long io_addr, 2549 unsigned count 2550 ) 2551 { 2552 unsigned reg; 2553 2554 for (reg = 0; reg < count; ++reg) { 2555 outl(*saved_regs, io_addr); 2556 dev_dbg(chip->card->dev, 2557 "resume: io 0x%04lx: 0x%08x --> 0x%08x\n", 2558 io_addr, *saved_regs, inl(io_addr)); 2559 ++saved_regs; 2560 io_addr += sizeof(*saved_regs); 2561 } 2562 } 2563 2564 static inline void 2565 snd_azf3328_suspend_ac97(struct snd_azf3328 *chip) 2566 { 2567 #ifdef AZF_USE_AC97_LAYER 2568 snd_ac97_suspend(chip->ac97); 2569 #else 2570 snd_azf3328_suspend_regs(chip, chip->mixer_io, 2571 ARRAY_SIZE(chip->saved_regs_mixer), chip->saved_regs_mixer); 2572 2573 /* make sure to disable master volume etc. to prevent looping sound */ 2574 snd_azf3328_mixer_mute_control_master(chip, 1); 2575 snd_azf3328_mixer_mute_control_pcm(chip, 1); 2576 #endif /* AZF_USE_AC97_LAYER */ 2577 } 2578 2579 static inline void 2580 snd_azf3328_resume_ac97(const struct snd_azf3328 *chip) 2581 { 2582 #ifdef AZF_USE_AC97_LAYER 2583 snd_ac97_resume(chip->ac97); 2584 #else 2585 snd_azf3328_resume_regs(chip, chip->saved_regs_mixer, chip->mixer_io, 2586 ARRAY_SIZE(chip->saved_regs_mixer)); 2587 2588 /* unfortunately with 32bit transfers, IDX_MIXER_PLAY_MASTER (0x02) 2589 and IDX_MIXER_RESET (offset 0x00) get touched at the same time, 2590 resulting in a mixer reset condition persisting until _after_ 2591 master vol was restored. Thus master vol needs an extra restore. */ 2592 outw(((u16 *)chip->saved_regs_mixer)[1], chip->mixer_io + 2); 2593 #endif /* AZF_USE_AC97_LAYER */ 2594 } 2595 2596 static int 2597 snd_azf3328_suspend(struct device *dev) 2598 { 2599 struct snd_card *card = dev_get_drvdata(dev); 2600 struct snd_azf3328 *chip = card->private_data; 2601 u16 *saved_regs_ctrl_u16; 2602 2603 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2604 2605 snd_azf3328_suspend_ac97(chip); 2606 2607 snd_azf3328_suspend_regs(chip, chip->ctrl_io, 2608 ARRAY_SIZE(chip->saved_regs_ctrl), chip->saved_regs_ctrl); 2609 2610 /* manually store the one currently relevant write-only reg, too */ 2611 saved_regs_ctrl_u16 = (u16 *)chip->saved_regs_ctrl; 2612 saved_regs_ctrl_u16[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH; 2613 2614 snd_azf3328_suspend_regs(chip, chip->game_io, 2615 ARRAY_SIZE(chip->saved_regs_game), chip->saved_regs_game); 2616 snd_azf3328_suspend_regs(chip, chip->mpu_io, 2617 ARRAY_SIZE(chip->saved_regs_mpu), chip->saved_regs_mpu); 2618 snd_azf3328_suspend_regs(chip, chip->opl3_io, 2619 ARRAY_SIZE(chip->saved_regs_opl3), chip->saved_regs_opl3); 2620 return 0; 2621 } 2622 2623 static int 2624 snd_azf3328_resume(struct device *dev) 2625 { 2626 struct snd_card *card = dev_get_drvdata(dev); 2627 const struct snd_azf3328 *chip = card->private_data; 2628 2629 snd_azf3328_resume_regs(chip, chip->saved_regs_game, chip->game_io, 2630 ARRAY_SIZE(chip->saved_regs_game)); 2631 snd_azf3328_resume_regs(chip, chip->saved_regs_mpu, chip->mpu_io, 2632 ARRAY_SIZE(chip->saved_regs_mpu)); 2633 snd_azf3328_resume_regs(chip, chip->saved_regs_opl3, chip->opl3_io, 2634 ARRAY_SIZE(chip->saved_regs_opl3)); 2635 2636 snd_azf3328_resume_ac97(chip); 2637 2638 snd_azf3328_resume_regs(chip, chip->saved_regs_ctrl, chip->ctrl_io, 2639 ARRAY_SIZE(chip->saved_regs_ctrl)); 2640 2641 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2642 return 0; 2643 } 2644 2645 static SIMPLE_DEV_PM_OPS(snd_azf3328_pm, snd_azf3328_suspend, snd_azf3328_resume); 2646 #define SND_AZF3328_PM_OPS &snd_azf3328_pm 2647 #else 2648 #define SND_AZF3328_PM_OPS NULL 2649 #endif /* CONFIG_PM_SLEEP */ 2650 2651 static struct pci_driver azf3328_driver = { 2652 .name = KBUILD_MODNAME, 2653 .id_table = snd_azf3328_ids, 2654 .probe = snd_azf3328_probe, 2655 .driver = { 2656 .pm = SND_AZF3328_PM_OPS, 2657 }, 2658 }; 2659 2660 module_pci_driver(azf3328_driver); 2661