1 /* 2 * ALSA driver for ATI IXP 150/200/250/300 AC97 controllers 3 * 4 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 */ 21 22 #include <sound/driver.h> 23 #include <asm/io.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/init.h> 27 #include <linux/pci.h> 28 #include <linux/slab.h> 29 #include <linux/moduleparam.h> 30 #include <sound/core.h> 31 #include <sound/pcm.h> 32 #include <sound/pcm_params.h> 33 #include <sound/info.h> 34 #include <sound/ac97_codec.h> 35 #include <sound/initval.h> 36 37 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>"); 38 MODULE_DESCRIPTION("ATI IXP AC97 controller"); 39 MODULE_LICENSE("GPL"); 40 MODULE_SUPPORTED_DEVICE("{{ATI,IXP150/200/250/300/400}}"); 41 42 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 43 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 44 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 45 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 48000}; 46 static char *ac97_quirk[SNDRV_CARDS]; 47 static int spdif_aclink[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1}; 48 49 module_param_array(index, int, NULL, 0444); 50 MODULE_PARM_DESC(index, "Index value for ATI IXP controller."); 51 module_param_array(id, charp, NULL, 0444); 52 MODULE_PARM_DESC(id, "ID string for ATI IXP controller."); 53 module_param_array(enable, bool, NULL, 0444); 54 MODULE_PARM_DESC(enable, "Enable audio part of ATI IXP controller."); 55 module_param_array(ac97_clock, int, NULL, 0444); 56 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz)."); 57 module_param_array(ac97_quirk, charp, NULL, 0444); 58 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); 59 module_param_array(spdif_aclink, bool, NULL, 0444); 60 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link."); 61 62 63 /* 64 */ 65 66 #define ATI_REG_ISR 0x00 /* interrupt source */ 67 #define ATI_REG_ISR_IN_XRUN (1U<<0) 68 #define ATI_REG_ISR_IN_STATUS (1U<<1) 69 #define ATI_REG_ISR_OUT_XRUN (1U<<2) 70 #define ATI_REG_ISR_OUT_STATUS (1U<<3) 71 #define ATI_REG_ISR_SPDF_XRUN (1U<<4) 72 #define ATI_REG_ISR_SPDF_STATUS (1U<<5) 73 #define ATI_REG_ISR_PHYS_INTR (1U<<8) 74 #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9) 75 #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10) 76 #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11) 77 #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12) 78 #define ATI_REG_ISR_NEW_FRAME (1U<<13) 79 80 #define ATI_REG_IER 0x04 /* interrupt enable */ 81 #define ATI_REG_IER_IN_XRUN_EN (1U<<0) 82 #define ATI_REG_IER_IO_STATUS_EN (1U<<1) 83 #define ATI_REG_IER_OUT_XRUN_EN (1U<<2) 84 #define ATI_REG_IER_OUT_XRUN_COND (1U<<3) 85 #define ATI_REG_IER_SPDF_XRUN_EN (1U<<4) 86 #define ATI_REG_IER_SPDF_STATUS_EN (1U<<5) 87 #define ATI_REG_IER_PHYS_INTR_EN (1U<<8) 88 #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9) 89 #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10) 90 #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11) 91 #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12) 92 #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */ 93 #define ATI_REG_IER_SET_BUS_BUSY (1U<<14) /* (WO) audio is running */ 94 95 #define ATI_REG_CMD 0x08 /* command */ 96 #define ATI_REG_CMD_POWERDOWN (1U<<0) 97 #define ATI_REG_CMD_RECEIVE_EN (1U<<1) 98 #define ATI_REG_CMD_SEND_EN (1U<<2) 99 #define ATI_REG_CMD_STATUS_MEM (1U<<3) 100 #define ATI_REG_CMD_SPDF_OUT_EN (1U<<4) 101 #define ATI_REG_CMD_SPDF_STATUS_MEM (1U<<5) 102 #define ATI_REG_CMD_SPDF_THRESHOLD (3U<<6) 103 #define ATI_REG_CMD_SPDF_THRESHOLD_SHIFT 6 104 #define ATI_REG_CMD_IN_DMA_EN (1U<<8) 105 #define ATI_REG_CMD_OUT_DMA_EN (1U<<9) 106 #define ATI_REG_CMD_SPDF_DMA_EN (1U<<10) 107 #define ATI_REG_CMD_SPDF_OUT_STOPPED (1U<<11) 108 #define ATI_REG_CMD_SPDF_CONFIG_MASK (7U<<12) 109 #define ATI_REG_CMD_SPDF_CONFIG_34 (1U<<12) 110 #define ATI_REG_CMD_SPDF_CONFIG_78 (2U<<12) 111 #define ATI_REG_CMD_SPDF_CONFIG_69 (3U<<12) 112 #define ATI_REG_CMD_SPDF_CONFIG_01 (4U<<12) 113 #define ATI_REG_CMD_INTERLEAVE_SPDF (1U<<16) 114 #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20) 115 #define ATI_REG_CMD_INTERLEAVE_IN (1U<<21) 116 #define ATI_REG_CMD_INTERLEAVE_OUT (1U<<22) 117 #define ATI_REG_CMD_LOOPBACK_EN (1U<<23) 118 #define ATI_REG_CMD_PACKED_DIS (1U<<24) 119 #define ATI_REG_CMD_BURST_EN (1U<<25) 120 #define ATI_REG_CMD_PANIC_EN (1U<<26) 121 #define ATI_REG_CMD_MODEM_PRESENT (1U<<27) 122 #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28) 123 #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29) 124 #define ATI_REG_CMD_AC_SYNC (1U<<30) 125 #define ATI_REG_CMD_AC_RESET (1U<<31) 126 127 #define ATI_REG_PHYS_OUT_ADDR 0x0c 128 #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0) 129 #define ATI_REG_PHYS_OUT_RW (1U<<2) 130 #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8) 131 #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9 132 #define ATI_REG_PHYS_OUT_DATA_SHIFT 16 133 134 #define ATI_REG_PHYS_IN_ADDR 0x10 135 #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8) 136 #define ATI_REG_PHYS_IN_ADDR_SHIFT 9 137 #define ATI_REG_PHYS_IN_DATA_SHIFT 16 138 139 #define ATI_REG_SLOTREQ 0x14 140 141 #define ATI_REG_COUNTER 0x18 142 #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */ 143 #define ATI_REG_COUNTER_BITCLOCK (31U<<8) 144 145 #define ATI_REG_IN_FIFO_THRESHOLD 0x1c 146 147 #define ATI_REG_IN_DMA_LINKPTR 0x20 148 #define ATI_REG_IN_DMA_DT_START 0x24 /* RO */ 149 #define ATI_REG_IN_DMA_DT_NEXT 0x28 /* RO */ 150 #define ATI_REG_IN_DMA_DT_CUR 0x2c /* RO */ 151 #define ATI_REG_IN_DMA_DT_SIZE 0x30 152 153 #define ATI_REG_OUT_DMA_SLOT 0x34 154 #define ATI_REG_OUT_DMA_SLOT_BIT(x) (1U << ((x) - 3)) 155 #define ATI_REG_OUT_DMA_SLOT_MASK 0x1ff 156 #define ATI_REG_OUT_DMA_THRESHOLD_MASK 0xf800 157 #define ATI_REG_OUT_DMA_THRESHOLD_SHIFT 11 158 159 #define ATI_REG_OUT_DMA_LINKPTR 0x38 160 #define ATI_REG_OUT_DMA_DT_START 0x3c /* RO */ 161 #define ATI_REG_OUT_DMA_DT_NEXT 0x40 /* RO */ 162 #define ATI_REG_OUT_DMA_DT_CUR 0x44 /* RO */ 163 #define ATI_REG_OUT_DMA_DT_SIZE 0x48 164 165 #define ATI_REG_SPDF_CMD 0x4c 166 #define ATI_REG_SPDF_CMD_LFSR (1U<<4) 167 #define ATI_REG_SPDF_CMD_SINGLE_CH (1U<<5) 168 #define ATI_REG_SPDF_CMD_LFSR_ACC (0xff<<8) /* RO */ 169 170 #define ATI_REG_SPDF_DMA_LINKPTR 0x50 171 #define ATI_REG_SPDF_DMA_DT_START 0x54 /* RO */ 172 #define ATI_REG_SPDF_DMA_DT_NEXT 0x58 /* RO */ 173 #define ATI_REG_SPDF_DMA_DT_CUR 0x5c /* RO */ 174 #define ATI_REG_SPDF_DMA_DT_SIZE 0x60 175 176 #define ATI_REG_MODEM_MIRROR 0x7c 177 #define ATI_REG_AUDIO_MIRROR 0x80 178 179 #define ATI_REG_6CH_REORDER 0x84 /* reorder slots for 6ch */ 180 #define ATI_REG_6CH_REORDER_EN (1U<<0) /* 3,4,7,8,6,9 -> 3,4,6,9,7,8 */ 181 182 #define ATI_REG_FIFO_FLUSH 0x88 183 #define ATI_REG_FIFO_OUT_FLUSH (1U<<0) 184 #define ATI_REG_FIFO_IN_FLUSH (1U<<1) 185 186 /* LINKPTR */ 187 #define ATI_REG_LINKPTR_EN (1U<<0) 188 189 /* [INT|OUT|SPDIF]_DMA_DT_SIZE */ 190 #define ATI_REG_DMA_DT_SIZE (0xffffU<<0) 191 #define ATI_REG_DMA_FIFO_USED (0x1fU<<16) 192 #define ATI_REG_DMA_FIFO_FREE (0x1fU<<21) 193 #define ATI_REG_DMA_STATE (7U<<26) 194 195 196 #define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */ 197 198 199 /* 200 */ 201 202 typedef struct snd_atiixp atiixp_t; 203 typedef struct snd_atiixp_dma atiixp_dma_t; 204 typedef struct snd_atiixp_dma_ops atiixp_dma_ops_t; 205 206 207 /* 208 * DMA packate descriptor 209 */ 210 211 typedef struct atiixp_dma_desc { 212 u32 addr; /* DMA buffer address */ 213 u16 status; /* status bits */ 214 u16 size; /* size of the packet in dwords */ 215 u32 next; /* address of the next packet descriptor */ 216 } atiixp_dma_desc_t; 217 218 /* 219 * stream enum 220 */ 221 enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, ATI_DMA_SPDIF, NUM_ATI_DMAS }; /* DMAs */ 222 enum { ATI_PCM_OUT, ATI_PCM_IN, ATI_PCM_SPDIF, NUM_ATI_PCMS }; /* AC97 pcm slots */ 223 enum { ATI_PCMDEV_ANALOG, ATI_PCMDEV_DIGITAL, NUM_ATI_PCMDEVS }; /* pcm devices */ 224 225 #define NUM_ATI_CODECS 3 226 227 228 /* 229 * constants and callbacks for each DMA type 230 */ 231 struct snd_atiixp_dma_ops { 232 int type; /* ATI_DMA_XXX */ 233 unsigned int llp_offset; /* LINKPTR offset */ 234 unsigned int dt_cur; /* DT_CUR offset */ 235 void (*enable_dma)(atiixp_t *chip, int on); /* called from open callback */ 236 void (*enable_transfer)(atiixp_t *chip, int on); /* called from trigger (START/STOP) */ 237 void (*flush_dma)(atiixp_t *chip); /* called from trigger (STOP only) */ 238 }; 239 240 /* 241 * DMA stream 242 */ 243 struct snd_atiixp_dma { 244 const atiixp_dma_ops_t *ops; 245 struct snd_dma_buffer desc_buf; 246 snd_pcm_substream_t *substream; /* assigned PCM substream */ 247 unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */ 248 unsigned int period_bytes, periods; 249 int opened; 250 int running; 251 int suspended; 252 int pcm_open_flag; 253 int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */ 254 unsigned int saved_curptr; 255 }; 256 257 /* 258 * ATI IXP chip 259 */ 260 struct snd_atiixp { 261 snd_card_t *card; 262 struct pci_dev *pci; 263 264 unsigned long addr; 265 void __iomem *remap_addr; 266 int irq; 267 268 ac97_bus_t *ac97_bus; 269 ac97_t *ac97[NUM_ATI_CODECS]; 270 271 spinlock_t reg_lock; 272 273 atiixp_dma_t dmas[NUM_ATI_DMAS]; 274 struct ac97_pcm *pcms[NUM_ATI_PCMS]; 275 snd_pcm_t *pcmdevs[NUM_ATI_PCMDEVS]; 276 277 int max_channels; /* max. channels for PCM out */ 278 279 unsigned int codec_not_ready_bits; /* for codec detection */ 280 281 int spdif_over_aclink; /* passed from the module option */ 282 struct semaphore open_mutex; /* playback open mutex */ 283 }; 284 285 286 /* 287 */ 288 static struct pci_device_id snd_atiixp_ids[] = { 289 { 0x1002, 0x4341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB200 */ 290 { 0x1002, 0x4361, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB300 */ 291 { 0x1002, 0x4370, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB400 */ 292 { 0, } 293 }; 294 295 MODULE_DEVICE_TABLE(pci, snd_atiixp_ids); 296 297 298 /* 299 * lowlevel functions 300 */ 301 302 /* 303 * update the bits of the given register. 304 * return 1 if the bits changed. 305 */ 306 static int snd_atiixp_update_bits(atiixp_t *chip, unsigned int reg, 307 unsigned int mask, unsigned int value) 308 { 309 void __iomem *addr = chip->remap_addr + reg; 310 unsigned int data, old_data; 311 old_data = data = readl(addr); 312 data &= ~mask; 313 data |= value; 314 if (old_data == data) 315 return 0; 316 writel(data, addr); 317 return 1; 318 } 319 320 /* 321 * macros for easy use 322 */ 323 #define atiixp_write(chip,reg,value) \ 324 writel(value, chip->remap_addr + ATI_REG_##reg) 325 #define atiixp_read(chip,reg) \ 326 readl(chip->remap_addr + ATI_REG_##reg) 327 #define atiixp_update(chip,reg,mask,val) \ 328 snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val) 329 330 /* delay for one tick */ 331 #define do_delay() do { \ 332 set_current_state(TASK_UNINTERRUPTIBLE); \ 333 schedule_timeout(1); \ 334 } while (0) 335 336 337 /* 338 * handling DMA packets 339 * 340 * we allocate a linear buffer for the DMA, and split it to each packet. 341 * in a future version, a scatter-gather buffer should be implemented. 342 */ 343 344 #define ATI_DESC_LIST_SIZE \ 345 PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(atiixp_dma_desc_t)) 346 347 /* 348 * build packets ring for the given buffer size. 349 * 350 * IXP handles the buffer descriptors, which are connected as a linked 351 * list. although we can change the list dynamically, in this version, 352 * a static RING of buffer descriptors is used. 353 * 354 * the ring is built in this function, and is set up to the hardware. 355 */ 356 static int atiixp_build_dma_packets(atiixp_t *chip, atiixp_dma_t *dma, 357 snd_pcm_substream_t *substream, 358 unsigned int periods, 359 unsigned int period_bytes) 360 { 361 unsigned int i; 362 u32 addr, desc_addr; 363 unsigned long flags; 364 365 if (periods > ATI_MAX_DESCRIPTORS) 366 return -ENOMEM; 367 368 if (dma->desc_buf.area == NULL) { 369 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), 370 ATI_DESC_LIST_SIZE, &dma->desc_buf) < 0) 371 return -ENOMEM; 372 dma->period_bytes = dma->periods = 0; /* clear */ 373 } 374 375 if (dma->periods == periods && dma->period_bytes == period_bytes) 376 return 0; 377 378 /* reset DMA before changing the descriptor table */ 379 spin_lock_irqsave(&chip->reg_lock, flags); 380 writel(0, chip->remap_addr + dma->ops->llp_offset); 381 dma->ops->enable_dma(chip, 0); 382 dma->ops->enable_dma(chip, 1); 383 spin_unlock_irqrestore(&chip->reg_lock, flags); 384 385 /* fill the entries */ 386 addr = (u32)substream->runtime->dma_addr; 387 desc_addr = (u32)dma->desc_buf.addr; 388 for (i = 0; i < periods; i++) { 389 atiixp_dma_desc_t *desc = &((atiixp_dma_desc_t *)dma->desc_buf.area)[i]; 390 desc->addr = cpu_to_le32(addr); 391 desc->status = 0; 392 desc->size = period_bytes >> 2; /* in dwords */ 393 desc_addr += sizeof(atiixp_dma_desc_t); 394 if (i == periods - 1) 395 desc->next = cpu_to_le32((u32)dma->desc_buf.addr); 396 else 397 desc->next = cpu_to_le32(desc_addr); 398 addr += period_bytes; 399 } 400 401 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN, 402 chip->remap_addr + dma->ops->llp_offset); 403 404 dma->period_bytes = period_bytes; 405 dma->periods = periods; 406 407 return 0; 408 } 409 410 /* 411 * remove the ring buffer and release it if assigned 412 */ 413 static void atiixp_clear_dma_packets(atiixp_t *chip, atiixp_dma_t *dma, snd_pcm_substream_t *substream) 414 { 415 if (dma->desc_buf.area) { 416 writel(0, chip->remap_addr + dma->ops->llp_offset); 417 snd_dma_free_pages(&dma->desc_buf); 418 dma->desc_buf.area = NULL; 419 } 420 } 421 422 /* 423 * AC97 interface 424 */ 425 static int snd_atiixp_acquire_codec(atiixp_t *chip) 426 { 427 int timeout = 1000; 428 429 while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) { 430 if (! timeout--) { 431 snd_printk(KERN_WARNING "atiixp: codec acquire timeout\n"); 432 return -EBUSY; 433 } 434 udelay(1); 435 } 436 return 0; 437 } 438 439 static unsigned short snd_atiixp_codec_read(atiixp_t *chip, unsigned short codec, unsigned short reg) 440 { 441 unsigned int data; 442 int timeout; 443 444 if (snd_atiixp_acquire_codec(chip) < 0) 445 return 0xffff; 446 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 447 ATI_REG_PHYS_OUT_ADDR_EN | 448 ATI_REG_PHYS_OUT_RW | 449 codec; 450 atiixp_write(chip, PHYS_OUT_ADDR, data); 451 if (snd_atiixp_acquire_codec(chip) < 0) 452 return 0xffff; 453 timeout = 1000; 454 do { 455 data = atiixp_read(chip, PHYS_IN_ADDR); 456 if (data & ATI_REG_PHYS_IN_READ_FLAG) 457 return data >> ATI_REG_PHYS_IN_DATA_SHIFT; 458 udelay(1); 459 } while (--timeout); 460 /* time out may happen during reset */ 461 if (reg < 0x7c) 462 snd_printk(KERN_WARNING "atiixp: codec read timeout (reg %x)\n", reg); 463 return 0xffff; 464 } 465 466 467 static void snd_atiixp_codec_write(atiixp_t *chip, unsigned short codec, unsigned short reg, unsigned short val) 468 { 469 unsigned int data; 470 471 if (snd_atiixp_acquire_codec(chip) < 0) 472 return; 473 data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) | 474 ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | 475 ATI_REG_PHYS_OUT_ADDR_EN | codec; 476 atiixp_write(chip, PHYS_OUT_ADDR, data); 477 } 478 479 480 static unsigned short snd_atiixp_ac97_read(ac97_t *ac97, unsigned short reg) 481 { 482 atiixp_t *chip = ac97->private_data; 483 return snd_atiixp_codec_read(chip, ac97->num, reg); 484 485 } 486 487 static void snd_atiixp_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val) 488 { 489 atiixp_t *chip = ac97->private_data; 490 snd_atiixp_codec_write(chip, ac97->num, reg, val); 491 } 492 493 /* 494 * reset AC link 495 */ 496 static int snd_atiixp_aclink_reset(atiixp_t *chip) 497 { 498 int timeout; 499 500 /* reset powerdoewn */ 501 if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0)) 502 udelay(10); 503 504 /* perform a software reset */ 505 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET); 506 atiixp_read(chip, CMD); 507 udelay(10); 508 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0); 509 510 timeout = 10; 511 while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) { 512 /* do a hard reset */ 513 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET, 514 ATI_REG_CMD_AC_SYNC); 515 atiixp_read(chip, CMD); 516 do_delay(); 517 atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET); 518 if (--timeout) { 519 snd_printk(KERN_ERR "atiixp: codec reset timeout\n"); 520 break; 521 } 522 } 523 524 /* deassert RESET and assert SYNC to make sure */ 525 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET, 526 ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET); 527 528 return 0; 529 } 530 531 #ifdef CONFIG_PM 532 static int snd_atiixp_aclink_down(atiixp_t *chip) 533 { 534 // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */ 535 // return -EBUSY; 536 atiixp_update(chip, CMD, 537 ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET, 538 ATI_REG_CMD_POWERDOWN); 539 return 0; 540 } 541 #endif 542 543 /* 544 * auto-detection of codecs 545 * 546 * the IXP chip can generate interrupts for the non-existing codecs. 547 * NEW_FRAME interrupt is used to make sure that the interrupt is generated 548 * even if all three codecs are connected. 549 */ 550 551 #define ALL_CODEC_NOT_READY \ 552 (ATI_REG_ISR_CODEC0_NOT_READY |\ 553 ATI_REG_ISR_CODEC1_NOT_READY |\ 554 ATI_REG_ISR_CODEC2_NOT_READY) 555 #define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME) 556 557 static int snd_atiixp_codec_detect(atiixp_t *chip) 558 { 559 int timeout; 560 561 chip->codec_not_ready_bits = 0; 562 atiixp_write(chip, IER, CODEC_CHECK_BITS); 563 /* wait for the interrupts */ 564 timeout = HZ / 10; 565 while (timeout-- > 0) { 566 do_delay(); 567 if (chip->codec_not_ready_bits) 568 break; 569 } 570 atiixp_write(chip, IER, 0); /* disable irqs */ 571 572 if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) { 573 snd_printk(KERN_ERR "atiixp: no codec detected!\n"); 574 return -ENXIO; 575 } 576 return 0; 577 } 578 579 580 /* 581 * enable DMA and irqs 582 */ 583 static int snd_atiixp_chip_start(atiixp_t *chip) 584 { 585 unsigned int reg; 586 587 /* set up spdif, enable burst mode */ 588 reg = atiixp_read(chip, CMD); 589 reg |= 0x02 << ATI_REG_CMD_SPDF_THRESHOLD_SHIFT; 590 reg |= ATI_REG_CMD_BURST_EN; 591 atiixp_write(chip, CMD, reg); 592 593 reg = atiixp_read(chip, SPDF_CMD); 594 reg &= ~(ATI_REG_SPDF_CMD_LFSR|ATI_REG_SPDF_CMD_SINGLE_CH); 595 atiixp_write(chip, SPDF_CMD, reg); 596 597 /* clear all interrupt source */ 598 atiixp_write(chip, ISR, 0xffffffff); 599 /* enable irqs */ 600 atiixp_write(chip, IER, 601 ATI_REG_IER_IO_STATUS_EN | 602 ATI_REG_IER_IN_XRUN_EN | 603 ATI_REG_IER_OUT_XRUN_EN | 604 ATI_REG_IER_SPDF_XRUN_EN | 605 ATI_REG_IER_SPDF_STATUS_EN); 606 return 0; 607 } 608 609 610 /* 611 * disable DMA and IRQs 612 */ 613 static int snd_atiixp_chip_stop(atiixp_t *chip) 614 { 615 /* clear interrupt source */ 616 atiixp_write(chip, ISR, atiixp_read(chip, ISR)); 617 /* disable irqs */ 618 atiixp_write(chip, IER, 0); 619 return 0; 620 } 621 622 623 /* 624 * PCM section 625 */ 626 627 /* 628 * pointer callback simplly reads XXX_DMA_DT_CUR register as the current 629 * position. when SG-buffer is implemented, the offset must be calculated 630 * correctly... 631 */ 632 static snd_pcm_uframes_t snd_atiixp_pcm_pointer(snd_pcm_substream_t *substream) 633 { 634 atiixp_t *chip = snd_pcm_substream_chip(substream); 635 snd_pcm_runtime_t *runtime = substream->runtime; 636 atiixp_dma_t *dma = (atiixp_dma_t *)runtime->private_data; 637 unsigned int curptr; 638 int timeout = 1000; 639 640 while (timeout--) { 641 curptr = readl(chip->remap_addr + dma->ops->dt_cur); 642 if (curptr < dma->buf_addr) 643 continue; 644 curptr -= dma->buf_addr; 645 if (curptr >= dma->buf_bytes) 646 continue; 647 return bytes_to_frames(runtime, curptr); 648 } 649 snd_printd("atiixp: invalid DMA pointer read 0x%x (buf=%x)\n", 650 readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr); 651 return 0; 652 } 653 654 /* 655 * XRUN detected, and stop the PCM substream 656 */ 657 static void snd_atiixp_xrun_dma(atiixp_t *chip, atiixp_dma_t *dma) 658 { 659 if (! dma->substream || ! dma->running) 660 return; 661 snd_printdd("atiixp: XRUN detected (DMA %d)\n", dma->ops->type); 662 snd_pcm_stop(dma->substream, SNDRV_PCM_STATE_XRUN); 663 } 664 665 /* 666 * the period ack. update the substream. 667 */ 668 static void snd_atiixp_update_dma(atiixp_t *chip, atiixp_dma_t *dma) 669 { 670 if (! dma->substream || ! dma->running) 671 return; 672 snd_pcm_period_elapsed(dma->substream); 673 } 674 675 /* set BUS_BUSY interrupt bit if any DMA is running */ 676 /* call with spinlock held */ 677 static void snd_atiixp_check_bus_busy(atiixp_t *chip) 678 { 679 unsigned int bus_busy; 680 if (atiixp_read(chip, CMD) & (ATI_REG_CMD_SEND_EN | 681 ATI_REG_CMD_RECEIVE_EN | 682 ATI_REG_CMD_SPDF_OUT_EN)) 683 bus_busy = ATI_REG_IER_SET_BUS_BUSY; 684 else 685 bus_busy = 0; 686 atiixp_update(chip, IER, ATI_REG_IER_SET_BUS_BUSY, bus_busy); 687 } 688 689 /* common trigger callback 690 * calling the lowlevel callbacks in it 691 */ 692 static int snd_atiixp_pcm_trigger(snd_pcm_substream_t *substream, int cmd) 693 { 694 atiixp_t *chip = snd_pcm_substream_chip(substream); 695 atiixp_dma_t *dma = (atiixp_dma_t *)substream->runtime->private_data; 696 int err = 0; 697 698 snd_assert(dma->ops->enable_transfer && dma->ops->flush_dma, return -EINVAL); 699 700 spin_lock(&chip->reg_lock); 701 switch (cmd) { 702 case SNDRV_PCM_TRIGGER_START: 703 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 704 case SNDRV_PCM_TRIGGER_RESUME: 705 dma->ops->enable_transfer(chip, 1); 706 dma->running = 1; 707 dma->suspended = 0; 708 break; 709 case SNDRV_PCM_TRIGGER_STOP: 710 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 711 case SNDRV_PCM_TRIGGER_SUSPEND: 712 dma->ops->enable_transfer(chip, 0); 713 dma->running = 0; 714 dma->suspended = cmd == SNDRV_PCM_TRIGGER_SUSPEND; 715 break; 716 default: 717 err = -EINVAL; 718 break; 719 } 720 if (! err) { 721 snd_atiixp_check_bus_busy(chip); 722 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 723 dma->ops->flush_dma(chip); 724 snd_atiixp_check_bus_busy(chip); 725 } 726 } 727 spin_unlock(&chip->reg_lock); 728 return err; 729 } 730 731 732 /* 733 * lowlevel callbacks for each DMA type 734 * 735 * every callback is supposed to be called in chip->reg_lock spinlock 736 */ 737 738 /* flush FIFO of analog OUT DMA */ 739 static void atiixp_out_flush_dma(atiixp_t *chip) 740 { 741 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_OUT_FLUSH); 742 } 743 744 /* enable/disable analog OUT DMA */ 745 static void atiixp_out_enable_dma(atiixp_t *chip, int on) 746 { 747 unsigned int data; 748 data = atiixp_read(chip, CMD); 749 if (on) { 750 if (data & ATI_REG_CMD_OUT_DMA_EN) 751 return; 752 atiixp_out_flush_dma(chip); 753 data |= ATI_REG_CMD_OUT_DMA_EN; 754 } else 755 data &= ~ATI_REG_CMD_OUT_DMA_EN; 756 atiixp_write(chip, CMD, data); 757 } 758 759 /* start/stop transfer over OUT DMA */ 760 static void atiixp_out_enable_transfer(atiixp_t *chip, int on) 761 { 762 atiixp_update(chip, CMD, ATI_REG_CMD_SEND_EN, 763 on ? ATI_REG_CMD_SEND_EN : 0); 764 } 765 766 /* enable/disable analog IN DMA */ 767 static void atiixp_in_enable_dma(atiixp_t *chip, int on) 768 { 769 atiixp_update(chip, CMD, ATI_REG_CMD_IN_DMA_EN, 770 on ? ATI_REG_CMD_IN_DMA_EN : 0); 771 } 772 773 /* start/stop analog IN DMA */ 774 static void atiixp_in_enable_transfer(atiixp_t *chip, int on) 775 { 776 if (on) { 777 unsigned int data = atiixp_read(chip, CMD); 778 if (! (data & ATI_REG_CMD_RECEIVE_EN)) { 779 data |= ATI_REG_CMD_RECEIVE_EN; 780 #if 0 /* FIXME: this causes the endless loop */ 781 /* wait until slot 3/4 are finished */ 782 while ((atiixp_read(chip, COUNTER) & 783 ATI_REG_COUNTER_SLOT) != 5) 784 ; 785 #endif 786 atiixp_write(chip, CMD, data); 787 } 788 } else 789 atiixp_update(chip, CMD, ATI_REG_CMD_RECEIVE_EN, 0); 790 } 791 792 /* flush FIFO of analog IN DMA */ 793 static void atiixp_in_flush_dma(atiixp_t *chip) 794 { 795 atiixp_write(chip, FIFO_FLUSH, ATI_REG_FIFO_IN_FLUSH); 796 } 797 798 /* enable/disable SPDIF OUT DMA */ 799 static void atiixp_spdif_enable_dma(atiixp_t *chip, int on) 800 { 801 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_DMA_EN, 802 on ? ATI_REG_CMD_SPDF_DMA_EN : 0); 803 } 804 805 /* start/stop SPDIF OUT DMA */ 806 static void atiixp_spdif_enable_transfer(atiixp_t *chip, int on) 807 { 808 unsigned int data; 809 data = atiixp_read(chip, CMD); 810 if (on) 811 data |= ATI_REG_CMD_SPDF_OUT_EN; 812 else 813 data &= ~ATI_REG_CMD_SPDF_OUT_EN; 814 atiixp_write(chip, CMD, data); 815 } 816 817 /* flush FIFO of SPDIF OUT DMA */ 818 static void atiixp_spdif_flush_dma(atiixp_t *chip) 819 { 820 int timeout; 821 822 /* DMA off, transfer on */ 823 atiixp_spdif_enable_dma(chip, 0); 824 atiixp_spdif_enable_transfer(chip, 1); 825 826 timeout = 100; 827 do { 828 if (! (atiixp_read(chip, SPDF_DMA_DT_SIZE) & ATI_REG_DMA_FIFO_USED)) 829 break; 830 udelay(1); 831 } while (timeout-- > 0); 832 833 atiixp_spdif_enable_transfer(chip, 0); 834 } 835 836 /* set up slots and formats for SPDIF OUT */ 837 static int snd_atiixp_spdif_prepare(snd_pcm_substream_t *substream) 838 { 839 atiixp_t *chip = snd_pcm_substream_chip(substream); 840 841 spin_lock_irq(&chip->reg_lock); 842 if (chip->spdif_over_aclink) { 843 unsigned int data; 844 /* enable slots 10/11 */ 845 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 846 ATI_REG_CMD_SPDF_CONFIG_01); 847 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK; 848 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) | 849 ATI_REG_OUT_DMA_SLOT_BIT(11); 850 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; 851 atiixp_write(chip, OUT_DMA_SLOT, data); 852 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT, 853 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? 854 ATI_REG_CMD_INTERLEAVE_OUT : 0); 855 } else { 856 atiixp_update(chip, CMD, ATI_REG_CMD_SPDF_CONFIG_MASK, 0); 857 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_SPDF, 0); 858 } 859 spin_unlock_irq(&chip->reg_lock); 860 return 0; 861 } 862 863 /* set up slots and formats for analog OUT */ 864 static int snd_atiixp_playback_prepare(snd_pcm_substream_t *substream) 865 { 866 atiixp_t *chip = snd_pcm_substream_chip(substream); 867 unsigned int data; 868 869 spin_lock_irq(&chip->reg_lock); 870 data = atiixp_read(chip, OUT_DMA_SLOT) & ~ATI_REG_OUT_DMA_SLOT_MASK; 871 switch (substream->runtime->channels) { 872 case 8: 873 data |= ATI_REG_OUT_DMA_SLOT_BIT(10) | 874 ATI_REG_OUT_DMA_SLOT_BIT(11); 875 /* fallthru */ 876 case 6: 877 data |= ATI_REG_OUT_DMA_SLOT_BIT(7) | 878 ATI_REG_OUT_DMA_SLOT_BIT(8); 879 /* fallthru */ 880 case 4: 881 data |= ATI_REG_OUT_DMA_SLOT_BIT(6) | 882 ATI_REG_OUT_DMA_SLOT_BIT(9); 883 /* fallthru */ 884 default: 885 data |= ATI_REG_OUT_DMA_SLOT_BIT(3) | 886 ATI_REG_OUT_DMA_SLOT_BIT(4); 887 break; 888 } 889 890 /* set output threshold */ 891 data |= 0x04 << ATI_REG_OUT_DMA_THRESHOLD_SHIFT; 892 atiixp_write(chip, OUT_DMA_SLOT, data); 893 894 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_OUT, 895 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? 896 ATI_REG_CMD_INTERLEAVE_OUT : 0); 897 898 /* 899 * enable 6 channel re-ordering bit if needed 900 */ 901 atiixp_update(chip, 6CH_REORDER, ATI_REG_6CH_REORDER_EN, 902 substream->runtime->channels >= 6 ? ATI_REG_6CH_REORDER_EN: 0); 903 904 spin_unlock_irq(&chip->reg_lock); 905 return 0; 906 } 907 908 /* set up slots and formats for analog IN */ 909 static int snd_atiixp_capture_prepare(snd_pcm_substream_t *substream) 910 { 911 atiixp_t *chip = snd_pcm_substream_chip(substream); 912 913 spin_lock_irq(&chip->reg_lock); 914 atiixp_update(chip, CMD, ATI_REG_CMD_INTERLEAVE_IN, 915 substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE ? 916 ATI_REG_CMD_INTERLEAVE_IN : 0); 917 spin_unlock_irq(&chip->reg_lock); 918 return 0; 919 } 920 921 /* 922 * hw_params - allocate the buffer and set up buffer descriptors 923 */ 924 static int snd_atiixp_pcm_hw_params(snd_pcm_substream_t *substream, 925 snd_pcm_hw_params_t *hw_params) 926 { 927 atiixp_t *chip = snd_pcm_substream_chip(substream); 928 atiixp_dma_t *dma = (atiixp_dma_t *)substream->runtime->private_data; 929 int err; 930 931 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 932 if (err < 0) 933 return err; 934 dma->buf_addr = substream->runtime->dma_addr; 935 dma->buf_bytes = params_buffer_bytes(hw_params); 936 937 err = atiixp_build_dma_packets(chip, dma, substream, 938 params_periods(hw_params), 939 params_period_bytes(hw_params)); 940 if (err < 0) 941 return err; 942 943 if (dma->ac97_pcm_type >= 0) { 944 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type]; 945 /* PCM is bound to AC97 codec(s) 946 * set up the AC97 codecs 947 */ 948 if (dma->pcm_open_flag) { 949 snd_ac97_pcm_close(pcm); 950 dma->pcm_open_flag = 0; 951 } 952 err = snd_ac97_pcm_open(pcm, params_rate(hw_params), 953 params_channels(hw_params), 954 pcm->r[0].slots); 955 if (err >= 0) 956 dma->pcm_open_flag = 1; 957 } 958 959 return err; 960 } 961 962 static int snd_atiixp_pcm_hw_free(snd_pcm_substream_t * substream) 963 { 964 atiixp_t *chip = snd_pcm_substream_chip(substream); 965 atiixp_dma_t *dma = (atiixp_dma_t *)substream->runtime->private_data; 966 967 if (dma->pcm_open_flag) { 968 struct ac97_pcm *pcm = chip->pcms[dma->ac97_pcm_type]; 969 snd_ac97_pcm_close(pcm); 970 dma->pcm_open_flag = 0; 971 } 972 atiixp_clear_dma_packets(chip, dma, substream); 973 snd_pcm_lib_free_pages(substream); 974 return 0; 975 } 976 977 978 /* 979 * pcm hardware definition, identical for all DMA types 980 */ 981 static snd_pcm_hardware_t snd_atiixp_pcm_hw = 982 { 983 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 984 SNDRV_PCM_INFO_BLOCK_TRANSFER | 985 SNDRV_PCM_INFO_PAUSE | 986 SNDRV_PCM_INFO_RESUME | 987 SNDRV_PCM_INFO_MMAP_VALID), 988 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 989 .rates = SNDRV_PCM_RATE_48000, 990 .rate_min = 48000, 991 .rate_max = 48000, 992 .channels_min = 2, 993 .channels_max = 2, 994 .buffer_bytes_max = 256 * 1024, 995 .period_bytes_min = 32, 996 .period_bytes_max = 128 * 1024, 997 .periods_min = 2, 998 .periods_max = ATI_MAX_DESCRIPTORS, 999 }; 1000 1001 static int snd_atiixp_pcm_open(snd_pcm_substream_t *substream, atiixp_dma_t *dma, int pcm_type) 1002 { 1003 atiixp_t *chip = snd_pcm_substream_chip(substream); 1004 snd_pcm_runtime_t *runtime = substream->runtime; 1005 int err; 1006 1007 snd_assert(dma->ops && dma->ops->enable_dma, return -EINVAL); 1008 1009 if (dma->opened) 1010 return -EBUSY; 1011 dma->substream = substream; 1012 runtime->hw = snd_atiixp_pcm_hw; 1013 dma->ac97_pcm_type = pcm_type; 1014 if (pcm_type >= 0) { 1015 runtime->hw.rates = chip->pcms[pcm_type]->rates; 1016 snd_pcm_limit_hw_rates(runtime); 1017 } else { 1018 /* direct SPDIF */ 1019 runtime->hw.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE; 1020 } 1021 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) 1022 return err; 1023 runtime->private_data = dma; 1024 1025 /* enable DMA bits */ 1026 spin_lock_irq(&chip->reg_lock); 1027 dma->ops->enable_dma(chip, 1); 1028 spin_unlock_irq(&chip->reg_lock); 1029 dma->opened = 1; 1030 1031 return 0; 1032 } 1033 1034 static int snd_atiixp_pcm_close(snd_pcm_substream_t *substream, atiixp_dma_t *dma) 1035 { 1036 atiixp_t *chip = snd_pcm_substream_chip(substream); 1037 /* disable DMA bits */ 1038 snd_assert(dma->ops && dma->ops->enable_dma, return -EINVAL); 1039 spin_lock_irq(&chip->reg_lock); 1040 dma->ops->enable_dma(chip, 0); 1041 spin_unlock_irq(&chip->reg_lock); 1042 dma->substream = NULL; 1043 dma->opened = 0; 1044 return 0; 1045 } 1046 1047 /* 1048 */ 1049 static int snd_atiixp_playback_open(snd_pcm_substream_t *substream) 1050 { 1051 atiixp_t *chip = snd_pcm_substream_chip(substream); 1052 int err; 1053 1054 down(&chip->open_mutex); 1055 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0); 1056 up(&chip->open_mutex); 1057 if (err < 0) 1058 return err; 1059 substream->runtime->hw.channels_max = chip->max_channels; 1060 if (chip->max_channels > 2) 1061 /* channels must be even */ 1062 snd_pcm_hw_constraint_step(substream->runtime, 0, 1063 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1064 return 0; 1065 } 1066 1067 static int snd_atiixp_playback_close(snd_pcm_substream_t *substream) 1068 { 1069 atiixp_t *chip = snd_pcm_substream_chip(substream); 1070 int err; 1071 down(&chip->open_mutex); 1072 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]); 1073 up(&chip->open_mutex); 1074 return err; 1075 } 1076 1077 static int snd_atiixp_capture_open(snd_pcm_substream_t *substream) 1078 { 1079 atiixp_t *chip = snd_pcm_substream_chip(substream); 1080 return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1); 1081 } 1082 1083 static int snd_atiixp_capture_close(snd_pcm_substream_t *substream) 1084 { 1085 atiixp_t *chip = snd_pcm_substream_chip(substream); 1086 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]); 1087 } 1088 1089 static int snd_atiixp_spdif_open(snd_pcm_substream_t *substream) 1090 { 1091 atiixp_t *chip = snd_pcm_substream_chip(substream); 1092 int err; 1093 down(&chip->open_mutex); 1094 if (chip->spdif_over_aclink) /* share DMA_PLAYBACK */ 1095 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 2); 1096 else 1097 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_SPDIF], -1); 1098 up(&chip->open_mutex); 1099 return err; 1100 } 1101 1102 static int snd_atiixp_spdif_close(snd_pcm_substream_t *substream) 1103 { 1104 atiixp_t *chip = snd_pcm_substream_chip(substream); 1105 int err; 1106 down(&chip->open_mutex); 1107 if (chip->spdif_over_aclink) 1108 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]); 1109 else 1110 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_SPDIF]); 1111 up(&chip->open_mutex); 1112 return err; 1113 } 1114 1115 /* AC97 playback */ 1116 static snd_pcm_ops_t snd_atiixp_playback_ops = { 1117 .open = snd_atiixp_playback_open, 1118 .close = snd_atiixp_playback_close, 1119 .ioctl = snd_pcm_lib_ioctl, 1120 .hw_params = snd_atiixp_pcm_hw_params, 1121 .hw_free = snd_atiixp_pcm_hw_free, 1122 .prepare = snd_atiixp_playback_prepare, 1123 .trigger = snd_atiixp_pcm_trigger, 1124 .pointer = snd_atiixp_pcm_pointer, 1125 }; 1126 1127 /* AC97 capture */ 1128 static snd_pcm_ops_t snd_atiixp_capture_ops = { 1129 .open = snd_atiixp_capture_open, 1130 .close = snd_atiixp_capture_close, 1131 .ioctl = snd_pcm_lib_ioctl, 1132 .hw_params = snd_atiixp_pcm_hw_params, 1133 .hw_free = snd_atiixp_pcm_hw_free, 1134 .prepare = snd_atiixp_capture_prepare, 1135 .trigger = snd_atiixp_pcm_trigger, 1136 .pointer = snd_atiixp_pcm_pointer, 1137 }; 1138 1139 /* SPDIF playback */ 1140 static snd_pcm_ops_t snd_atiixp_spdif_ops = { 1141 .open = snd_atiixp_spdif_open, 1142 .close = snd_atiixp_spdif_close, 1143 .ioctl = snd_pcm_lib_ioctl, 1144 .hw_params = snd_atiixp_pcm_hw_params, 1145 .hw_free = snd_atiixp_pcm_hw_free, 1146 .prepare = snd_atiixp_spdif_prepare, 1147 .trigger = snd_atiixp_pcm_trigger, 1148 .pointer = snd_atiixp_pcm_pointer, 1149 }; 1150 1151 static struct ac97_pcm atiixp_pcm_defs[] __devinitdata = { 1152 /* front PCM */ 1153 { 1154 .exclusive = 1, 1155 .r = { { 1156 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1157 (1 << AC97_SLOT_PCM_RIGHT) | 1158 (1 << AC97_SLOT_PCM_CENTER) | 1159 (1 << AC97_SLOT_PCM_SLEFT) | 1160 (1 << AC97_SLOT_PCM_SRIGHT) | 1161 (1 << AC97_SLOT_LFE) 1162 } 1163 } 1164 }, 1165 /* PCM IN #1 */ 1166 { 1167 .stream = 1, 1168 .exclusive = 1, 1169 .r = { { 1170 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1171 (1 << AC97_SLOT_PCM_RIGHT) 1172 } 1173 } 1174 }, 1175 /* S/PDIF OUT (optional) */ 1176 { 1177 .exclusive = 1, 1178 .spdif = 1, 1179 .r = { { 1180 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | 1181 (1 << AC97_SLOT_SPDIF_RIGHT2) 1182 } 1183 } 1184 }, 1185 }; 1186 1187 static atiixp_dma_ops_t snd_atiixp_playback_dma_ops = { 1188 .type = ATI_DMA_PLAYBACK, 1189 .llp_offset = ATI_REG_OUT_DMA_LINKPTR, 1190 .dt_cur = ATI_REG_OUT_DMA_DT_CUR, 1191 .enable_dma = atiixp_out_enable_dma, 1192 .enable_transfer = atiixp_out_enable_transfer, 1193 .flush_dma = atiixp_out_flush_dma, 1194 }; 1195 1196 static atiixp_dma_ops_t snd_atiixp_capture_dma_ops = { 1197 .type = ATI_DMA_CAPTURE, 1198 .llp_offset = ATI_REG_IN_DMA_LINKPTR, 1199 .dt_cur = ATI_REG_IN_DMA_DT_CUR, 1200 .enable_dma = atiixp_in_enable_dma, 1201 .enable_transfer = atiixp_in_enable_transfer, 1202 .flush_dma = atiixp_in_flush_dma, 1203 }; 1204 1205 static atiixp_dma_ops_t snd_atiixp_spdif_dma_ops = { 1206 .type = ATI_DMA_SPDIF, 1207 .llp_offset = ATI_REG_SPDF_DMA_LINKPTR, 1208 .dt_cur = ATI_REG_SPDF_DMA_DT_CUR, 1209 .enable_dma = atiixp_spdif_enable_dma, 1210 .enable_transfer = atiixp_spdif_enable_transfer, 1211 .flush_dma = atiixp_spdif_flush_dma, 1212 }; 1213 1214 1215 static int __devinit snd_atiixp_pcm_new(atiixp_t *chip) 1216 { 1217 snd_pcm_t *pcm; 1218 ac97_bus_t *pbus = chip->ac97_bus; 1219 int err, i, num_pcms; 1220 1221 /* initialize constants */ 1222 chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops; 1223 chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops; 1224 if (! chip->spdif_over_aclink) 1225 chip->dmas[ATI_DMA_SPDIF].ops = &snd_atiixp_spdif_dma_ops; 1226 1227 /* assign AC97 pcm */ 1228 if (chip->spdif_over_aclink) 1229 num_pcms = 3; 1230 else 1231 num_pcms = 2; 1232 err = snd_ac97_pcm_assign(pbus, num_pcms, atiixp_pcm_defs); 1233 if (err < 0) 1234 return err; 1235 for (i = 0; i < num_pcms; i++) 1236 chip->pcms[i] = &pbus->pcms[i]; 1237 1238 chip->max_channels = 2; 1239 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { 1240 if (pbus->pcms[ATI_PCM_OUT].r[0].slots & (1 << AC97_SLOT_LFE)) 1241 chip->max_channels = 6; 1242 else 1243 chip->max_channels = 4; 1244 } 1245 1246 /* PCM #0: analog I/O */ 1247 err = snd_pcm_new(chip->card, "ATI IXP AC97", ATI_PCMDEV_ANALOG, 1, 1, &pcm); 1248 if (err < 0) 1249 return err; 1250 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops); 1251 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops); 1252 pcm->private_data = chip; 1253 strcpy(pcm->name, "ATI IXP AC97"); 1254 chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm; 1255 1256 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1257 snd_dma_pci_data(chip->pci), 64*1024, 128*1024); 1258 1259 /* no SPDIF support on codec? */ 1260 if (chip->pcms[ATI_PCM_SPDIF] && ! chip->pcms[ATI_PCM_SPDIF]->rates) 1261 return 0; 1262 1263 /* FIXME: non-48k sample rate doesn't work on my test machine with AD1888 */ 1264 if (chip->pcms[ATI_PCM_SPDIF]) 1265 chip->pcms[ATI_PCM_SPDIF]->rates = SNDRV_PCM_RATE_48000; 1266 1267 /* PCM #1: spdif playback */ 1268 err = snd_pcm_new(chip->card, "ATI IXP IEC958", ATI_PCMDEV_DIGITAL, 1, 0, &pcm); 1269 if (err < 0) 1270 return err; 1271 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_spdif_ops); 1272 pcm->private_data = chip; 1273 if (chip->spdif_over_aclink) 1274 strcpy(pcm->name, "ATI IXP IEC958 (AC97)"); 1275 else 1276 strcpy(pcm->name, "ATI IXP IEC958 (Direct)"); 1277 chip->pcmdevs[ATI_PCMDEV_DIGITAL] = pcm; 1278 1279 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1280 snd_dma_pci_data(chip->pci), 64*1024, 128*1024); 1281 1282 /* pre-select AC97 SPDIF slots 10/11 */ 1283 for (i = 0; i < NUM_ATI_CODECS; i++) { 1284 if (chip->ac97[i]) 1285 snd_ac97_update_bits(chip->ac97[i], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4); 1286 } 1287 1288 return 0; 1289 } 1290 1291 1292 1293 /* 1294 * interrupt handler 1295 */ 1296 static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id, struct pt_regs *regs) 1297 { 1298 atiixp_t *chip = dev_id; 1299 unsigned int status; 1300 1301 status = atiixp_read(chip, ISR); 1302 1303 if (! status) 1304 return IRQ_NONE; 1305 1306 /* process audio DMA */ 1307 if (status & ATI_REG_ISR_OUT_XRUN) 1308 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]); 1309 else if (status & ATI_REG_ISR_OUT_STATUS) 1310 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]); 1311 if (status & ATI_REG_ISR_IN_XRUN) 1312 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]); 1313 else if (status & ATI_REG_ISR_IN_STATUS) 1314 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]); 1315 if (! chip->spdif_over_aclink) { 1316 if (status & ATI_REG_ISR_SPDF_XRUN) 1317 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_SPDIF]); 1318 else if (status & ATI_REG_ISR_SPDF_STATUS) 1319 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_SPDIF]); 1320 } 1321 1322 /* for codec detection */ 1323 if (status & CODEC_CHECK_BITS) { 1324 unsigned int detected; 1325 detected = status & CODEC_CHECK_BITS; 1326 spin_lock(&chip->reg_lock); 1327 chip->codec_not_ready_bits |= detected; 1328 atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */ 1329 spin_unlock(&chip->reg_lock); 1330 } 1331 1332 /* ack */ 1333 atiixp_write(chip, ISR, status); 1334 1335 return IRQ_HANDLED; 1336 } 1337 1338 1339 /* 1340 * ac97 mixer section 1341 */ 1342 1343 static struct ac97_quirk ac97_quirks[] __devinitdata = { 1344 { 1345 .subvendor = 0x103c, 1346 .subdevice = 0x006b, 1347 .name = "HP Pavilion ZV5030US", 1348 .type = AC97_TUNE_MUTE_LED 1349 }, 1350 { } /* terminator */ 1351 }; 1352 1353 static int __devinit snd_atiixp_mixer_new(atiixp_t *chip, int clock, const char *quirk_override) 1354 { 1355 ac97_bus_t *pbus; 1356 ac97_template_t ac97; 1357 int i, err; 1358 int codec_count; 1359 static ac97_bus_ops_t ops = { 1360 .write = snd_atiixp_ac97_write, 1361 .read = snd_atiixp_ac97_read, 1362 }; 1363 static unsigned int codec_skip[NUM_ATI_CODECS] = { 1364 ATI_REG_ISR_CODEC0_NOT_READY, 1365 ATI_REG_ISR_CODEC1_NOT_READY, 1366 ATI_REG_ISR_CODEC2_NOT_READY, 1367 }; 1368 1369 if (snd_atiixp_codec_detect(chip) < 0) 1370 return -ENXIO; 1371 1372 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0) 1373 return err; 1374 pbus->clock = clock; 1375 pbus->shared_type = AC97_SHARED_TYPE_ATIIXP; /* shared with modem driver */ 1376 chip->ac97_bus = pbus; 1377 1378 codec_count = 0; 1379 for (i = 0; i < NUM_ATI_CODECS; i++) { 1380 if (chip->codec_not_ready_bits & codec_skip[i]) 1381 continue; 1382 memset(&ac97, 0, sizeof(ac97)); 1383 ac97.private_data = chip; 1384 ac97.pci = chip->pci; 1385 ac97.num = i; 1386 ac97.scaps = AC97_SCAP_SKIP_MODEM; 1387 if (! chip->spdif_over_aclink) 1388 ac97.scaps |= AC97_SCAP_NO_SPDIF; 1389 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) { 1390 chip->ac97[i] = NULL; /* to be sure */ 1391 snd_printdd("atiixp: codec %d not available for audio\n", i); 1392 continue; 1393 } 1394 codec_count++; 1395 } 1396 1397 if (! codec_count) { 1398 snd_printk(KERN_ERR "atiixp: no codec available\n"); 1399 return -ENODEV; 1400 } 1401 1402 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); 1403 1404 return 0; 1405 } 1406 1407 1408 #ifdef CONFIG_PM 1409 /* 1410 * power management 1411 */ 1412 static int snd_atiixp_suspend(snd_card_t *card, pm_message_t state) 1413 { 1414 atiixp_t *chip = card->pm_private_data; 1415 int i; 1416 1417 for (i = 0; i < NUM_ATI_PCMDEVS; i++) 1418 if (chip->pcmdevs[i]) { 1419 atiixp_dma_t *dma = &chip->dmas[i]; 1420 if (dma->substream && dma->running) 1421 dma->saved_curptr = readl(chip->remap_addr + dma->ops->dt_cur); 1422 snd_pcm_suspend_all(chip->pcmdevs[i]); 1423 } 1424 for (i = 0; i < NUM_ATI_CODECS; i++) 1425 if (chip->ac97[i]) 1426 snd_ac97_suspend(chip->ac97[i]); 1427 snd_atiixp_aclink_down(chip); 1428 snd_atiixp_chip_stop(chip); 1429 1430 pci_set_power_state(chip->pci, PCI_D3hot); 1431 pci_disable_device(chip->pci); 1432 return 0; 1433 } 1434 1435 static int snd_atiixp_resume(snd_card_t *card) 1436 { 1437 atiixp_t *chip = card->pm_private_data; 1438 int i; 1439 1440 pci_enable_device(chip->pci); 1441 pci_set_power_state(chip->pci, PCI_D0); 1442 pci_set_master(chip->pci); 1443 1444 snd_atiixp_aclink_reset(chip); 1445 snd_atiixp_chip_start(chip); 1446 1447 for (i = 0; i < NUM_ATI_CODECS; i++) 1448 if (chip->ac97[i]) 1449 snd_ac97_resume(chip->ac97[i]); 1450 1451 for (i = 0; i < NUM_ATI_PCMDEVS; i++) 1452 if (chip->pcmdevs[i]) { 1453 atiixp_dma_t *dma = &chip->dmas[i]; 1454 if (dma->substream && dma->suspended) { 1455 dma->ops->enable_dma(chip, 1); 1456 dma->substream->ops->prepare(dma->substream); 1457 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN, 1458 chip->remap_addr + dma->ops->llp_offset); 1459 writel(dma->saved_curptr, chip->remap_addr + dma->ops->dt_cur); 1460 } 1461 } 1462 1463 return 0; 1464 } 1465 #endif /* CONFIG_PM */ 1466 1467 1468 /* 1469 * proc interface for register dump 1470 */ 1471 1472 static void snd_atiixp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer) 1473 { 1474 atiixp_t *chip = entry->private_data; 1475 int i; 1476 1477 for (i = 0; i < 256; i += 4) 1478 snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i)); 1479 } 1480 1481 static void __devinit snd_atiixp_proc_init(atiixp_t *chip) 1482 { 1483 snd_info_entry_t *entry; 1484 1485 if (! snd_card_proc_new(chip->card, "atiixp", &entry)) 1486 snd_info_set_text_ops(entry, chip, 1024, snd_atiixp_proc_read); 1487 } 1488 1489 1490 1491 /* 1492 * destructor 1493 */ 1494 1495 static int snd_atiixp_free(atiixp_t *chip) 1496 { 1497 if (chip->irq < 0) 1498 goto __hw_end; 1499 snd_atiixp_chip_stop(chip); 1500 synchronize_irq(chip->irq); 1501 __hw_end: 1502 if (chip->irq >= 0) 1503 free_irq(chip->irq, (void *)chip); 1504 if (chip->remap_addr) 1505 iounmap(chip->remap_addr); 1506 pci_release_regions(chip->pci); 1507 pci_disable_device(chip->pci); 1508 kfree(chip); 1509 return 0; 1510 } 1511 1512 static int snd_atiixp_dev_free(snd_device_t *device) 1513 { 1514 atiixp_t *chip = device->device_data; 1515 return snd_atiixp_free(chip); 1516 } 1517 1518 /* 1519 * constructor for chip instance 1520 */ 1521 static int __devinit snd_atiixp_create(snd_card_t *card, 1522 struct pci_dev *pci, 1523 atiixp_t **r_chip) 1524 { 1525 static snd_device_ops_t ops = { 1526 .dev_free = snd_atiixp_dev_free, 1527 }; 1528 atiixp_t *chip; 1529 int err; 1530 1531 if ((err = pci_enable_device(pci)) < 0) 1532 return err; 1533 1534 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1535 if (chip == NULL) { 1536 pci_disable_device(pci); 1537 return -ENOMEM; 1538 } 1539 1540 spin_lock_init(&chip->reg_lock); 1541 init_MUTEX(&chip->open_mutex); 1542 chip->card = card; 1543 chip->pci = pci; 1544 chip->irq = -1; 1545 if ((err = pci_request_regions(pci, "ATI IXP AC97")) < 0) { 1546 pci_disable_device(pci); 1547 kfree(chip); 1548 return err; 1549 } 1550 chip->addr = pci_resource_start(pci, 0); 1551 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci, 0)); 1552 if (chip->remap_addr == NULL) { 1553 snd_printk(KERN_ERR "AC'97 space ioremap problem\n"); 1554 snd_atiixp_free(chip); 1555 return -EIO; 1556 } 1557 1558 if (request_irq(pci->irq, snd_atiixp_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) { 1559 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 1560 snd_atiixp_free(chip); 1561 return -EBUSY; 1562 } 1563 chip->irq = pci->irq; 1564 pci_set_master(pci); 1565 synchronize_irq(chip->irq); 1566 1567 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1568 snd_atiixp_free(chip); 1569 return err; 1570 } 1571 1572 snd_card_set_dev(card, &pci->dev); 1573 1574 *r_chip = chip; 1575 return 0; 1576 } 1577 1578 1579 static int __devinit snd_atiixp_probe(struct pci_dev *pci, 1580 const struct pci_device_id *pci_id) 1581 { 1582 static int dev; 1583 snd_card_t *card; 1584 atiixp_t *chip; 1585 unsigned char revision; 1586 int err; 1587 1588 if (dev >= SNDRV_CARDS) 1589 return -ENODEV; 1590 if (!enable[dev]) { 1591 dev++; 1592 return -ENOENT; 1593 } 1594 1595 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 1596 if (card == NULL) 1597 return -ENOMEM; 1598 1599 pci_read_config_byte(pci, PCI_REVISION_ID, &revision); 1600 1601 strcpy(card->driver, spdif_aclink[dev] ? "ATIIXP" : "ATIIXP-SPDMA"); 1602 strcpy(card->shortname, "ATI IXP"); 1603 if ((err = snd_atiixp_create(card, pci, &chip)) < 0) 1604 goto __error; 1605 1606 if ((err = snd_atiixp_aclink_reset(chip)) < 0) 1607 goto __error; 1608 1609 chip->spdif_over_aclink = spdif_aclink[dev]; 1610 1611 if ((err = snd_atiixp_mixer_new(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) 1612 goto __error; 1613 1614 if ((err = snd_atiixp_pcm_new(chip)) < 0) 1615 goto __error; 1616 1617 snd_atiixp_proc_init(chip); 1618 1619 snd_atiixp_chip_start(chip); 1620 1621 snprintf(card->longname, sizeof(card->longname), 1622 "%s rev %x with %s at %#lx, irq %i", card->shortname, revision, 1623 chip->ac97[0] ? snd_ac97_get_short_name(chip->ac97[0]) : "?", 1624 chip->addr, chip->irq); 1625 1626 snd_card_set_pm_callback(card, snd_atiixp_suspend, snd_atiixp_resume, chip); 1627 1628 if ((err = snd_card_register(card)) < 0) 1629 goto __error; 1630 1631 pci_set_drvdata(pci, card); 1632 dev++; 1633 return 0; 1634 1635 __error: 1636 snd_card_free(card); 1637 return err; 1638 } 1639 1640 static void __devexit snd_atiixp_remove(struct pci_dev *pci) 1641 { 1642 snd_card_free(pci_get_drvdata(pci)); 1643 pci_set_drvdata(pci, NULL); 1644 } 1645 1646 static struct pci_driver driver = { 1647 .name = "ATI IXP AC97 controller", 1648 .owner = THIS_MODULE, 1649 .id_table = snd_atiixp_ids, 1650 .probe = snd_atiixp_probe, 1651 .remove = __devexit_p(snd_atiixp_remove), 1652 SND_PCI_PM_CALLBACKS 1653 }; 1654 1655 1656 static int __init alsa_card_atiixp_init(void) 1657 { 1658 return pci_register_driver(&driver); 1659 } 1660 1661 static void __exit alsa_card_atiixp_exit(void) 1662 { 1663 pci_unregister_driver(&driver); 1664 } 1665 1666 module_init(alsa_card_atiixp_init) 1667 module_exit(alsa_card_atiixp_exit) 1668