1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HD-audio stream operations 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/export.h> 9 #include <linux/clocksource.h> 10 #include <sound/compress_driver.h> 11 #include <sound/core.h> 12 #include <sound/pcm.h> 13 #include <sound/hdaudio.h> 14 #include <sound/hda_register.h> 15 #include "trace.h" 16 17 /* 18 * the hdac_stream library is intended to be used with the following 19 * transitions. The states are not formally defined in the code but loosely 20 * inspired by boolean variables. Note that the 'prepared' field is not used 21 * in this library but by the callers during the hw_params/prepare transitions 22 * 23 * | 24 * stream_init() | 25 * v 26 * +--+-------+ 27 * | unused | 28 * +--+----+--+ 29 * | ^ 30 * stream_assign() | | stream_release() 31 * v | 32 * +--+----+--+ 33 * | opened | 34 * +--+----+--+ 35 * | ^ 36 * stream_reset() | | 37 * stream_setup() | | stream_cleanup() 38 * v | 39 * +--+----+--+ 40 * | prepared | 41 * +--+----+--+ 42 * | ^ 43 * stream_start() | | stream_stop() 44 * v | 45 * +--+----+--+ 46 * | running | 47 * +----------+ 48 */ 49 50 /** 51 * snd_hdac_get_stream_stripe_ctl - get stripe control value 52 * @bus: HD-audio core bus 53 * @substream: PCM substream 54 */ 55 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, 56 struct snd_pcm_substream *substream) 57 { 58 struct snd_pcm_runtime *runtime = substream->runtime; 59 unsigned int channels = runtime->channels, 60 rate = runtime->rate, 61 bits_per_sample = runtime->sample_bits, 62 max_sdo_lines, value, sdo_line; 63 64 /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */ 65 max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO; 66 67 /* following is from HD audio spec */ 68 for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) { 69 if (rate > 48000) 70 value = (channels * bits_per_sample * 71 (rate / 48000)) / sdo_line; 72 else 73 value = (channels * bits_per_sample) / sdo_line; 74 75 if (value >= bus->sdo_limit) 76 break; 77 } 78 79 /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */ 80 return sdo_line >> 1; 81 } 82 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl); 83 84 /** 85 * snd_hdac_stream_init - initialize each stream (aka device) 86 * @bus: HD-audio core bus 87 * @azx_dev: HD-audio core stream object to initialize 88 * @idx: stream index number 89 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE) 90 * @tag: the tag id to assign 91 * 92 * Assign the starting bdl address to each stream (device) and initialize. 93 */ 94 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, 95 int idx, int direction, int tag) 96 { 97 azx_dev->bus = bus; 98 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 99 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80); 100 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ 101 azx_dev->sd_int_sta_mask = 1 << idx; 102 azx_dev->index = idx; 103 azx_dev->direction = direction; 104 azx_dev->stream_tag = tag; 105 snd_hdac_dsp_lock_init(azx_dev); 106 list_add_tail(&azx_dev->list, &bus->stream_list); 107 108 if (bus->spbcap) { 109 azx_dev->spib_addr = bus->spbcap + AZX_SPB_BASE + 110 AZX_SPB_INTERVAL * idx + 111 AZX_SPB_SPIB; 112 113 azx_dev->fifo_addr = bus->spbcap + AZX_SPB_BASE + 114 AZX_SPB_INTERVAL * idx + 115 AZX_SPB_MAXFIFO; 116 } 117 118 if (bus->drsmcap) 119 azx_dev->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE + 120 AZX_DRSM_INTERVAL * idx; 121 } 122 EXPORT_SYMBOL_GPL(snd_hdac_stream_init); 123 124 /** 125 * snd_hdac_stream_start - start a stream 126 * @azx_dev: HD-audio core stream to start 127 * 128 * Start a stream, set start_wallclk and set the running flag. 129 */ 130 void snd_hdac_stream_start(struct hdac_stream *azx_dev) 131 { 132 struct hdac_bus *bus = azx_dev->bus; 133 int stripe_ctl; 134 135 trace_snd_hdac_stream_start(bus, azx_dev); 136 137 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK); 138 139 /* enable SIE */ 140 snd_hdac_chip_updatel(bus, INTCTL, 141 1 << azx_dev->index, 142 1 << azx_dev->index); 143 /* set stripe control */ 144 if (azx_dev->stripe) { 145 if (azx_dev->substream) 146 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream); 147 else 148 stripe_ctl = 0; 149 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 150 stripe_ctl); 151 } 152 /* set DMA start and interrupt mask */ 153 if (bus->access_sdnctl_in_dword) 154 snd_hdac_stream_updatel(azx_dev, SD_CTL, 155 0, SD_CTL_DMA_START | SD_INT_MASK); 156 else 157 snd_hdac_stream_updateb(azx_dev, SD_CTL, 158 0, SD_CTL_DMA_START | SD_INT_MASK); 159 azx_dev->running = true; 160 } 161 EXPORT_SYMBOL_GPL(snd_hdac_stream_start); 162 163 /** 164 * snd_hdac_stream_clear - helper to clear stream registers and stop DMA transfers 165 * @azx_dev: HD-audio core stream to stop 166 */ 167 static void snd_hdac_stream_clear(struct hdac_stream *azx_dev) 168 { 169 snd_hdac_stream_updateb(azx_dev, SD_CTL, 170 SD_CTL_DMA_START | SD_INT_MASK, 0); 171 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ 172 if (azx_dev->stripe) 173 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0); 174 azx_dev->running = false; 175 } 176 177 /** 178 * snd_hdac_stream_stop - stop a stream 179 * @azx_dev: HD-audio core stream to stop 180 * 181 * Stop a stream DMA and disable stream interrupt 182 */ 183 void snd_hdac_stream_stop(struct hdac_stream *azx_dev) 184 { 185 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev); 186 187 snd_hdac_stream_clear(azx_dev); 188 /* disable SIE */ 189 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0); 190 } 191 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop); 192 193 /** 194 * snd_hdac_stop_streams - stop all streams 195 * @bus: HD-audio core bus 196 */ 197 void snd_hdac_stop_streams(struct hdac_bus *bus) 198 { 199 struct hdac_stream *stream; 200 201 list_for_each_entry(stream, &bus->stream_list, list) 202 snd_hdac_stream_stop(stream); 203 } 204 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams); 205 206 /** 207 * snd_hdac_stop_streams_and_chip - stop all streams and chip if running 208 * @bus: HD-audio core bus 209 */ 210 void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus) 211 { 212 213 if (bus->chip_init) { 214 snd_hdac_stop_streams(bus); 215 snd_hdac_bus_stop_chip(bus); 216 } 217 } 218 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip); 219 220 /** 221 * snd_hdac_stream_reset - reset a stream 222 * @azx_dev: HD-audio core stream to reset 223 */ 224 void snd_hdac_stream_reset(struct hdac_stream *azx_dev) 225 { 226 unsigned char val; 227 int dma_run_state; 228 229 snd_hdac_stream_clear(azx_dev); 230 231 dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START; 232 233 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET); 234 235 /* wait for hardware to report that the stream entered reset */ 236 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, (val & SD_CTL_STREAM_RESET), 3, 300); 237 238 if (azx_dev->bus->dma_stop_delay && dma_run_state) 239 udelay(azx_dev->bus->dma_stop_delay); 240 241 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0); 242 243 /* wait for hardware to report that the stream is out of reset */ 244 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, !(val & SD_CTL_STREAM_RESET), 3, 300); 245 246 /* reset first position - may not be synced with hw at this time */ 247 if (azx_dev->posbuf) 248 *azx_dev->posbuf = 0; 249 } 250 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset); 251 252 /** 253 * snd_hdac_stream_setup - set up the SD for streaming 254 * @azx_dev: HD-audio core stream to set up 255 */ 256 int snd_hdac_stream_setup(struct hdac_stream *azx_dev) 257 { 258 struct hdac_bus *bus = azx_dev->bus; 259 struct snd_pcm_runtime *runtime; 260 unsigned int val; 261 u16 reg; 262 int ret; 263 264 if (azx_dev->substream) 265 runtime = azx_dev->substream->runtime; 266 else 267 runtime = NULL; 268 /* make sure the run bit is zero for SD */ 269 snd_hdac_stream_clear(azx_dev); 270 /* program the stream_tag */ 271 val = snd_hdac_stream_readl(azx_dev, SD_CTL); 272 val = (val & ~SD_CTL_STREAM_TAG_MASK) | 273 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); 274 if (!bus->snoop) 275 val |= SD_CTL_TRAFFIC_PRIO; 276 snd_hdac_stream_writel(azx_dev, SD_CTL, val); 277 278 /* program the length of samples in cyclic buffer */ 279 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize); 280 281 /* program the stream format */ 282 /* this value needs to be the same as the one programmed */ 283 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val); 284 285 /* program the stream LVI (last valid index) of the BDL */ 286 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1); 287 288 /* program the BDL address */ 289 /* lower BDL address */ 290 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); 291 /* upper BDL address */ 292 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 293 upper_32_bits(azx_dev->bdl.addr)); 294 295 /* enable the position buffer */ 296 if (bus->use_posbuf && bus->posbuf.addr) { 297 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE)) 298 snd_hdac_chip_writel(bus, DPLBASE, 299 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE); 300 } 301 302 /* set the interrupt enable bits in the descriptor control register */ 303 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK); 304 305 /* Once SDxFMT is set, the controller programs SDxFIFOS to non-zero value. */ 306 ret = snd_hdac_stream_readw_poll(azx_dev, SD_FIFOSIZE, reg, reg & AZX_SD_FIFOSIZE_MASK, 307 3, 300); 308 if (ret) 309 dev_dbg(bus->dev, "polling SD_FIFOSIZE 0x%04x failed: %d\n", 310 AZX_REG_SD_FIFOSIZE, ret); 311 azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1; 312 313 /* when LPIB delay correction gives a small negative value, 314 * we ignore it; currently set the threshold statically to 315 * 64 frames 316 */ 317 if (runtime && runtime->period_size > 64) 318 azx_dev->delay_negative_threshold = 319 -frames_to_bytes(runtime, 64); 320 else 321 azx_dev->delay_negative_threshold = 0; 322 323 /* wallclk has 24Mhz clock source */ 324 if (runtime) 325 azx_dev->period_wallclk = (((runtime->period_size * 24000) / 326 runtime->rate) * 1000); 327 328 return 0; 329 } 330 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup); 331 332 /** 333 * snd_hdac_stream_cleanup - cleanup a stream 334 * @azx_dev: HD-audio core stream to clean up 335 */ 336 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev) 337 { 338 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 339 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 340 snd_hdac_stream_writel(azx_dev, SD_CTL, 0); 341 azx_dev->bufsize = 0; 342 azx_dev->period_bytes = 0; 343 azx_dev->format_val = 0; 344 } 345 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup); 346 347 /** 348 * snd_hdac_stream_assign - assign a stream for the PCM 349 * @bus: HD-audio core bus 350 * @substream: PCM substream to assign 351 * 352 * Look for an unused stream for the given PCM substream, assign it 353 * and return the stream object. If no stream is free, returns NULL. 354 * The function tries to keep using the same stream object when it's used 355 * beforehand. Also, when bus->reverse_assign flag is set, the last free 356 * or matching entry is returned. This is needed for some strange codecs. 357 */ 358 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, 359 struct snd_pcm_substream *substream) 360 { 361 struct hdac_stream *azx_dev; 362 struct hdac_stream *res = NULL; 363 364 /* make a non-zero unique key for the substream */ 365 int key = (substream->pcm->device << 16) | (substream->number << 2) | 366 (substream->stream + 1); 367 368 spin_lock_irq(&bus->reg_lock); 369 list_for_each_entry(azx_dev, &bus->stream_list, list) { 370 if (azx_dev->direction != substream->stream) 371 continue; 372 if (azx_dev->opened) 373 continue; 374 if (azx_dev->assigned_key == key) { 375 res = azx_dev; 376 break; 377 } 378 if (!res || bus->reverse_assign) 379 res = azx_dev; 380 } 381 if (res) { 382 res->opened = 1; 383 res->running = 0; 384 res->assigned_key = key; 385 res->substream = substream; 386 } 387 spin_unlock_irq(&bus->reg_lock); 388 return res; 389 } 390 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign); 391 392 /** 393 * snd_hdac_stream_release_locked - release the assigned stream 394 * @azx_dev: HD-audio core stream to release 395 * 396 * Release the stream that has been assigned by snd_hdac_stream_assign(). 397 * The bus->reg_lock needs to be taken at a higher level 398 */ 399 void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev) 400 { 401 azx_dev->opened = 0; 402 azx_dev->running = 0; 403 azx_dev->substream = NULL; 404 } 405 EXPORT_SYMBOL_GPL(snd_hdac_stream_release_locked); 406 407 /** 408 * snd_hdac_stream_release - release the assigned stream 409 * @azx_dev: HD-audio core stream to release 410 * 411 * Release the stream that has been assigned by snd_hdac_stream_assign(). 412 */ 413 void snd_hdac_stream_release(struct hdac_stream *azx_dev) 414 { 415 struct hdac_bus *bus = azx_dev->bus; 416 417 spin_lock_irq(&bus->reg_lock); 418 snd_hdac_stream_release_locked(azx_dev); 419 spin_unlock_irq(&bus->reg_lock); 420 } 421 EXPORT_SYMBOL_GPL(snd_hdac_stream_release); 422 423 /** 424 * snd_hdac_get_stream - return hdac_stream based on stream_tag and 425 * direction 426 * 427 * @bus: HD-audio core bus 428 * @dir: direction for the stream to be found 429 * @stream_tag: stream tag for stream to be found 430 */ 431 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, 432 int dir, int stream_tag) 433 { 434 struct hdac_stream *s; 435 436 list_for_each_entry(s, &bus->stream_list, list) { 437 if (s->direction == dir && s->stream_tag == stream_tag) 438 return s; 439 } 440 441 return NULL; 442 } 443 EXPORT_SYMBOL_GPL(snd_hdac_get_stream); 444 445 /* 446 * set up a BDL entry 447 */ 448 static int setup_bdle(struct hdac_bus *bus, 449 struct snd_dma_buffer *dmab, 450 struct hdac_stream *azx_dev, __le32 **bdlp, 451 int ofs, int size, int with_ioc) 452 { 453 __le32 *bdl = *bdlp; 454 455 while (size > 0) { 456 dma_addr_t addr; 457 int chunk; 458 459 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) 460 return -EINVAL; 461 462 addr = snd_sgbuf_get_addr(dmab, ofs); 463 /* program the address field of the BDL entry */ 464 bdl[0] = cpu_to_le32((u32)addr); 465 bdl[1] = cpu_to_le32(upper_32_bits(addr)); 466 /* program the size field of the BDL entry */ 467 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); 468 /* one BDLE cannot cross 4K boundary on CTHDA chips */ 469 if (bus->align_bdle_4k) { 470 u32 remain = 0x1000 - (ofs & 0xfff); 471 472 if (chunk > remain) 473 chunk = remain; 474 } 475 bdl[2] = cpu_to_le32(chunk); 476 /* program the IOC to enable interrupt 477 * only when the whole fragment is processed 478 */ 479 size -= chunk; 480 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); 481 bdl += 4; 482 azx_dev->frags++; 483 ofs += chunk; 484 } 485 *bdlp = bdl; 486 return ofs; 487 } 488 489 /** 490 * snd_hdac_stream_setup_periods - set up BDL entries 491 * @azx_dev: HD-audio core stream to set up 492 * 493 * Set up the buffer descriptor table of the given stream based on the 494 * period and buffer sizes of the assigned PCM substream. 495 */ 496 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev) 497 { 498 struct hdac_bus *bus = azx_dev->bus; 499 struct snd_pcm_substream *substream = azx_dev->substream; 500 struct snd_compr_stream *cstream = azx_dev->cstream; 501 struct snd_pcm_runtime *runtime = NULL; 502 struct snd_dma_buffer *dmab; 503 __le32 *bdl; 504 int i, ofs, periods, period_bytes; 505 int pos_adj, pos_align; 506 507 if (substream) { 508 runtime = substream->runtime; 509 dmab = snd_pcm_get_dma_buf(substream); 510 } else if (cstream) { 511 dmab = snd_pcm_get_dma_buf(cstream); 512 } else { 513 WARN(1, "No substream or cstream assigned\n"); 514 return -EINVAL; 515 } 516 517 /* reset BDL address */ 518 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 519 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 520 521 period_bytes = azx_dev->period_bytes; 522 periods = azx_dev->bufsize / period_bytes; 523 524 /* program the initial BDL entries */ 525 bdl = (__le32 *)azx_dev->bdl.area; 526 ofs = 0; 527 azx_dev->frags = 0; 528 529 pos_adj = bus->bdl_pos_adj; 530 if (runtime && !azx_dev->no_period_wakeup && pos_adj > 0) { 531 pos_align = pos_adj; 532 pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000); 533 if (!pos_adj) 534 pos_adj = pos_align; 535 else 536 pos_adj = roundup(pos_adj, pos_align); 537 pos_adj = frames_to_bytes(runtime, pos_adj); 538 if (pos_adj >= period_bytes) { 539 dev_warn(bus->dev, "Too big adjustment %d\n", 540 pos_adj); 541 pos_adj = 0; 542 } else { 543 ofs = setup_bdle(bus, dmab, azx_dev, 544 &bdl, ofs, pos_adj, true); 545 if (ofs < 0) 546 goto error; 547 } 548 } else 549 pos_adj = 0; 550 551 for (i = 0; i < periods; i++) { 552 if (i == periods - 1 && pos_adj) 553 ofs = setup_bdle(bus, dmab, azx_dev, 554 &bdl, ofs, period_bytes - pos_adj, 0); 555 else 556 ofs = setup_bdle(bus, dmab, azx_dev, 557 &bdl, ofs, period_bytes, 558 !azx_dev->no_period_wakeup); 559 if (ofs < 0) 560 goto error; 561 } 562 return 0; 563 564 error: 565 dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n", 566 azx_dev->bufsize, period_bytes); 567 return -EINVAL; 568 } 569 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods); 570 571 /** 572 * snd_hdac_stream_set_params - set stream parameters 573 * @azx_dev: HD-audio core stream for which parameters are to be set 574 * @format_val: format value parameter 575 * 576 * Setup the HD-audio core stream parameters from substream of the stream 577 * and passed format value 578 */ 579 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, 580 unsigned int format_val) 581 { 582 struct snd_pcm_substream *substream = azx_dev->substream; 583 struct snd_compr_stream *cstream = azx_dev->cstream; 584 unsigned int bufsize, period_bytes; 585 unsigned int no_period_wakeup; 586 int err; 587 588 if (substream) { 589 bufsize = snd_pcm_lib_buffer_bytes(substream); 590 period_bytes = snd_pcm_lib_period_bytes(substream); 591 no_period_wakeup = substream->runtime->no_period_wakeup; 592 } else if (cstream) { 593 bufsize = cstream->runtime->buffer_size; 594 period_bytes = cstream->runtime->fragment_size; 595 no_period_wakeup = 0; 596 } else { 597 return -EINVAL; 598 } 599 600 if (bufsize != azx_dev->bufsize || 601 period_bytes != azx_dev->period_bytes || 602 format_val != azx_dev->format_val || 603 no_period_wakeup != azx_dev->no_period_wakeup) { 604 azx_dev->bufsize = bufsize; 605 azx_dev->period_bytes = period_bytes; 606 azx_dev->format_val = format_val; 607 azx_dev->no_period_wakeup = no_period_wakeup; 608 err = snd_hdac_stream_setup_periods(azx_dev); 609 if (err < 0) 610 return err; 611 } 612 return 0; 613 } 614 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params); 615 616 static u64 azx_cc_read(const struct cyclecounter *cc) 617 { 618 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc); 619 620 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK); 621 } 622 623 static void azx_timecounter_init(struct hdac_stream *azx_dev, 624 bool force, u64 last) 625 { 626 struct timecounter *tc = &azx_dev->tc; 627 struct cyclecounter *cc = &azx_dev->cc; 628 u64 nsec; 629 630 cc->read = azx_cc_read; 631 cc->mask = CLOCKSOURCE_MASK(32); 632 633 /* 634 * Calculate the optimal mult/shift values. The counter wraps 635 * around after ~178.9 seconds. 636 */ 637 clocks_calc_mult_shift(&cc->mult, &cc->shift, 24000000, 638 NSEC_PER_SEC, 178); 639 640 nsec = 0; /* audio time is elapsed time since trigger */ 641 timecounter_init(tc, cc, nsec); 642 if (force) { 643 /* 644 * force timecounter to use predefined value, 645 * used for synchronized starts 646 */ 647 tc->cycle_last = last; 648 } 649 } 650 651 /** 652 * snd_hdac_stream_timecounter_init - initialize time counter 653 * @azx_dev: HD-audio core stream (master stream) 654 * @streams: bit flags of streams to set up 655 * 656 * Initializes the time counter of streams marked by the bit flags (each 657 * bit corresponds to the stream index). 658 * The trigger timestamp of PCM substream assigned to the given stream is 659 * updated accordingly, too. 660 */ 661 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, 662 unsigned int streams) 663 { 664 struct hdac_bus *bus = azx_dev->bus; 665 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime; 666 struct hdac_stream *s; 667 bool inited = false; 668 u64 cycle_last = 0; 669 int i = 0; 670 671 list_for_each_entry(s, &bus->stream_list, list) { 672 if (streams & (1 << i)) { 673 azx_timecounter_init(s, inited, cycle_last); 674 if (!inited) { 675 inited = true; 676 cycle_last = s->tc.cycle_last; 677 } 678 } 679 i++; 680 } 681 682 snd_pcm_gettime(runtime, &runtime->trigger_tstamp); 683 runtime->trigger_tstamp_latched = true; 684 } 685 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init); 686 687 /** 688 * snd_hdac_stream_sync_trigger - turn on/off stream sync register 689 * @azx_dev: HD-audio core stream (master stream) 690 * @set: true = set, false = clear 691 * @streams: bit flags of streams to sync 692 * @reg: the stream sync register address 693 */ 694 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, 695 unsigned int streams, unsigned int reg) 696 { 697 struct hdac_bus *bus = azx_dev->bus; 698 unsigned int val; 699 700 if (!reg) 701 reg = AZX_REG_SSYNC; 702 val = _snd_hdac_chip_readl(bus, reg); 703 if (set) 704 val |= streams; 705 else 706 val &= ~streams; 707 _snd_hdac_chip_writel(bus, reg, val); 708 } 709 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger); 710 711 /** 712 * snd_hdac_stream_sync - sync with start/stop trigger operation 713 * @azx_dev: HD-audio core stream (master stream) 714 * @start: true = start, false = stop 715 * @streams: bit flags of streams to sync 716 * 717 * For @start = true, wait until all FIFOs get ready. 718 * For @start = false, wait until all RUN bits are cleared. 719 */ 720 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, 721 unsigned int streams) 722 { 723 struct hdac_bus *bus = azx_dev->bus; 724 int i, nwait, timeout; 725 struct hdac_stream *s; 726 727 for (timeout = 5000; timeout; timeout--) { 728 nwait = 0; 729 i = 0; 730 list_for_each_entry(s, &bus->stream_list, list) { 731 if (!(streams & (1 << i++))) 732 continue; 733 734 if (start) { 735 /* check FIFO gets ready */ 736 if (!(snd_hdac_stream_readb(s, SD_STS) & 737 SD_STS_FIFO_READY)) 738 nwait++; 739 } else { 740 /* check RUN bit is cleared */ 741 if (snd_hdac_stream_readb(s, SD_CTL) & 742 SD_CTL_DMA_START) { 743 nwait++; 744 /* 745 * Perform stream reset if DMA RUN 746 * bit not cleared within given timeout 747 */ 748 if (timeout == 1) 749 snd_hdac_stream_reset(s); 750 } 751 } 752 } 753 if (!nwait) 754 break; 755 cpu_relax(); 756 } 757 } 758 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync); 759 760 /** 761 * snd_hdac_stream_spbcap_enable - enable SPIB for a stream 762 * @bus: HD-audio core bus 763 * @enable: flag to enable/disable SPIB 764 * @index: stream index for which SPIB need to be enabled 765 */ 766 void snd_hdac_stream_spbcap_enable(struct hdac_bus *bus, 767 bool enable, int index) 768 { 769 u32 mask = 0; 770 771 if (!bus->spbcap) { 772 dev_err(bus->dev, "Address of SPB capability is NULL\n"); 773 return; 774 } 775 776 mask |= (1 << index); 777 778 if (enable) 779 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask); 780 else 781 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0); 782 } 783 EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enable); 784 785 /** 786 * snd_hdac_stream_set_spib - sets the spib value of a stream 787 * @bus: HD-audio core bus 788 * @azx_dev: hdac_stream 789 * @value: spib value to set 790 */ 791 int snd_hdac_stream_set_spib(struct hdac_bus *bus, 792 struct hdac_stream *azx_dev, u32 value) 793 { 794 if (!bus->spbcap) { 795 dev_err(bus->dev, "Address of SPB capability is NULL\n"); 796 return -EINVAL; 797 } 798 799 writel(value, azx_dev->spib_addr); 800 801 return 0; 802 } 803 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib); 804 805 /** 806 * snd_hdac_stream_get_spbmaxfifo - gets the spib value of a stream 807 * @bus: HD-audio core bus 808 * @azx_dev: hdac_stream 809 * 810 * Return maxfifo for the stream 811 */ 812 int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus, 813 struct hdac_stream *azx_dev) 814 { 815 if (!bus->spbcap) { 816 dev_err(bus->dev, "Address of SPB capability is NULL\n"); 817 return -EINVAL; 818 } 819 820 return readl(azx_dev->fifo_addr); 821 } 822 EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfifo); 823 824 /** 825 * snd_hdac_stream_drsm_enable - enable DMA resume for a stream 826 * @bus: HD-audio core bus 827 * @enable: flag to enable/disable DRSM 828 * @index: stream index for which DRSM need to be enabled 829 */ 830 void snd_hdac_stream_drsm_enable(struct hdac_bus *bus, 831 bool enable, int index) 832 { 833 u32 mask = 0; 834 835 if (!bus->drsmcap) { 836 dev_err(bus->dev, "Address of DRSM capability is NULL\n"); 837 return; 838 } 839 840 mask |= (1 << index); 841 842 if (enable) 843 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask); 844 else 845 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0); 846 } 847 EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable); 848 849 /* 850 * snd_hdac_stream_wait_drsm - wait for HW to clear RSM for a stream 851 * @azx_dev: HD-audio core stream to await RSM for 852 * 853 * Returns 0 on success and -ETIMEDOUT upon a timeout. 854 */ 855 int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev) 856 { 857 struct hdac_bus *bus = azx_dev->bus; 858 u32 mask, reg; 859 int ret; 860 861 mask = 1 << azx_dev->index; 862 863 ret = read_poll_timeout(snd_hdac_reg_readl, reg, !(reg & mask), 250, 2000, false, bus, 864 bus->drsmcap + AZX_REG_DRSM_CTL); 865 if (ret) 866 dev_dbg(bus->dev, "polling RSM 0x%08x failed: %d\n", mask, ret); 867 return ret; 868 } 869 EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm); 870 871 /** 872 * snd_hdac_stream_set_dpibr - sets the dpibr value of a stream 873 * @bus: HD-audio core bus 874 * @azx_dev: hdac_stream 875 * @value: dpib value to set 876 */ 877 int snd_hdac_stream_set_dpibr(struct hdac_bus *bus, 878 struct hdac_stream *azx_dev, u32 value) 879 { 880 if (!bus->drsmcap) { 881 dev_err(bus->dev, "Address of DRSM capability is NULL\n"); 882 return -EINVAL; 883 } 884 885 writel(value, azx_dev->dpibr_addr); 886 887 return 0; 888 } 889 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr); 890 891 /** 892 * snd_hdac_stream_set_lpib - sets the lpib value of a stream 893 * @azx_dev: hdac_stream 894 * @value: lpib value to set 895 */ 896 int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value) 897 { 898 snd_hdac_stream_writel(azx_dev, SD_LPIB, value); 899 900 return 0; 901 } 902 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib); 903 904 #ifdef CONFIG_SND_HDA_DSP_LOADER 905 /** 906 * snd_hdac_dsp_prepare - prepare for DSP loading 907 * @azx_dev: HD-audio core stream used for DSP loading 908 * @format: HD-audio stream format 909 * @byte_size: data chunk byte size 910 * @bufp: allocated buffer 911 * 912 * Allocate the buffer for the given size and set up the given stream for 913 * DSP loading. Returns the stream tag (>= 0), or a negative error code. 914 */ 915 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, 916 unsigned int byte_size, struct snd_dma_buffer *bufp) 917 { 918 struct hdac_bus *bus = azx_dev->bus; 919 __le32 *bdl; 920 int err; 921 922 snd_hdac_dsp_lock(azx_dev); 923 spin_lock_irq(&bus->reg_lock); 924 if (azx_dev->running || azx_dev->locked) { 925 spin_unlock_irq(&bus->reg_lock); 926 err = -EBUSY; 927 goto unlock; 928 } 929 azx_dev->locked = true; 930 spin_unlock_irq(&bus->reg_lock); 931 932 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev, 933 byte_size, bufp); 934 if (err < 0) 935 goto err_alloc; 936 937 azx_dev->substream = NULL; 938 azx_dev->bufsize = byte_size; 939 azx_dev->period_bytes = byte_size; 940 azx_dev->format_val = format; 941 942 snd_hdac_stream_reset(azx_dev); 943 944 /* reset BDL address */ 945 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 946 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 947 948 azx_dev->frags = 0; 949 bdl = (__le32 *)azx_dev->bdl.area; 950 err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0); 951 if (err < 0) 952 goto error; 953 954 snd_hdac_stream_setup(azx_dev); 955 snd_hdac_dsp_unlock(azx_dev); 956 return azx_dev->stream_tag; 957 958 error: 959 snd_dma_free_pages(bufp); 960 err_alloc: 961 spin_lock_irq(&bus->reg_lock); 962 azx_dev->locked = false; 963 spin_unlock_irq(&bus->reg_lock); 964 unlock: 965 snd_hdac_dsp_unlock(azx_dev); 966 return err; 967 } 968 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare); 969 970 /** 971 * snd_hdac_dsp_trigger - start / stop DSP loading 972 * @azx_dev: HD-audio core stream used for DSP loading 973 * @start: trigger start or stop 974 */ 975 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) 976 { 977 if (start) 978 snd_hdac_stream_start(azx_dev); 979 else 980 snd_hdac_stream_stop(azx_dev); 981 } 982 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger); 983 984 /** 985 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal 986 * @azx_dev: HD-audio core stream used for DSP loading 987 * @dmab: buffer used by DSP loading 988 */ 989 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, 990 struct snd_dma_buffer *dmab) 991 { 992 struct hdac_bus *bus = azx_dev->bus; 993 994 if (!dmab->area || !azx_dev->locked) 995 return; 996 997 snd_hdac_dsp_lock(azx_dev); 998 /* reset BDL address */ 999 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0); 1000 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0); 1001 snd_hdac_stream_writel(azx_dev, SD_CTL, 0); 1002 azx_dev->bufsize = 0; 1003 azx_dev->period_bytes = 0; 1004 azx_dev->format_val = 0; 1005 1006 snd_dma_free_pages(dmab); 1007 dmab->area = NULL; 1008 1009 spin_lock_irq(&bus->reg_lock); 1010 azx_dev->locked = false; 1011 spin_unlock_irq(&bus->reg_lock); 1012 snd_hdac_dsp_unlock(azx_dev); 1013 } 1014 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup); 1015 #endif /* CONFIG_SND_HDA_DSP_LOADER */ 1016