1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HD-audio controller helpers 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/export.h> 9 #include <sound/core.h> 10 #include <sound/hdaudio.h> 11 #include <sound/hda_register.h> 12 13 /* clear CORB read pointer properly */ 14 static void azx_clear_corbrp(struct hdac_bus *bus) 15 { 16 int timeout; 17 18 for (timeout = 1000; timeout > 0; timeout--) { 19 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST) 20 break; 21 udelay(1); 22 } 23 if (timeout <= 0) 24 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n", 25 snd_hdac_chip_readw(bus, CORBRP)); 26 27 snd_hdac_chip_writew(bus, CORBRP, 0); 28 for (timeout = 1000; timeout > 0; timeout--) { 29 if (snd_hdac_chip_readw(bus, CORBRP) == 0) 30 break; 31 udelay(1); 32 } 33 if (timeout <= 0) 34 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n", 35 snd_hdac_chip_readw(bus, CORBRP)); 36 } 37 38 /** 39 * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers 40 * @bus: HD-audio core bus 41 */ 42 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus) 43 { 44 WARN_ON_ONCE(!bus->rb.area); 45 46 spin_lock_irq(&bus->reg_lock); 47 /* CORB set up */ 48 bus->corb.addr = bus->rb.addr; 49 bus->corb.buf = (__le32 *)bus->rb.area; 50 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr); 51 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr)); 52 53 /* set the corb size to 256 entries (ULI requires explicitly) */ 54 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02); 55 /* set the corb write pointer to 0 */ 56 snd_hdac_chip_writew(bus, CORBWP, 0); 57 58 /* reset the corb hw read pointer */ 59 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST); 60 if (!bus->corbrp_self_clear) 61 azx_clear_corbrp(bus); 62 63 /* enable corb dma */ 64 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN); 65 66 /* RIRB set up */ 67 bus->rirb.addr = bus->rb.addr + 2048; 68 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048); 69 bus->rirb.wp = bus->rirb.rp = 0; 70 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds)); 71 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr); 72 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr)); 73 74 /* set the rirb size to 256 entries (ULI requires explicitly) */ 75 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02); 76 /* reset the rirb hw write pointer */ 77 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST); 78 /* set N=1, get RIRB response interrupt for new entry */ 79 snd_hdac_chip_writew(bus, RINTCNT, 1); 80 /* enable rirb dma and response irq */ 81 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN); 82 spin_unlock_irq(&bus->reg_lock); 83 } 84 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io); 85 86 /* wait for cmd dmas till they are stopped */ 87 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus) 88 { 89 unsigned long timeout; 90 91 timeout = jiffies + msecs_to_jiffies(100); 92 while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN) 93 && time_before(jiffies, timeout)) 94 udelay(10); 95 96 timeout = jiffies + msecs_to_jiffies(100); 97 while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN) 98 && time_before(jiffies, timeout)) 99 udelay(10); 100 } 101 102 /** 103 * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers 104 * @bus: HD-audio core bus 105 */ 106 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus) 107 { 108 spin_lock_irq(&bus->reg_lock); 109 /* disable ringbuffer DMAs */ 110 snd_hdac_chip_writeb(bus, RIRBCTL, 0); 111 snd_hdac_chip_writeb(bus, CORBCTL, 0); 112 spin_unlock_irq(&bus->reg_lock); 113 114 hdac_wait_for_cmd_dmas(bus); 115 116 spin_lock_irq(&bus->reg_lock); 117 /* disable unsolicited responses */ 118 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0); 119 spin_unlock_irq(&bus->reg_lock); 120 } 121 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io); 122 123 static unsigned int azx_command_addr(u32 cmd) 124 { 125 unsigned int addr = cmd >> 28; 126 127 if (snd_BUG_ON(addr >= HDA_MAX_CODECS)) 128 addr = 0; 129 return addr; 130 } 131 132 /** 133 * snd_hdac_bus_send_cmd - send a command verb via CORB 134 * @bus: HD-audio core bus 135 * @val: encoded verb value to send 136 * 137 * Returns zero for success or a negative error code. 138 */ 139 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val) 140 { 141 unsigned int addr = azx_command_addr(val); 142 unsigned int wp, rp; 143 144 spin_lock_irq(&bus->reg_lock); 145 146 bus->last_cmd[azx_command_addr(val)] = val; 147 148 /* add command to corb */ 149 wp = snd_hdac_chip_readw(bus, CORBWP); 150 if (wp == 0xffff) { 151 /* something wrong, controller likely turned to D3 */ 152 spin_unlock_irq(&bus->reg_lock); 153 return -EIO; 154 } 155 wp++; 156 wp %= AZX_MAX_CORB_ENTRIES; 157 158 rp = snd_hdac_chip_readw(bus, CORBRP); 159 if (wp == rp) { 160 /* oops, it's full */ 161 spin_unlock_irq(&bus->reg_lock); 162 return -EAGAIN; 163 } 164 165 bus->rirb.cmds[addr]++; 166 bus->corb.buf[wp] = cpu_to_le32(val); 167 snd_hdac_chip_writew(bus, CORBWP, wp); 168 169 spin_unlock_irq(&bus->reg_lock); 170 171 return 0; 172 } 173 EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd); 174 175 #define AZX_RIRB_EX_UNSOL_EV (1<<4) 176 177 /** 178 * snd_hdac_bus_update_rirb - retrieve RIRB entries 179 * @bus: HD-audio core bus 180 * 181 * Usually called from interrupt handler. 182 */ 183 void snd_hdac_bus_update_rirb(struct hdac_bus *bus) 184 { 185 unsigned int rp, wp; 186 unsigned int addr; 187 u32 res, res_ex; 188 189 wp = snd_hdac_chip_readw(bus, RIRBWP); 190 if (wp == 0xffff) { 191 /* something wrong, controller likely turned to D3 */ 192 return; 193 } 194 195 if (wp == bus->rirb.wp) 196 return; 197 bus->rirb.wp = wp; 198 199 while (bus->rirb.rp != wp) { 200 bus->rirb.rp++; 201 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES; 202 203 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */ 204 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]); 205 res = le32_to_cpu(bus->rirb.buf[rp]); 206 addr = res_ex & 0xf; 207 if (addr >= HDA_MAX_CODECS) { 208 dev_err(bus->dev, 209 "spurious response %#x:%#x, rp = %d, wp = %d", 210 res, res_ex, bus->rirb.rp, wp); 211 snd_BUG(); 212 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV) 213 snd_hdac_bus_queue_event(bus, res, res_ex); 214 else if (bus->rirb.cmds[addr]) { 215 bus->rirb.res[addr] = res; 216 bus->rirb.cmds[addr]--; 217 } else { 218 dev_err_ratelimited(bus->dev, 219 "spurious response %#x:%#x, last cmd=%#08x\n", 220 res, res_ex, bus->last_cmd[addr]); 221 } 222 } 223 } 224 EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb); 225 226 /** 227 * snd_hdac_bus_get_response - receive a response via RIRB 228 * @bus: HD-audio core bus 229 * @addr: codec address 230 * @res: pointer to store the value, NULL when not needed 231 * 232 * Returns zero if a value is read, or a negative error code. 233 */ 234 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, 235 unsigned int *res) 236 { 237 unsigned long timeout; 238 unsigned long loopcounter; 239 240 timeout = jiffies + msecs_to_jiffies(1000); 241 242 for (loopcounter = 0;; loopcounter++) { 243 spin_lock_irq(&bus->reg_lock); 244 if (!bus->rirb.cmds[addr]) { 245 if (res) 246 *res = bus->rirb.res[addr]; /* the last value */ 247 spin_unlock_irq(&bus->reg_lock); 248 return 0; 249 } 250 spin_unlock_irq(&bus->reg_lock); 251 if (time_after(jiffies, timeout)) 252 break; 253 if (loopcounter > 3000) 254 msleep(2); /* temporary workaround */ 255 else { 256 udelay(10); 257 cond_resched(); 258 } 259 } 260 261 return -EIO; 262 } 263 EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response); 264 265 #define HDAC_MAX_CAPS 10 266 /** 267 * snd_hdac_bus_parse_capabilities - parse capability structure 268 * @bus: the pointer to bus object 269 * 270 * Returns 0 if successful, or a negative error code. 271 */ 272 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus) 273 { 274 unsigned int cur_cap; 275 unsigned int offset; 276 unsigned int counter = 0; 277 278 offset = snd_hdac_chip_readw(bus, LLCH); 279 280 /* Lets walk the linked capabilities list */ 281 do { 282 cur_cap = _snd_hdac_chip_readl(bus, offset); 283 284 dev_dbg(bus->dev, "Capability version: 0x%x\n", 285 (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF); 286 287 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n", 288 (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF); 289 290 if (cur_cap == -1) { 291 dev_dbg(bus->dev, "Invalid capability reg read\n"); 292 break; 293 } 294 295 switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) { 296 case AZX_ML_CAP_ID: 297 dev_dbg(bus->dev, "Found ML capability\n"); 298 bus->mlcap = bus->remap_addr + offset; 299 break; 300 301 case AZX_GTS_CAP_ID: 302 dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset); 303 bus->gtscap = bus->remap_addr + offset; 304 break; 305 306 case AZX_PP_CAP_ID: 307 /* PP capability found, the Audio DSP is present */ 308 dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset); 309 bus->ppcap = bus->remap_addr + offset; 310 break; 311 312 case AZX_SPB_CAP_ID: 313 /* SPIB capability found, handler function */ 314 dev_dbg(bus->dev, "Found SPB capability\n"); 315 bus->spbcap = bus->remap_addr + offset; 316 break; 317 318 case AZX_DRSM_CAP_ID: 319 /* DMA resume capability found, handler function */ 320 dev_dbg(bus->dev, "Found DRSM capability\n"); 321 bus->drsmcap = bus->remap_addr + offset; 322 break; 323 324 default: 325 dev_err(bus->dev, "Unknown capability %d\n", cur_cap); 326 cur_cap = 0; 327 break; 328 } 329 330 counter++; 331 332 if (counter > HDAC_MAX_CAPS) { 333 dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n"); 334 break; 335 } 336 337 /* read the offset of next capability */ 338 offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK; 339 340 } while (offset); 341 342 return 0; 343 } 344 EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities); 345 346 /* 347 * Lowlevel interface 348 */ 349 350 /** 351 * snd_hdac_bus_enter_link_reset - enter link reset 352 * @bus: HD-audio core bus 353 * 354 * Enter to the link reset state. 355 */ 356 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus) 357 { 358 unsigned long timeout; 359 360 /* reset controller */ 361 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0); 362 363 timeout = jiffies + msecs_to_jiffies(100); 364 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) && 365 time_before(jiffies, timeout)) 366 usleep_range(500, 1000); 367 } 368 EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset); 369 370 /** 371 * snd_hdac_bus_exit_link_reset - exit link reset 372 * @bus: HD-audio core bus 373 * 374 * Exit from the link reset state. 375 */ 376 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus) 377 { 378 unsigned long timeout; 379 380 snd_hdac_chip_updateb(bus, GCTL, AZX_GCTL_RESET, AZX_GCTL_RESET); 381 382 timeout = jiffies + msecs_to_jiffies(100); 383 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout)) 384 usleep_range(500, 1000); 385 } 386 EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset); 387 388 /* reset codec link */ 389 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset) 390 { 391 if (!full_reset) 392 goto skip_reset; 393 394 /* clear STATESTS */ 395 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK); 396 397 /* reset controller */ 398 snd_hdac_bus_enter_link_reset(bus); 399 400 /* delay for >= 100us for codec PLL to settle per spec 401 * Rev 0.9 section 5.5.1 402 */ 403 usleep_range(500, 1000); 404 405 /* Bring controller out of reset */ 406 snd_hdac_bus_exit_link_reset(bus); 407 408 /* Brent Chartrand said to wait >= 540us for codecs to initialize */ 409 usleep_range(1000, 1200); 410 411 skip_reset: 412 /* check to see if controller is ready */ 413 if (!snd_hdac_chip_readb(bus, GCTL)) { 414 dev_dbg(bus->dev, "controller not ready!\n"); 415 return -EBUSY; 416 } 417 418 /* Accept unsolicited responses */ 419 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL); 420 421 /* detect codecs */ 422 if (!bus->codec_mask) { 423 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS); 424 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask); 425 } 426 427 return 0; 428 } 429 EXPORT_SYMBOL_GPL(snd_hdac_bus_reset_link); 430 431 /* enable interrupts */ 432 static void azx_int_enable(struct hdac_bus *bus) 433 { 434 /* enable controller CIE and GIE */ 435 snd_hdac_chip_updatel(bus, INTCTL, 436 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 437 AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN); 438 } 439 440 /* disable interrupts */ 441 static void azx_int_disable(struct hdac_bus *bus) 442 { 443 struct hdac_stream *azx_dev; 444 445 /* disable interrupts in stream descriptor */ 446 list_for_each_entry(azx_dev, &bus->stream_list, list) 447 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0); 448 449 /* disable SIE for all streams */ 450 snd_hdac_chip_writeb(bus, INTCTL, 0); 451 452 /* disable controller CIE and GIE */ 453 snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0); 454 } 455 456 /* clear interrupts */ 457 static void azx_int_clear(struct hdac_bus *bus) 458 { 459 struct hdac_stream *azx_dev; 460 461 /* clear stream status */ 462 list_for_each_entry(azx_dev, &bus->stream_list, list) 463 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); 464 465 /* clear STATESTS */ 466 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK); 467 468 /* clear rirb status */ 469 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK); 470 471 /* clear int status */ 472 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM); 473 } 474 475 /** 476 * snd_hdac_bus_init_chip - reset and start the controller registers 477 * @bus: HD-audio core bus 478 * @full_reset: Do full reset 479 */ 480 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset) 481 { 482 if (bus->chip_init) 483 return false; 484 485 /* reset controller */ 486 snd_hdac_bus_reset_link(bus, full_reset); 487 488 /* clear interrupts */ 489 azx_int_clear(bus); 490 491 /* initialize the codec command I/O */ 492 snd_hdac_bus_init_cmd_io(bus); 493 494 /* enable interrupts after CORB/RIRB buffers are initialized above */ 495 azx_int_enable(bus); 496 497 /* program the position buffer */ 498 if (bus->use_posbuf && bus->posbuf.addr) { 499 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr); 500 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr)); 501 } 502 503 bus->chip_init = true; 504 return true; 505 } 506 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip); 507 508 /** 509 * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os 510 * @bus: HD-audio core bus 511 */ 512 void snd_hdac_bus_stop_chip(struct hdac_bus *bus) 513 { 514 if (!bus->chip_init) 515 return; 516 517 /* disable interrupts */ 518 azx_int_disable(bus); 519 azx_int_clear(bus); 520 521 /* disable CORB/RIRB */ 522 snd_hdac_bus_stop_cmd_io(bus); 523 524 /* disable position buffer */ 525 if (bus->posbuf.addr) { 526 snd_hdac_chip_writel(bus, DPLBASE, 0); 527 snd_hdac_chip_writel(bus, DPUBASE, 0); 528 } 529 530 bus->chip_init = false; 531 } 532 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip); 533 534 /** 535 * snd_hdac_bus_handle_stream_irq - interrupt handler for streams 536 * @bus: HD-audio core bus 537 * @status: INTSTS register value 538 * @ask: callback to be called for woken streams 539 * 540 * Returns the bits of handled streams, or zero if no stream is handled. 541 */ 542 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, 543 void (*ack)(struct hdac_bus *, 544 struct hdac_stream *)) 545 { 546 struct hdac_stream *azx_dev; 547 u8 sd_status; 548 int handled = 0; 549 550 list_for_each_entry(azx_dev, &bus->stream_list, list) { 551 if (status & azx_dev->sd_int_sta_mask) { 552 sd_status = snd_hdac_stream_readb(azx_dev, SD_STS); 553 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); 554 handled |= 1 << azx_dev->index; 555 if (!azx_dev->substream || !azx_dev->running || 556 !(sd_status & SD_INT_COMPLETE)) 557 continue; 558 if (ack) 559 ack(bus, azx_dev); 560 } 561 } 562 return handled; 563 } 564 EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq); 565 566 /** 567 * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers 568 * @bus: HD-audio core bus 569 * 570 * Call this after assigning the all streams. 571 * Returns zero for success, or a negative error code. 572 */ 573 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus) 574 { 575 struct hdac_stream *s; 576 int num_streams = 0; 577 int err; 578 579 list_for_each_entry(s, &bus->stream_list, list) { 580 /* allocate memory for the BDL for each stream */ 581 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, 582 BDL_SIZE, &s->bdl); 583 num_streams++; 584 if (err < 0) 585 return -ENOMEM; 586 } 587 588 if (WARN_ON(!num_streams)) 589 return -EINVAL; 590 /* allocate memory for the position buffer */ 591 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, 592 num_streams * 8, &bus->posbuf); 593 if (err < 0) 594 return -ENOMEM; 595 list_for_each_entry(s, &bus->stream_list, list) 596 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8); 597 598 /* single page (at least 4096 bytes) must suffice for both ringbuffes */ 599 return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, 600 PAGE_SIZE, &bus->rb); 601 } 602 EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages); 603 604 /** 605 * snd_hdac_bus_free_stream_pages - release BDL and other buffers 606 * @bus: HD-audio core bus 607 */ 608 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus) 609 { 610 struct hdac_stream *s; 611 612 list_for_each_entry(s, &bus->stream_list, list) { 613 if (s->bdl.area) 614 bus->io_ops->dma_free_pages(bus, &s->bdl); 615 } 616 617 if (bus->rb.area) 618 bus->io_ops->dma_free_pages(bus, &bus->rb); 619 if (bus->posbuf.area) 620 bus->io_ops->dma_free_pages(bus, &bus->posbuf); 621 } 622 EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages); 623