1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clocksource.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <linux/mutex.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/reset.h> 22 #include <linux/slab.h> 23 #include <linux/time.h> 24 #include <linux/string.h> 25 #include <linux/pm_runtime.h> 26 27 #include <sound/core.h> 28 #include <sound/initval.h> 29 30 #include <sound/hda_codec.h> 31 #include "hda_controller.h" 32 33 /* Defines for Nvidia Tegra HDA support */ 34 #define HDA_BAR0 0x8000 35 36 #define HDA_CFG_CMD 0x1004 37 #define HDA_CFG_BAR0 0x1010 38 39 #define HDA_ENABLE_IO_SPACE (1 << 0) 40 #define HDA_ENABLE_MEM_SPACE (1 << 1) 41 #define HDA_ENABLE_BUS_MASTER (1 << 2) 42 #define HDA_ENABLE_SERR (1 << 8) 43 #define HDA_DISABLE_INTR (1 << 10) 44 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF 45 #define HDA_BAR0_FINAL_PROGRAM (1 << 14) 46 47 /* IPFS */ 48 #define HDA_IPFS_CONFIG 0x180 49 #define HDA_IPFS_EN_FPCI 0x1 50 51 #define HDA_IPFS_FPCI_BAR0 0x80 52 #define HDA_FPCI_BAR0_START 0x40 53 54 #define HDA_IPFS_INTR_MASK 0x188 55 #define HDA_IPFS_EN_INTR (1 << 16) 56 57 /* FPCI */ 58 #define FPCI_DBG_CFG_2 0x10F4 59 #define FPCI_GCAP_NSDO_SHIFT 18 60 #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT) 61 62 /* max number of SDs */ 63 #define NUM_CAPTURE_SD 1 64 #define NUM_PLAYBACK_SD 1 65 66 /* 67 * Tegra194 does not reflect correct number of SDO lines. Below macro 68 * is used to update the GCAP register to workaround the issue. 69 */ 70 #define TEGRA194_NUM_SDO_LINES 4 71 72 struct hda_tegra_soc { 73 bool has_hda2codec_2x_reset; 74 bool has_hda2hdmi; 75 bool has_hda2codec_2x; 76 bool input_stream; 77 bool always_on; 78 bool requires_init; 79 }; 80 81 struct hda_tegra { 82 struct azx chip; 83 struct device *dev; 84 struct reset_control_bulk_data resets[3]; 85 struct clk_bulk_data clocks[3]; 86 unsigned int nresets; 87 unsigned int nclocks; 88 void __iomem *regs; 89 struct work_struct probe_work; 90 const struct hda_tegra_soc *soc; 91 }; 92 93 #ifdef CONFIG_PM 94 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 95 module_param(power_save, bint, 0644); 96 MODULE_PARM_DESC(power_save, 97 "Automatic power-saving timeout (in seconds, 0 = disable)."); 98 #else 99 #define power_save 0 100 #endif 101 102 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */ 103 104 static void hda_tegra_init(struct hda_tegra *hda) 105 { 106 u32 v; 107 108 /* Enable PCI access */ 109 v = readl(hda->regs + HDA_IPFS_CONFIG); 110 v |= HDA_IPFS_EN_FPCI; 111 writel(v, hda->regs + HDA_IPFS_CONFIG); 112 113 /* Enable MEM/IO space and bus master */ 114 v = readl(hda->regs + HDA_CFG_CMD); 115 v &= ~HDA_DISABLE_INTR; 116 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | 117 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; 118 writel(v, hda->regs + HDA_CFG_CMD); 119 120 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); 121 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); 122 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); 123 124 v = readl(hda->regs + HDA_IPFS_INTR_MASK); 125 v |= HDA_IPFS_EN_INTR; 126 writel(v, hda->regs + HDA_IPFS_INTR_MASK); 127 } 128 129 /* 130 * power management 131 */ 132 static int hda_tegra_suspend(struct device *dev) 133 { 134 struct snd_card *card = dev_get_drvdata(dev); 135 int rc; 136 137 rc = pm_runtime_force_suspend(dev); 138 if (rc < 0) 139 return rc; 140 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 141 142 return 0; 143 } 144 145 static int hda_tegra_resume(struct device *dev) 146 { 147 struct snd_card *card = dev_get_drvdata(dev); 148 int rc; 149 150 rc = pm_runtime_force_resume(dev); 151 if (rc < 0) 152 return rc; 153 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 154 155 return 0; 156 } 157 158 static int hda_tegra_runtime_suspend(struct device *dev) 159 { 160 struct snd_card *card = dev_get_drvdata(dev); 161 struct azx *chip = card->private_data; 162 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 163 164 if (chip && chip->running) { 165 /* enable controller wake up event */ 166 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 167 STATESTS_INT_MASK); 168 169 azx_stop_chip(chip); 170 azx_enter_link_reset(chip); 171 } 172 clk_bulk_disable_unprepare(hda->nclocks, hda->clocks); 173 174 return 0; 175 } 176 177 static int hda_tegra_runtime_resume(struct device *dev) 178 { 179 struct snd_card *card = dev_get_drvdata(dev); 180 struct azx *chip = card->private_data; 181 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 182 int rc; 183 184 if (!chip->running) { 185 rc = reset_control_bulk_assert(hda->nresets, hda->resets); 186 if (rc) 187 return rc; 188 } 189 190 rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks); 191 if (rc != 0) 192 return rc; 193 if (chip->running) { 194 if (hda->soc->requires_init) 195 hda_tegra_init(hda); 196 197 azx_init_chip(chip, 1); 198 /* disable controller wake up event*/ 199 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 200 ~STATESTS_INT_MASK); 201 } else { 202 usleep_range(10, 100); 203 204 rc = reset_control_bulk_deassert(hda->nresets, hda->resets); 205 if (rc) 206 return rc; 207 } 208 209 return 0; 210 } 211 212 static const struct dev_pm_ops hda_tegra_pm = { 213 SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) 214 RUNTIME_PM_OPS(hda_tegra_runtime_suspend, hda_tegra_runtime_resume, NULL) 215 }; 216 217 static int hda_tegra_dev_disconnect(struct snd_device *device) 218 { 219 struct azx *chip = device->device_data; 220 221 chip->bus.shutdown = 1; 222 return 0; 223 } 224 225 /* 226 * destructor 227 */ 228 static int hda_tegra_dev_free(struct snd_device *device) 229 { 230 struct azx *chip = device->device_data; 231 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 232 233 cancel_work_sync(&hda->probe_work); 234 if (azx_bus(chip)->chip_init) { 235 azx_stop_all_streams(chip); 236 azx_stop_chip(chip); 237 } 238 239 azx_free_stream_pages(chip); 240 azx_free_streams(chip); 241 snd_hdac_bus_exit(azx_bus(chip)); 242 243 return 0; 244 } 245 246 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) 247 { 248 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 249 struct hdac_bus *bus = azx_bus(chip); 250 struct resource *res; 251 252 hda->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 253 if (IS_ERR(hda->regs)) 254 return PTR_ERR(hda->regs); 255 256 bus->remap_addr = hda->regs + HDA_BAR0; 257 bus->addr = res->start + HDA_BAR0; 258 259 if (hda->soc->requires_init) 260 hda_tegra_init(hda); 261 262 return 0; 263 } 264 265 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) 266 { 267 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 268 struct hdac_bus *bus = azx_bus(chip); 269 struct snd_card *card = chip->card; 270 int err; 271 unsigned short gcap; 272 int irq_id = platform_get_irq(pdev, 0); 273 const char *sname, *drv_name = "tegra-hda"; 274 struct device_node *np = pdev->dev.of_node; 275 276 if (irq_id < 0) 277 return irq_id; 278 279 err = hda_tegra_init_chip(chip, pdev); 280 if (err) 281 return err; 282 283 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, 284 IRQF_SHARED, KBUILD_MODNAME, chip); 285 if (err) { 286 dev_err(chip->card->dev, 287 "unable to request IRQ %d, disabling device\n", 288 irq_id); 289 return err; 290 } 291 bus->irq = irq_id; 292 bus->dma_stop_delay = 100; 293 card->sync_irq = bus->irq; 294 295 /* 296 * Tegra194 has 4 SDO lines and the STRIPE can be used to 297 * indicate how many of the SDO lines the stream should be 298 * striped. But GCAP register does not reflect the true 299 * capability of HW. Below workaround helps to fix this. 300 * 301 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2, 302 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines. 303 */ 304 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) { 305 u32 val; 306 307 dev_info(card->dev, "Override SDO lines to %u\n", 308 TEGRA194_NUM_SDO_LINES); 309 310 val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK; 311 val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT; 312 writel(val, hda->regs + FPCI_DBG_CFG_2); 313 } 314 315 gcap = azx_readw(chip, GCAP); 316 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 317 318 chip->align_buffer_size = 1; 319 320 /* read number of streams from GCAP register instead of using 321 * hardcoded value 322 */ 323 chip->capture_streams = (gcap >> 8) & 0x0f; 324 325 /* The GCAP register on Tegra234 implies no Input Streams(ISS) support, 326 * but the HW output stream descriptor programming should start with 327 * offset 0x20*4 from base stream descriptor address. This will be a 328 * problem while calculating the offset for output stream descriptor 329 * which will be considering input stream also. So here output stream 330 * starts with offset 0 which is wrong as HW register for output stream 331 * offset starts with 4. 332 */ 333 if (!hda->soc->input_stream) 334 chip->capture_streams = 4; 335 336 chip->playback_streams = (gcap >> 12) & 0x0f; 337 if (!chip->playback_streams && !chip->capture_streams) { 338 /* gcap didn't give any info, switching to old method */ 339 chip->playback_streams = NUM_PLAYBACK_SD; 340 chip->capture_streams = NUM_CAPTURE_SD; 341 } 342 chip->capture_index_offset = 0; 343 chip->playback_index_offset = chip->capture_streams; 344 chip->num_streams = chip->playback_streams + chip->capture_streams; 345 346 /* initialize streams */ 347 err = azx_init_streams(chip); 348 if (err < 0) { 349 dev_err(card->dev, "failed to initialize streams: %d\n", err); 350 return err; 351 } 352 353 err = azx_alloc_stream_pages(chip); 354 if (err < 0) { 355 dev_err(card->dev, "failed to allocate stream pages: %d\n", 356 err); 357 return err; 358 } 359 360 /* initialize chip */ 361 azx_init_chip(chip, 1); 362 363 /* 364 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with 365 * 4 SDO lines due to legacy design limitation. Following 366 * is, from HD Audio Specification (Revision 1.0a), used to 367 * control striping of the stream across multiple SDO lines 368 * for sample rates <= 48K. 369 * 370 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 } 371 * 372 * Due to legacy design issue it is recommended that above 373 * ratio must be greater than 8. Since number of SDO lines is 374 * in powers of 2, next available ratio is 16 which can be 375 * used as a limiting factor here. 376 */ 377 if (of_device_is_compatible(np, "nvidia,tegra30-hda") || 378 of_device_is_compatible(np, "nvidia,tegra194-hda")) 379 chip->bus.core.sdo_limit = 16; 380 381 /* codec detection */ 382 if (!bus->codec_mask) { 383 dev_err(card->dev, "no codecs found!\n"); 384 return -ENODEV; 385 } 386 387 /* driver name */ 388 strscpy(card->driver, drv_name); 389 /* shortname for card */ 390 sname = of_get_property(np, "nvidia,model", NULL); 391 if (!sname) 392 sname = drv_name; 393 if (strlen(sname) > sizeof(card->shortname)) 394 dev_info(card->dev, "truncating shortname for card\n"); 395 strscpy(card->shortname, sname); 396 397 /* longname for card */ 398 snprintf(card->longname, sizeof(card->longname), 399 "%s at 0x%lx irq %i", 400 card->shortname, bus->addr, bus->irq); 401 402 return 0; 403 } 404 405 /* 406 * constructor 407 */ 408 409 static void hda_tegra_probe_work(struct work_struct *work); 410 411 static int hda_tegra_create(struct snd_card *card, 412 unsigned int driver_caps, 413 struct hda_tegra *hda) 414 { 415 static const struct snd_device_ops ops = { 416 .dev_disconnect = hda_tegra_dev_disconnect, 417 .dev_free = hda_tegra_dev_free, 418 }; 419 struct azx *chip; 420 int err; 421 422 chip = &hda->chip; 423 424 mutex_init(&chip->open_mutex); 425 chip->card = card; 426 chip->ops = &hda_tegra_ops; 427 chip->driver_caps = driver_caps; 428 chip->driver_type = driver_caps & 0xff; 429 chip->dev_index = 0; 430 INIT_LIST_HEAD(&chip->pcm_list); 431 432 chip->codec_probe_mask = -1; 433 434 chip->single_cmd = false; 435 chip->snoop = true; 436 437 INIT_WORK(&hda->probe_work, hda_tegra_probe_work); 438 439 err = azx_bus_init(chip, NULL); 440 if (err < 0) 441 return err; 442 443 chip->bus.core.sync_write = 0; 444 chip->bus.core.needs_damn_long_delay = 1; 445 chip->bus.core.aligned_mmio = 1; 446 447 /* 448 * HDA power domain and clocks are always on for Tegra264 and 449 * the jack detection logic would work always, so no need of 450 * jack polling mechanism running. 451 */ 452 if (!hda->soc->always_on) { 453 chip->jackpoll_interval = msecs_to_jiffies(5000); 454 chip->bus.jackpoll_in_suspend = 1; 455 } 456 457 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 458 if (err < 0) { 459 dev_err(card->dev, "Error creating device\n"); 460 return err; 461 } 462 463 return 0; 464 } 465 466 static const struct hda_tegra_soc tegra30_data = { 467 .has_hda2codec_2x_reset = true, 468 .has_hda2hdmi = true, 469 .has_hda2codec_2x = true, 470 .input_stream = true, 471 .always_on = false, 472 .requires_init = true, 473 }; 474 475 static const struct hda_tegra_soc tegra194_data = { 476 .has_hda2codec_2x_reset = false, 477 .has_hda2hdmi = true, 478 .has_hda2codec_2x = true, 479 .input_stream = true, 480 .always_on = false, 481 .requires_init = true, 482 }; 483 484 static const struct hda_tegra_soc tegra234_data = { 485 .has_hda2codec_2x_reset = true, 486 .has_hda2hdmi = false, 487 .has_hda2codec_2x = true, 488 .input_stream = false, 489 .always_on = false, 490 .requires_init = true, 491 }; 492 493 static const struct hda_tegra_soc tegra264_data = { 494 .has_hda2codec_2x_reset = true, 495 .has_hda2hdmi = false, 496 .has_hda2codec_2x = false, 497 .input_stream = false, 498 .always_on = true, 499 .requires_init = false, 500 }; 501 502 static const struct of_device_id hda_tegra_match[] = { 503 { .compatible = "nvidia,tegra30-hda", .data = &tegra30_data }, 504 { .compatible = "nvidia,tegra194-hda", .data = &tegra194_data }, 505 { .compatible = "nvidia,tegra234-hda", .data = &tegra234_data }, 506 { .compatible = "nvidia,tegra264-hda", .data = &tegra264_data }, 507 {}, 508 }; 509 MODULE_DEVICE_TABLE(of, hda_tegra_match); 510 511 static int hda_tegra_probe(struct platform_device *pdev) 512 { 513 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR | 514 AZX_DCAPS_PM_RUNTIME | 515 AZX_DCAPS_4K_BDLE_BOUNDARY; 516 struct snd_card *card; 517 struct azx *chip; 518 struct hda_tegra *hda; 519 int err; 520 521 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); 522 if (!hda) 523 return -ENOMEM; 524 hda->dev = &pdev->dev; 525 chip = &hda->chip; 526 527 hda->soc = of_device_get_match_data(&pdev->dev); 528 529 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 530 THIS_MODULE, 0, &card); 531 if (err < 0) { 532 dev_err(&pdev->dev, "Error creating card!\n"); 533 return err; 534 } 535 536 hda->resets[hda->nresets++].id = "hda"; 537 538 /* 539 * "hda2hdmi" is not applicable for Tegra234. This is because the 540 * codec is separate IP and not under display SOR partition now. 541 */ 542 if (hda->soc->has_hda2hdmi) 543 hda->resets[hda->nresets++].id = "hda2hdmi"; 544 545 /* 546 * "hda2codec_2x" reset is not present on Tegra194. Though DT would 547 * be updated to reflect this, but to have backward compatibility 548 * below is necessary. 549 */ 550 if (hda->soc->has_hda2codec_2x_reset) 551 hda->resets[hda->nresets++].id = "hda2codec_2x"; 552 553 err = devm_reset_control_bulk_get_exclusive(&pdev->dev, hda->nresets, 554 hda->resets); 555 if (err) 556 goto out_free; 557 558 hda->clocks[hda->nclocks++].id = "hda"; 559 if (hda->soc->has_hda2hdmi) 560 hda->clocks[hda->nclocks++].id = "hda2hdmi"; 561 562 if (hda->soc->has_hda2codec_2x) 563 hda->clocks[hda->nclocks++].id = "hda2codec_2x"; 564 565 err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks); 566 if (err < 0) 567 goto out_free; 568 569 err = hda_tegra_create(card, driver_flags, hda); 570 if (err < 0) 571 goto out_free; 572 card->private_data = chip; 573 574 dev_set_drvdata(&pdev->dev, card); 575 576 pm_runtime_enable(hda->dev); 577 if (!azx_has_pm_runtime(chip)) 578 pm_runtime_forbid(hda->dev); 579 580 schedule_work(&hda->probe_work); 581 582 return 0; 583 584 out_free: 585 snd_card_free(card); 586 return err; 587 } 588 589 static void hda_tegra_probe_work(struct work_struct *work) 590 { 591 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work); 592 struct azx *chip = &hda->chip; 593 struct platform_device *pdev = to_platform_device(hda->dev); 594 int err; 595 596 guard(pm_runtime_active)(hda->dev); 597 err = hda_tegra_first_init(chip, pdev); 598 if (err < 0) 599 return; 600 601 /* create codec instances */ 602 err = azx_probe_codecs(chip, 8); 603 if (err < 0) 604 return; 605 606 err = azx_codec_configure(chip); 607 if (err < 0) 608 return; 609 610 err = snd_card_register(chip->card); 611 if (err < 0) 612 return; 613 614 chip->running = 1; 615 snd_hda_set_power_save(&chip->bus, power_save * 1000); 616 } 617 618 static void hda_tegra_remove(struct platform_device *pdev) 619 { 620 snd_card_free(dev_get_drvdata(&pdev->dev)); 621 pm_runtime_disable(&pdev->dev); 622 } 623 624 static void hda_tegra_shutdown(struct platform_device *pdev) 625 { 626 struct snd_card *card = dev_get_drvdata(&pdev->dev); 627 struct azx *chip; 628 629 if (!card) 630 return; 631 chip = card->private_data; 632 if (chip && chip->running) 633 azx_stop_chip(chip); 634 } 635 636 static struct platform_driver tegra_platform_hda = { 637 .driver = { 638 .name = "tegra-hda", 639 .pm = pm_ptr(&hda_tegra_pm), 640 .of_match_table = hda_tegra_match, 641 }, 642 .probe = hda_tegra_probe, 643 .remove = hda_tegra_remove, 644 .shutdown = hda_tegra_shutdown, 645 }; 646 module_platform_driver(tegra_platform_hda); 647 648 MODULE_DESCRIPTION("Tegra HDA bus driver"); 649 MODULE_LICENSE("GPL v2"); 650