1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 #include <linux/pgtable.h> 40 #include <linux/dmi.h> 41 42 #ifdef CONFIG_X86 43 /* for snoop control */ 44 #include <asm/set_memory.h> 45 #include <asm/cpufeature.h> 46 #endif 47 #include <sound/core.h> 48 #include <sound/initval.h> 49 #include <sound/hdaudio.h> 50 #include <sound/hda_i915.h> 51 #include <sound/intel-dsp-config.h> 52 #include <linux/vgaarb.h> 53 #include <linux/vga_switcheroo.h> 54 #include <linux/apple-gmux.h> 55 #include <linux/firmware.h> 56 #include <sound/hda_codec.h> 57 #include "intel.h" 58 59 #define CREATE_TRACE_POINTS 60 #include "intel_trace.h" 61 62 /* position fix mode */ 63 enum { 64 POS_FIX_AUTO, 65 POS_FIX_LPIB, 66 POS_FIX_POSBUF, 67 POS_FIX_VIACOMBO, 68 POS_FIX_COMBO, 69 POS_FIX_SKL, 70 POS_FIX_FIFO, 71 }; 72 73 /* Defines for ATI HD Audio support in SB450 south bridge */ 74 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 75 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 76 77 /* Defines for Nvidia HDA support */ 78 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 79 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 80 #define NVIDIA_HDA_ISTRM_COH 0x4d 81 #define NVIDIA_HDA_OSTRM_COH 0x4c 82 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 83 84 /* Defines for Intel SCH HDA snoop control */ 85 #define INTEL_HDA_CGCTL 0x48 86 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 87 #define INTEL_SCH_HDA_DEVC 0x78 88 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 89 90 /* max number of SDs */ 91 /* ICH, ATI and VIA have 4 playback and 4 capture */ 92 #define ICH6_NUM_CAPTURE 4 93 #define ICH6_NUM_PLAYBACK 4 94 95 /* ULI has 6 playback and 5 capture */ 96 #define ULI_NUM_CAPTURE 5 97 #define ULI_NUM_PLAYBACK 6 98 99 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 100 #define ATIHDMI_NUM_CAPTURE 0 101 #define ATIHDMI_NUM_PLAYBACK 8 102 103 104 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 105 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 106 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 107 static char *model[SNDRV_CARDS]; 108 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 109 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 110 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 111 static int probe_only[SNDRV_CARDS]; 112 static int jackpoll_ms[SNDRV_CARDS]; 113 static int single_cmd = -1; 114 static int enable_msi = -1; 115 #ifdef CONFIG_SND_HDA_PATCH_LOADER 116 static char *patch[SNDRV_CARDS]; 117 #endif 118 #ifdef CONFIG_SND_HDA_INPUT_BEEP 119 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 120 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 121 #endif 122 static bool dmic_detect = 1; 123 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0; 124 125 module_param_array(index, int, NULL, 0444); 126 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 127 module_param_array(id, charp, NULL, 0444); 128 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 129 module_param_array(enable, bool, NULL, 0444); 130 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 131 module_param_array(model, charp, NULL, 0444); 132 MODULE_PARM_DESC(model, "Use the given board model."); 133 module_param_array(position_fix, int, NULL, 0444); 134 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 135 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 136 module_param_array(bdl_pos_adj, int, NULL, 0644); 137 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 138 module_param_array(probe_mask, int, NULL, 0444); 139 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 140 module_param_array(probe_only, int, NULL, 0444); 141 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 142 module_param_array(jackpoll_ms, int, NULL, 0444); 143 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 144 module_param(single_cmd, bint, 0444); 145 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 146 "(for debugging only)."); 147 module_param(enable_msi, bint, 0444); 148 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 149 #ifdef CONFIG_SND_HDA_PATCH_LOADER 150 module_param_array(patch, charp, NULL, 0444); 151 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 152 #endif 153 #ifdef CONFIG_SND_HDA_INPUT_BEEP 154 module_param_array(beep_mode, bool, NULL, 0444); 155 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 156 "(0=off, 1=on) (default=1)."); 157 #endif 158 module_param(dmic_detect, bool, 0444); 159 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 160 "(0=off, 1=on) (default=1); " 161 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 162 module_param(ctl_dev_id, bool, 0444); 163 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address)."); 164 165 #ifdef CONFIG_PM 166 static int param_set_xint(const char *val, const struct kernel_param *kp); 167 static const struct kernel_param_ops param_ops_xint = { 168 .set = param_set_xint, 169 .get = param_get_int, 170 }; 171 #define param_check_xint param_check_int 172 173 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 174 module_param(power_save, xint, 0644); 175 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 176 "(in second, 0 = disable)."); 177 178 static int pm_blacklist = -1; 179 module_param(pm_blacklist, bint, 0644); 180 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); 181 182 /* reset the HD-audio controller in power save mode. 183 * this may give more power-saving, but will take longer time to 184 * wake up. 185 */ 186 static bool power_save_controller = 1; 187 module_param(power_save_controller, bool, 0644); 188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 189 #else /* CONFIG_PM */ 190 #define power_save 0 191 #define pm_blacklist 0 192 #define power_save_controller false 193 #endif /* CONFIG_PM */ 194 195 static int align_buffer_size = -1; 196 module_param(align_buffer_size, bint, 0644); 197 MODULE_PARM_DESC(align_buffer_size, 198 "Force buffer and period sizes to be multiple of 128 bytes."); 199 200 #ifdef CONFIG_X86 201 static int hda_snoop = -1; 202 module_param_named(snoop, hda_snoop, bint, 0444); 203 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 204 #else 205 #define hda_snoop true 206 #endif 207 208 209 MODULE_LICENSE("GPL"); 210 MODULE_DESCRIPTION("Intel HDA driver"); 211 212 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 213 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 214 #define SUPPORT_VGA_SWITCHEROO 215 #endif 216 #endif 217 218 219 /* 220 */ 221 222 /* driver types */ 223 enum { 224 AZX_DRIVER_ICH, 225 AZX_DRIVER_PCH, 226 AZX_DRIVER_SCH, 227 AZX_DRIVER_SKL, 228 AZX_DRIVER_HDMI, 229 AZX_DRIVER_ATI, 230 AZX_DRIVER_ATIHDMI, 231 AZX_DRIVER_ATIHDMI_NS, 232 AZX_DRIVER_GFHDMI, 233 AZX_DRIVER_VIA, 234 AZX_DRIVER_SIS, 235 AZX_DRIVER_ULI, 236 AZX_DRIVER_NVIDIA, 237 AZX_DRIVER_TERA, 238 AZX_DRIVER_CTX, 239 AZX_DRIVER_CTHDA, 240 AZX_DRIVER_CMEDIA, 241 AZX_DRIVER_ZHAOXIN, 242 AZX_DRIVER_ZHAOXINHDMI, 243 AZX_DRIVER_LOONGSON, 244 AZX_DRIVER_GENERIC, 245 AZX_NUM_DRIVERS, /* keep this as last entry */ 246 }; 247 248 #define azx_get_snoop_type(chip) \ 249 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 250 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 251 252 /* quirks for old Intel chipsets */ 253 #define AZX_DCAPS_INTEL_ICH \ 254 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 255 256 /* quirks for Intel PCH */ 257 #define AZX_DCAPS_INTEL_PCH_BASE \ 258 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 259 AZX_DCAPS_SNOOP_TYPE(SCH)) 260 261 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 262 #define AZX_DCAPS_INTEL_PCH_NOPM \ 263 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 264 265 /* PCH for HSW/BDW; with runtime PM */ 266 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 267 #define AZX_DCAPS_INTEL_PCH \ 268 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 269 270 /* HSW HDMI */ 271 #define AZX_DCAPS_INTEL_HASWELL \ 272 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 273 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 274 AZX_DCAPS_SNOOP_TYPE(SCH)) 275 276 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 277 #define AZX_DCAPS_INTEL_BROADWELL \ 278 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 279 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 280 AZX_DCAPS_SNOOP_TYPE(SCH)) 281 282 #define AZX_DCAPS_INTEL_BAYTRAIL \ 283 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 284 285 #define AZX_DCAPS_INTEL_BRASWELL \ 286 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 287 AZX_DCAPS_I915_COMPONENT) 288 289 #define AZX_DCAPS_INTEL_SKYLAKE \ 290 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 291 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 292 293 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 294 295 #define AZX_DCAPS_INTEL_LNL \ 296 (AZX_DCAPS_INTEL_SKYLAKE | AZX_DCAPS_PIO_COMMANDS) 297 298 /* quirks for ATI SB / AMD Hudson */ 299 #define AZX_DCAPS_PRESET_ATI_SB \ 300 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ 301 AZX_DCAPS_SNOOP_TYPE(ATI)) 302 303 /* quirks for ATI/AMD HDMI */ 304 #define AZX_DCAPS_PRESET_ATI_HDMI \ 305 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ 306 AZX_DCAPS_NO_MSI64) 307 308 /* quirks for ATI HDMI with snoop off */ 309 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 310 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 311 312 /* quirks for AMD SB */ 313 #define AZX_DCAPS_PRESET_AMD_SB \ 314 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ 315 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\ 316 AZX_DCAPS_RETRY_PROBE) 317 318 /* quirks for Nvidia */ 319 #define AZX_DCAPS_PRESET_NVIDIA \ 320 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 321 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 322 323 #define AZX_DCAPS_PRESET_CTHDA \ 324 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 325 AZX_DCAPS_NO_64BIT |\ 326 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 327 328 /* 329 * vga_switcheroo support 330 */ 331 #ifdef SUPPORT_VGA_SWITCHEROO 332 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 333 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 334 #else 335 #define use_vga_switcheroo(chip) 0 336 #define needs_eld_notify_link(chip) false 337 #endif 338 339 static const char * const driver_short_names[] = { 340 [AZX_DRIVER_ICH] = "HDA Intel", 341 [AZX_DRIVER_PCH] = "HDA Intel PCH", 342 [AZX_DRIVER_SCH] = "HDA Intel MID", 343 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 344 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 345 [AZX_DRIVER_ATI] = "HDA ATI SB", 346 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 347 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 348 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI", 349 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 350 [AZX_DRIVER_SIS] = "HDA SIS966", 351 [AZX_DRIVER_ULI] = "HDA ULI M5461", 352 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 353 [AZX_DRIVER_TERA] = "HDA Teradici", 354 [AZX_DRIVER_CTX] = "HDA Creative", 355 [AZX_DRIVER_CTHDA] = "HDA Creative", 356 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 357 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 358 [AZX_DRIVER_ZHAOXINHDMI] = "HDA Zhaoxin HDMI", 359 [AZX_DRIVER_LOONGSON] = "HDA Loongson", 360 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 361 }; 362 363 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 364 static void set_default_power_save(struct azx *chip); 365 366 /* 367 * initialize the PCI registers 368 */ 369 /* update bits in a PCI register byte */ 370 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 371 unsigned char mask, unsigned char val) 372 { 373 unsigned char data; 374 375 pci_read_config_byte(pci, reg, &data); 376 data &= ~mask; 377 data |= (val & mask); 378 pci_write_config_byte(pci, reg, data); 379 } 380 381 static void azx_init_pci(struct azx *chip) 382 { 383 int snoop_type = azx_get_snoop_type(chip); 384 385 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 386 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 387 * Ensuring these bits are 0 clears playback static on some HD Audio 388 * codecs. 389 * The PCI register TCSEL is defined in the Intel manuals. 390 */ 391 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 392 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 393 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 394 } 395 396 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 397 * we need to enable snoop. 398 */ 399 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 400 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 401 azx_snoop(chip)); 402 update_pci_byte(chip->pci, 403 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 404 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 405 } 406 407 /* For NVIDIA HDA, enable snoop */ 408 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 409 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 410 azx_snoop(chip)); 411 update_pci_byte(chip->pci, 412 NVIDIA_HDA_TRANSREG_ADDR, 413 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 414 update_pci_byte(chip->pci, 415 NVIDIA_HDA_ISTRM_COH, 416 0x01, NVIDIA_HDA_ENABLE_COHBIT); 417 update_pci_byte(chip->pci, 418 NVIDIA_HDA_OSTRM_COH, 419 0x01, NVIDIA_HDA_ENABLE_COHBIT); 420 } 421 422 /* Enable SCH/PCH snoop if needed */ 423 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 424 unsigned short snoop; 425 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 426 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 427 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 428 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 429 if (!azx_snoop(chip)) 430 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 431 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 432 pci_read_config_word(chip->pci, 433 INTEL_SCH_HDA_DEVC, &snoop); 434 } 435 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 436 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 437 "Disabled" : "Enabled"); 438 } 439 } 440 441 /* 442 * In BXT-P A0, HD-Audio DMA requests is later than expected, 443 * and makes an audio stream sensitive to system latencies when 444 * 24/32 bits are playing. 445 * Adjusting threshold of DMA fifo to force the DMA request 446 * sooner to improve latency tolerance at the expense of power. 447 */ 448 static void bxt_reduce_dma_latency(struct azx *chip) 449 { 450 u32 val; 451 452 val = azx_readl(chip, VS_EM4L); 453 val &= (0x3 << 20); 454 azx_writel(chip, VS_EM4L, val); 455 } 456 457 /* 458 * ML_LCAP bits: 459 * bit 0: 6 MHz Supported 460 * bit 1: 12 MHz Supported 461 * bit 2: 24 MHz Supported 462 * bit 3: 48 MHz Supported 463 * bit 4: 96 MHz Supported 464 * bit 5: 192 MHz Supported 465 */ 466 static int intel_get_lctl_scf(struct azx *chip) 467 { 468 struct hdac_bus *bus = azx_bus(chip); 469 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 470 u32 val, t; 471 int i; 472 473 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 474 475 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 476 t = preferred_bits[i]; 477 if (val & (1 << t)) 478 return t; 479 } 480 481 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 482 return 0; 483 } 484 485 static int intel_ml_lctl_set_power(struct azx *chip, int state) 486 { 487 struct hdac_bus *bus = azx_bus(chip); 488 u32 val; 489 int timeout; 490 491 /* 492 * Changes to LCTL.SCF are only needed for the first multi-link dealing 493 * with external codecs 494 */ 495 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 496 val &= ~AZX_ML_LCTL_SPA; 497 val |= state << AZX_ML_LCTL_SPA_SHIFT; 498 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 499 /* wait for CPA */ 500 timeout = 50; 501 while (timeout) { 502 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 503 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT)) 504 return 0; 505 timeout--; 506 udelay(10); 507 } 508 509 return -1; 510 } 511 512 static void intel_init_lctl(struct azx *chip) 513 { 514 struct hdac_bus *bus = azx_bus(chip); 515 u32 val; 516 int ret; 517 518 /* 0. check lctl register value is correct or not */ 519 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 520 /* only perform additional configurations if the SCF is initially based on 6MHz */ 521 if ((val & AZX_ML_LCTL_SCF) != 0) 522 return; 523 524 /* 525 * Before operating on SPA, CPA must match SPA. 526 * Any deviation may result in undefined behavior. 527 */ 528 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) != 529 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT)) 530 return; 531 532 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 533 ret = intel_ml_lctl_set_power(chip, 0); 534 udelay(100); 535 if (ret) 536 goto set_spa; 537 538 /* 2. update SCF to select an audio clock different from 6MHz */ 539 val &= ~AZX_ML_LCTL_SCF; 540 val |= intel_get_lctl_scf(chip); 541 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 542 543 set_spa: 544 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 545 intel_ml_lctl_set_power(chip, 1); 546 udelay(100); 547 } 548 549 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 550 { 551 struct hdac_bus *bus = azx_bus(chip); 552 struct pci_dev *pci = chip->pci; 553 u32 val; 554 555 snd_hdac_set_codec_wakeup(bus, true); 556 if (chip->driver_type == AZX_DRIVER_SKL) { 557 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 558 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 559 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 560 } 561 azx_init_chip(chip, full_reset); 562 if (chip->driver_type == AZX_DRIVER_SKL) { 563 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 564 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 565 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 566 } 567 568 snd_hdac_set_codec_wakeup(bus, false); 569 570 /* reduce dma latency to avoid noise */ 571 if (HDA_CONTROLLER_IS_APL(pci)) 572 bxt_reduce_dma_latency(chip); 573 574 if (bus->mlcap != NULL) 575 intel_init_lctl(chip); 576 } 577 578 /* calculate runtime delay from LPIB */ 579 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 580 unsigned int pos) 581 { 582 struct snd_pcm_substream *substream = azx_dev->core.substream; 583 int stream = substream->stream; 584 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 585 int delay; 586 587 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 588 delay = pos - lpib_pos; 589 else 590 delay = lpib_pos - pos; 591 if (delay < 0) { 592 if (delay >= azx_dev->core.delay_negative_threshold) 593 delay = 0; 594 else 595 delay += azx_dev->core.bufsize; 596 } 597 598 if (delay >= azx_dev->core.period_bytes) { 599 dev_info(chip->card->dev, 600 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 601 delay, azx_dev->core.period_bytes); 602 delay = 0; 603 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 604 chip->get_delay[stream] = NULL; 605 } 606 607 return bytes_to_frames(substream->runtime, delay); 608 } 609 610 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 611 612 /* called from IRQ */ 613 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 614 { 615 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 616 int ok; 617 618 ok = azx_position_ok(chip, azx_dev); 619 if (ok == 1) { 620 azx_dev->irq_pending = 0; 621 return ok; 622 } else if (ok == 0) { 623 /* bogus IRQ, process it later */ 624 azx_dev->irq_pending = 1; 625 schedule_work(&hda->irq_pending_work); 626 } 627 return 0; 628 } 629 630 #define display_power(chip, enable) \ 631 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 632 633 /* 634 * Check whether the current DMA position is acceptable for updating 635 * periods. Returns non-zero if it's OK. 636 * 637 * Many HD-audio controllers appear pretty inaccurate about 638 * the update-IRQ timing. The IRQ is issued before actually the 639 * data is processed. So, we need to process it afterwords in a 640 * workqueue. 641 * 642 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update 643 */ 644 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 645 { 646 struct snd_pcm_substream *substream = azx_dev->core.substream; 647 struct snd_pcm_runtime *runtime = substream->runtime; 648 int stream = substream->stream; 649 u32 wallclk; 650 unsigned int pos; 651 snd_pcm_uframes_t hwptr, target; 652 653 /* 654 * The value of the WALLCLK register is always 0 655 * on the Loongson controller, so we return directly. 656 */ 657 if (chip->driver_type == AZX_DRIVER_LOONGSON) 658 return 1; 659 660 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 661 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 662 return -1; /* bogus (too early) interrupt */ 663 664 if (chip->get_position[stream]) 665 pos = chip->get_position[stream](chip, azx_dev); 666 else { /* use the position buffer as default */ 667 pos = azx_get_pos_posbuf(chip, azx_dev); 668 if (!pos || pos == (u32)-1) { 669 dev_info(chip->card->dev, 670 "Invalid position buffer, using LPIB read method instead.\n"); 671 chip->get_position[stream] = azx_get_pos_lpib; 672 if (chip->get_position[0] == azx_get_pos_lpib && 673 chip->get_position[1] == azx_get_pos_lpib) 674 azx_bus(chip)->use_posbuf = false; 675 pos = azx_get_pos_lpib(chip, azx_dev); 676 chip->get_delay[stream] = NULL; 677 } else { 678 chip->get_position[stream] = azx_get_pos_posbuf; 679 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 680 chip->get_delay[stream] = azx_get_delay_from_lpib; 681 } 682 } 683 684 if (pos >= azx_dev->core.bufsize) 685 pos = 0; 686 687 if (WARN_ONCE(!azx_dev->core.period_bytes, 688 "hda-intel: zero azx_dev->period_bytes")) 689 return -1; /* this shouldn't happen! */ 690 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 691 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 692 /* NG - it's below the first next period boundary */ 693 return chip->bdl_pos_adj ? 0 : -1; 694 azx_dev->core.start_wallclk += wallclk; 695 696 if (azx_dev->core.no_period_wakeup) 697 return 1; /* OK, no need to check period boundary */ 698 699 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt) 700 return 1; /* OK, already in hwptr updating process */ 701 702 /* check whether the period gets really elapsed */ 703 pos = bytes_to_frames(runtime, pos); 704 hwptr = runtime->hw_ptr_base + pos; 705 if (hwptr < runtime->status->hw_ptr) 706 hwptr += runtime->buffer_size; 707 target = runtime->hw_ptr_interrupt + runtime->period_size; 708 if (hwptr < target) { 709 /* too early wakeup, process it later */ 710 return chip->bdl_pos_adj ? 0 : -1; 711 } 712 713 return 1; /* OK, it's fine */ 714 } 715 716 /* 717 * The work for pending PCM period updates. 718 */ 719 static void azx_irq_pending_work(struct work_struct *work) 720 { 721 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 722 struct azx *chip = &hda->chip; 723 struct hdac_bus *bus = azx_bus(chip); 724 struct hdac_stream *s; 725 int pending, ok; 726 727 if (!hda->irq_pending_warned) { 728 dev_info(chip->card->dev, 729 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 730 chip->card->number); 731 hda->irq_pending_warned = 1; 732 } 733 734 for (;;) { 735 pending = 0; 736 spin_lock_irq(&bus->reg_lock); 737 list_for_each_entry(s, &bus->stream_list, list) { 738 struct azx_dev *azx_dev = stream_to_azx_dev(s); 739 if (!azx_dev->irq_pending || 740 !s->substream || 741 !s->running) 742 continue; 743 ok = azx_position_ok(chip, azx_dev); 744 if (ok > 0) { 745 azx_dev->irq_pending = 0; 746 spin_unlock(&bus->reg_lock); 747 snd_pcm_period_elapsed(s->substream); 748 spin_lock(&bus->reg_lock); 749 } else if (ok < 0) { 750 pending = 0; /* too early */ 751 } else 752 pending++; 753 } 754 spin_unlock_irq(&bus->reg_lock); 755 if (!pending) 756 return; 757 msleep(1); 758 } 759 } 760 761 /* clear irq_pending flags and assure no on-going workq */ 762 static void azx_clear_irq_pending(struct azx *chip) 763 { 764 struct hdac_bus *bus = azx_bus(chip); 765 struct hdac_stream *s; 766 767 guard(spinlock_irq)(&bus->reg_lock); 768 list_for_each_entry(s, &bus->stream_list, list) { 769 struct azx_dev *azx_dev = stream_to_azx_dev(s); 770 azx_dev->irq_pending = 0; 771 } 772 } 773 774 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 775 { 776 struct hdac_bus *bus = azx_bus(chip); 777 int ret; 778 779 if (!chip->msi || pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_MSI) < 0) { 780 ret = pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_INTX); 781 if (ret < 0) 782 return ret; 783 chip->msi = 0; 784 } 785 786 if (request_irq(chip->pci->irq, azx_interrupt, 787 chip->msi ? 0 : IRQF_SHARED, 788 chip->card->irq_descr, chip)) { 789 dev_err(chip->card->dev, 790 "unable to grab IRQ %d, disabling device\n", 791 chip->pci->irq); 792 if (do_disconnect) 793 snd_card_disconnect(chip->card); 794 return -1; 795 } 796 bus->irq = chip->pci->irq; 797 chip->card->sync_irq = bus->irq; 798 return 0; 799 } 800 801 /* get the current DMA position with correction on VIA chips */ 802 static unsigned int azx_via_get_position(struct azx *chip, 803 struct azx_dev *azx_dev) 804 { 805 unsigned int link_pos, mini_pos, bound_pos; 806 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 807 unsigned int fifo_size; 808 809 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 810 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 811 /* Playback, no problem using link position */ 812 return link_pos; 813 } 814 815 /* Capture */ 816 /* For new chipset, 817 * use mod to get the DMA position just like old chipset 818 */ 819 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 820 mod_dma_pos %= azx_dev->core.period_bytes; 821 822 fifo_size = azx_stream(azx_dev)->fifo_size; 823 824 if (azx_dev->insufficient) { 825 /* Link position never gather than FIFO size */ 826 if (link_pos <= fifo_size) 827 return 0; 828 829 azx_dev->insufficient = 0; 830 } 831 832 if (link_pos <= fifo_size) 833 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 834 else 835 mini_pos = link_pos - fifo_size; 836 837 /* Find nearest previous boudary */ 838 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 839 mod_link_pos = link_pos % azx_dev->core.period_bytes; 840 if (mod_link_pos >= fifo_size) 841 bound_pos = link_pos - mod_link_pos; 842 else if (mod_dma_pos >= mod_mini_pos) 843 bound_pos = mini_pos - mod_mini_pos; 844 else { 845 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 846 if (bound_pos >= azx_dev->core.bufsize) 847 bound_pos = 0; 848 } 849 850 /* Calculate real DMA position we want */ 851 return bound_pos + mod_dma_pos; 852 } 853 854 #define AMD_FIFO_SIZE 32 855 856 /* get the current DMA position with FIFO size correction */ 857 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 858 { 859 struct snd_pcm_substream *substream = azx_dev->core.substream; 860 struct snd_pcm_runtime *runtime = substream->runtime; 861 unsigned int pos, delay; 862 863 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 864 if (!runtime) 865 return pos; 866 867 runtime->delay = AMD_FIFO_SIZE; 868 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 869 if (azx_dev->insufficient) { 870 if (pos < delay) { 871 delay = pos; 872 runtime->delay = bytes_to_frames(runtime, pos); 873 } else { 874 azx_dev->insufficient = 0; 875 } 876 } 877 878 /* correct the DMA position for capture stream */ 879 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 880 if (pos < delay) 881 pos += azx_dev->core.bufsize; 882 pos -= delay; 883 } 884 885 return pos; 886 } 887 888 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 889 unsigned int pos) 890 { 891 struct snd_pcm_substream *substream = azx_dev->core.substream; 892 893 /* just read back the calculated value in the above */ 894 return substream->runtime->delay; 895 } 896 897 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset) 898 { 899 azx_stop_chip(chip); 900 if (!skip_link_reset) 901 azx_enter_link_reset(chip); 902 azx_clear_irq_pending(chip); 903 display_power(chip, false); 904 } 905 906 static DEFINE_MUTEX(card_list_lock); 907 static LIST_HEAD(card_list); 908 909 static void azx_shutdown_chip(struct azx *chip) 910 { 911 __azx_shutdown_chip(chip, false); 912 } 913 914 static void azx_add_card_list(struct azx *chip) 915 { 916 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 917 918 guard(mutex)(&card_list_lock); 919 list_add(&hda->list, &card_list); 920 } 921 922 static void azx_del_card_list(struct azx *chip) 923 { 924 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 925 926 guard(mutex)(&card_list_lock); 927 list_del_init(&hda->list); 928 } 929 930 /* trigger power-save check at writing parameter */ 931 static int __maybe_unused param_set_xint(const char *val, const struct kernel_param *kp) 932 { 933 struct hda_intel *hda; 934 struct azx *chip; 935 int prev = power_save; 936 int ret = param_set_int(val, kp); 937 938 if (ret || prev == power_save) 939 return ret; 940 941 if (pm_blacklist > 0) 942 return 0; 943 944 guard(mutex)(&card_list_lock); 945 list_for_each_entry(hda, &card_list, list) { 946 chip = &hda->chip; 947 if (!hda->probe_continued || chip->disabled || 948 hda->runtime_pm_disabled) 949 continue; 950 snd_hda_set_power_save(&chip->bus, power_save * 1000); 951 } 952 return 0; 953 } 954 955 /* 956 * power management 957 */ 958 static bool azx_is_pm_ready(struct snd_card *card) 959 { 960 struct azx *chip; 961 struct hda_intel *hda; 962 963 if (!card) 964 return false; 965 chip = card->private_data; 966 hda = container_of(chip, struct hda_intel, chip); 967 if (chip->disabled || hda->init_failed || !chip->running) 968 return false; 969 return true; 970 } 971 972 static void __azx_runtime_resume(struct azx *chip) 973 { 974 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 975 struct hdac_bus *bus = azx_bus(chip); 976 struct hda_codec *codec; 977 int status; 978 979 display_power(chip, true); 980 if (hda->need_i915_power) 981 snd_hdac_i915_set_bclk(bus); 982 983 /* Read STATESTS before controller reset */ 984 status = azx_readw(chip, STATESTS); 985 986 azx_init_pci(chip); 987 hda_intel_init_chip(chip, true); 988 989 /* Avoid codec resume if runtime resume is for system suspend */ 990 if (!chip->pm_prepared) { 991 list_for_each_codec(codec, &chip->bus) { 992 if (codec->relaxed_resume) 993 continue; 994 995 if (codec->forced_resume || (status & (1 << codec->addr))) 996 pm_request_resume(hda_codec_dev(codec)); 997 } 998 } 999 1000 /* power down again for link-controlled chips */ 1001 if (!hda->need_i915_power) 1002 display_power(chip, false); 1003 } 1004 1005 static int azx_prepare(struct device *dev) 1006 { 1007 struct snd_card *card = dev_get_drvdata(dev); 1008 struct azx *chip; 1009 1010 if (!azx_is_pm_ready(card)) 1011 return 0; 1012 1013 chip = card->private_data; 1014 chip->pm_prepared = 1; 1015 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1016 1017 flush_work(&azx_bus(chip)->unsol_work); 1018 1019 /* HDA controller always requires different WAKEEN for runtime suspend 1020 * and system suspend, so don't use direct-complete here. 1021 */ 1022 return 0; 1023 } 1024 1025 static void azx_complete(struct device *dev) 1026 { 1027 struct snd_card *card = dev_get_drvdata(dev); 1028 struct azx *chip; 1029 1030 if (!azx_is_pm_ready(card)) 1031 return; 1032 1033 chip = card->private_data; 1034 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1035 chip->pm_prepared = 0; 1036 } 1037 1038 static int azx_suspend(struct device *dev) 1039 { 1040 struct snd_card *card = dev_get_drvdata(dev); 1041 struct azx *chip; 1042 1043 if (!azx_is_pm_ready(card)) 1044 return 0; 1045 1046 chip = card->private_data; 1047 azx_shutdown_chip(chip); 1048 1049 trace_azx_suspend(chip); 1050 return 0; 1051 } 1052 1053 static int azx_resume(struct device *dev) 1054 { 1055 struct snd_card *card = dev_get_drvdata(dev); 1056 struct azx *chip; 1057 1058 if (!azx_is_pm_ready(card)) 1059 return 0; 1060 1061 chip = card->private_data; 1062 1063 __azx_runtime_resume(chip); 1064 1065 trace_azx_resume(chip); 1066 return 0; 1067 } 1068 1069 /* put codec down to D3 at hibernation for Intel SKL+; 1070 * otherwise BIOS may still access the codec and screw up the driver 1071 */ 1072 static int azx_freeze_noirq(struct device *dev) 1073 { 1074 struct snd_card *card = dev_get_drvdata(dev); 1075 struct azx *chip = card->private_data; 1076 struct pci_dev *pci = to_pci_dev(dev); 1077 1078 if (!azx_is_pm_ready(card)) 1079 return 0; 1080 if (chip->driver_type == AZX_DRIVER_SKL) 1081 pci_set_power_state(pci, PCI_D3hot); 1082 1083 return 0; 1084 } 1085 1086 static int azx_thaw_noirq(struct device *dev) 1087 { 1088 struct snd_card *card = dev_get_drvdata(dev); 1089 struct azx *chip = card->private_data; 1090 struct pci_dev *pci = to_pci_dev(dev); 1091 1092 if (!azx_is_pm_ready(card)) 1093 return 0; 1094 if (chip->driver_type == AZX_DRIVER_SKL) 1095 pci_set_power_state(pci, PCI_D0); 1096 1097 return 0; 1098 } 1099 1100 static int azx_runtime_suspend(struct device *dev) 1101 { 1102 struct snd_card *card = dev_get_drvdata(dev); 1103 struct azx *chip; 1104 1105 if (!azx_is_pm_ready(card)) 1106 return 0; 1107 chip = card->private_data; 1108 1109 /* enable controller wake up event */ 1110 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); 1111 1112 azx_shutdown_chip(chip); 1113 trace_azx_runtime_suspend(chip); 1114 return 0; 1115 } 1116 1117 static int azx_runtime_resume(struct device *dev) 1118 { 1119 struct snd_card *card = dev_get_drvdata(dev); 1120 struct azx *chip; 1121 1122 if (!azx_is_pm_ready(card)) 1123 return 0; 1124 chip = card->private_data; 1125 __azx_runtime_resume(chip); 1126 1127 /* disable controller Wake Up event*/ 1128 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); 1129 1130 trace_azx_runtime_resume(chip); 1131 return 0; 1132 } 1133 1134 static int azx_runtime_idle(struct device *dev) 1135 { 1136 struct snd_card *card = dev_get_drvdata(dev); 1137 struct azx *chip; 1138 struct hda_intel *hda; 1139 1140 if (!card) 1141 return 0; 1142 1143 chip = card->private_data; 1144 hda = container_of(chip, struct hda_intel, chip); 1145 if (chip->disabled || hda->init_failed) 1146 return 0; 1147 1148 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1149 azx_bus(chip)->codec_powered || !chip->running) 1150 return -EBUSY; 1151 1152 /* ELD notification gets broken when HD-audio bus is off */ 1153 if (needs_eld_notify_link(chip)) 1154 return -EBUSY; 1155 1156 return 0; 1157 } 1158 1159 static const struct dev_pm_ops azx_pm = { 1160 SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1161 .prepare = pm_sleep_ptr(azx_prepare), 1162 .complete = pm_sleep_ptr(azx_complete), 1163 .freeze_noirq = pm_sleep_ptr(azx_freeze_noirq), 1164 .thaw_noirq = pm_sleep_ptr(azx_thaw_noirq), 1165 RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1166 }; 1167 1168 1169 static int azx_probe_continue(struct azx *chip); 1170 1171 #ifdef SUPPORT_VGA_SWITCHEROO 1172 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1173 1174 static void azx_vs_set_state(struct pci_dev *pci, 1175 enum vga_switcheroo_state state) 1176 { 1177 struct snd_card *card = pci_get_drvdata(pci); 1178 struct azx *chip = card->private_data; 1179 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1180 struct hda_codec *codec; 1181 bool disabled; 1182 1183 wait_for_completion(&hda->probe_wait); 1184 if (hda->init_failed) 1185 return; 1186 1187 disabled = (state == VGA_SWITCHEROO_OFF); 1188 if (chip->disabled == disabled) 1189 return; 1190 1191 if (!hda->probe_continued) { 1192 chip->disabled = disabled; 1193 if (!disabled) { 1194 dev_info(chip->card->dev, 1195 "Start delayed initialization\n"); 1196 if (azx_probe_continue(chip) < 0) 1197 dev_err(chip->card->dev, "initialization error\n"); 1198 } 1199 } else { 1200 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1201 disabled ? "Disabling" : "Enabling"); 1202 if (disabled) { 1203 list_for_each_codec(codec, &chip->bus) { 1204 pm_runtime_suspend(hda_codec_dev(codec)); 1205 pm_runtime_disable(hda_codec_dev(codec)); 1206 } 1207 pm_runtime_suspend(card->dev); 1208 pm_runtime_disable(card->dev); 1209 /* when we get suspended by vga_switcheroo we end up in D3cold, 1210 * however we have no ACPI handle, so pci/acpi can't put us there, 1211 * put ourselves there */ 1212 pci->current_state = PCI_D3cold; 1213 chip->disabled = true; 1214 if (snd_hda_lock_devices(&chip->bus)) 1215 dev_warn(chip->card->dev, 1216 "Cannot lock devices!\n"); 1217 } else { 1218 snd_hda_unlock_devices(&chip->bus); 1219 chip->disabled = false; 1220 pm_runtime_enable(card->dev); 1221 list_for_each_codec(codec, &chip->bus) { 1222 pm_runtime_enable(hda_codec_dev(codec)); 1223 pm_runtime_resume(hda_codec_dev(codec)); 1224 } 1225 } 1226 } 1227 } 1228 1229 static bool azx_vs_can_switch(struct pci_dev *pci) 1230 { 1231 struct snd_card *card = pci_get_drvdata(pci); 1232 struct azx *chip = card->private_data; 1233 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1234 1235 wait_for_completion(&hda->probe_wait); 1236 if (hda->init_failed) 1237 return false; 1238 if (chip->disabled || !hda->probe_continued) 1239 return true; 1240 if (snd_hda_lock_devices(&chip->bus)) 1241 return false; 1242 snd_hda_unlock_devices(&chip->bus); 1243 return true; 1244 } 1245 1246 /* 1247 * The discrete GPU cannot power down unless the HDA controller runtime 1248 * suspends, so activate runtime PM on codecs even if power_save == 0. 1249 */ 1250 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1251 { 1252 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1253 struct hda_codec *codec; 1254 1255 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1256 list_for_each_codec(codec, &chip->bus) 1257 codec->auto_runtime_pm = 1; 1258 /* reset the power save setup */ 1259 if (chip->running) 1260 set_default_power_save(chip); 1261 } 1262 } 1263 1264 static void azx_vs_gpu_bound(struct pci_dev *pci, 1265 enum vga_switcheroo_client_id client_id) 1266 { 1267 struct snd_card *card = pci_get_drvdata(pci); 1268 struct azx *chip = card->private_data; 1269 1270 if (client_id == VGA_SWITCHEROO_DIS) 1271 chip->bus.keep_power = 0; 1272 setup_vga_switcheroo_runtime_pm(chip); 1273 } 1274 1275 static void init_vga_switcheroo(struct azx *chip) 1276 { 1277 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1278 struct pci_dev *p = get_bound_vga(chip->pci); 1279 struct pci_dev *parent; 1280 if (p) { 1281 dev_info(chip->card->dev, 1282 "Handle vga_switcheroo audio client\n"); 1283 hda->use_vga_switcheroo = 1; 1284 1285 /* cleared in either gpu_bound op or codec probe, or when its 1286 * upstream port has _PR3 (i.e. dGPU). 1287 */ 1288 parent = pci_upstream_bridge(p); 1289 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1290 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1291 pci_dev_put(p); 1292 } 1293 } 1294 1295 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1296 .set_gpu_state = azx_vs_set_state, 1297 .can_switch = azx_vs_can_switch, 1298 .gpu_bound = azx_vs_gpu_bound, 1299 }; 1300 1301 static int register_vga_switcheroo(struct azx *chip) 1302 { 1303 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1304 struct pci_dev *p; 1305 int err; 1306 1307 if (!hda->use_vga_switcheroo) 1308 return 0; 1309 1310 p = get_bound_vga(chip->pci); 1311 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1312 pci_dev_put(p); 1313 1314 if (err < 0) 1315 return err; 1316 hda->vga_switcheroo_registered = 1; 1317 1318 return 0; 1319 } 1320 #else 1321 #define init_vga_switcheroo(chip) /* NOP */ 1322 #define register_vga_switcheroo(chip) 0 1323 #define check_hdmi_disabled(pci) false 1324 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1325 #endif /* SUPPORT_VGA_SWITCHER */ 1326 1327 /* 1328 * destructor 1329 */ 1330 static void azx_free(struct azx *chip) 1331 { 1332 struct pci_dev *pci = chip->pci; 1333 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1334 struct hdac_bus *bus = azx_bus(chip); 1335 1336 if (hda->freed) 1337 return; 1338 1339 if (azx_has_pm_runtime(chip) && chip->running) { 1340 pm_runtime_get_noresume(&pci->dev); 1341 pm_runtime_forbid(&pci->dev); 1342 pm_runtime_dont_use_autosuspend(&pci->dev); 1343 } 1344 1345 chip->running = 0; 1346 1347 azx_del_card_list(chip); 1348 1349 hda->init_failed = 1; /* to be sure */ 1350 complete_all(&hda->probe_wait); 1351 1352 if (use_vga_switcheroo(hda)) { 1353 if (chip->disabled && hda->probe_continued) 1354 snd_hda_unlock_devices(&chip->bus); 1355 if (hda->vga_switcheroo_registered) { 1356 vga_switcheroo_unregister_client(chip->pci); 1357 1358 /* Some GPUs don't have sound, and azx_first_init fails, 1359 * leaving the device probed but non-functional. As long 1360 * as it's probed, the PCI subsystem keeps its runtime 1361 * PM status as active. Force it to suspended (as we 1362 * actually stop the chip) to allow GPU to suspend via 1363 * vga_switcheroo, and print a warning. 1364 */ 1365 dev_warn(&pci->dev, "GPU sound probed, but not operational: please add a quirk to driver_denylist\n"); 1366 pm_runtime_disable(&pci->dev); 1367 pm_runtime_set_suspended(&pci->dev); 1368 pm_runtime_enable(&pci->dev); 1369 } 1370 } 1371 1372 if (bus->chip_init) { 1373 azx_clear_irq_pending(chip); 1374 azx_stop_all_streams(chip); 1375 azx_stop_chip(chip); 1376 } 1377 1378 if (bus->irq >= 0) 1379 free_irq(bus->irq, (void*)chip); 1380 1381 azx_free_stream_pages(chip); 1382 azx_free_streams(chip); 1383 snd_hdac_bus_exit(bus); 1384 1385 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1386 release_firmware(chip->fw); 1387 #endif 1388 display_power(chip, false); 1389 1390 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1391 snd_hdac_i915_exit(bus); 1392 1393 hda->freed = 1; 1394 } 1395 1396 static int azx_dev_disconnect(struct snd_device *device) 1397 { 1398 struct azx *chip = device->device_data; 1399 struct hdac_bus *bus = azx_bus(chip); 1400 1401 chip->bus.shutdown = 1; 1402 cancel_work_sync(&bus->unsol_work); 1403 1404 return 0; 1405 } 1406 1407 static int azx_dev_free(struct snd_device *device) 1408 { 1409 azx_free(device->device_data); 1410 return 0; 1411 } 1412 1413 #ifdef SUPPORT_VGA_SWITCHEROO 1414 #ifdef CONFIG_ACPI 1415 /* ATPX is in the integrated GPU's namespace */ 1416 static bool atpx_present(void) 1417 { 1418 struct pci_dev *pdev = NULL; 1419 acpi_handle dhandle, atpx_handle; 1420 acpi_status status; 1421 1422 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) { 1423 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) && 1424 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8)) 1425 continue; 1426 1427 dhandle = ACPI_HANDLE(&pdev->dev); 1428 if (dhandle) { 1429 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1430 if (ACPI_SUCCESS(status)) { 1431 pci_dev_put(pdev); 1432 return true; 1433 } 1434 } 1435 } 1436 return false; 1437 } 1438 #else 1439 static bool atpx_present(void) 1440 { 1441 return false; 1442 } 1443 #endif 1444 1445 /* 1446 * Check of disabled HDMI controller by vga_switcheroo 1447 */ 1448 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1449 { 1450 struct pci_dev *p; 1451 1452 /* check only discrete GPU */ 1453 switch (pci->vendor) { 1454 case PCI_VENDOR_ID_ATI: 1455 case PCI_VENDOR_ID_AMD: 1456 if (pci->devfn == 1) { 1457 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1458 pci->bus->number, 0); 1459 if (p) { 1460 /* ATPX is in the integrated GPU's ACPI namespace 1461 * rather than the dGPU's namespace. However, 1462 * the dGPU is the one who is involved in 1463 * vgaswitcheroo. 1464 */ 1465 if (pci_is_display(p) && 1466 (atpx_present() || apple_gmux_detect(NULL, NULL))) 1467 return p; 1468 pci_dev_put(p); 1469 } 1470 } 1471 break; 1472 case PCI_VENDOR_ID_NVIDIA: 1473 if (pci->devfn == 1) { 1474 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1475 pci->bus->number, 0); 1476 if (p) { 1477 if (pci_is_display(p)) 1478 return p; 1479 pci_dev_put(p); 1480 } 1481 } 1482 break; 1483 } 1484 return NULL; 1485 } 1486 1487 static bool check_hdmi_disabled(struct pci_dev *pci) 1488 { 1489 bool vga_inactive = false; 1490 struct pci_dev *p = get_bound_vga(pci); 1491 1492 if (p) { 1493 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1494 vga_inactive = true; 1495 pci_dev_put(p); 1496 } 1497 return vga_inactive; 1498 } 1499 #endif /* SUPPORT_VGA_SWITCHEROO */ 1500 1501 /* 1502 * allow/deny-listing for position_fix 1503 */ 1504 static const struct snd_pci_quirk position_fix_list[] = { 1505 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1506 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1507 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1508 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1509 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1510 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1511 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1512 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1513 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1514 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1515 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1516 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1517 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1518 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1519 {} 1520 }; 1521 1522 static int check_position_fix(struct azx *chip, int fix) 1523 { 1524 const struct snd_pci_quirk *q; 1525 1526 switch (fix) { 1527 case POS_FIX_AUTO: 1528 case POS_FIX_LPIB: 1529 case POS_FIX_POSBUF: 1530 case POS_FIX_VIACOMBO: 1531 case POS_FIX_COMBO: 1532 case POS_FIX_SKL: 1533 case POS_FIX_FIFO: 1534 return fix; 1535 } 1536 1537 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1538 if (q) { 1539 dev_info(chip->card->dev, 1540 "position_fix set to %d for device %04x:%04x\n", 1541 q->value, q->subvendor, q->subdevice); 1542 return q->value; 1543 } 1544 1545 /* Check VIA/ATI HD Audio Controller exist */ 1546 if (chip->driver_type == AZX_DRIVER_VIA) { 1547 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1548 return POS_FIX_VIACOMBO; 1549 } 1550 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1551 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1552 return POS_FIX_FIFO; 1553 } 1554 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1555 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1556 return POS_FIX_LPIB; 1557 } 1558 if (chip->driver_type == AZX_DRIVER_SKL) { 1559 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1560 return POS_FIX_SKL; 1561 } 1562 return POS_FIX_AUTO; 1563 } 1564 1565 static void assign_position_fix(struct azx *chip, int fix) 1566 { 1567 static const azx_get_pos_callback_t callbacks[] = { 1568 [POS_FIX_AUTO] = NULL, 1569 [POS_FIX_LPIB] = azx_get_pos_lpib, 1570 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1571 [POS_FIX_VIACOMBO] = azx_via_get_position, 1572 [POS_FIX_COMBO] = azx_get_pos_lpib, 1573 [POS_FIX_SKL] = azx_get_pos_posbuf, 1574 [POS_FIX_FIFO] = azx_get_pos_fifo, 1575 }; 1576 1577 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1578 1579 /* combo mode uses LPIB only for playback */ 1580 if (fix == POS_FIX_COMBO) 1581 chip->get_position[1] = NULL; 1582 1583 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1584 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1585 chip->get_delay[0] = chip->get_delay[1] = 1586 azx_get_delay_from_lpib; 1587 } 1588 1589 if (fix == POS_FIX_FIFO) 1590 chip->get_delay[0] = chip->get_delay[1] = 1591 azx_get_delay_from_fifo; 1592 } 1593 1594 /* 1595 * deny-lists for probe_mask 1596 */ 1597 static const struct snd_pci_quirk probe_mask_list[] = { 1598 /* Thinkpad often breaks the controller communication when accessing 1599 * to the non-working (or non-existing) modem codec slot. 1600 */ 1601 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1602 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1603 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1604 /* broken BIOS */ 1605 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1606 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1607 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1608 /* forced codec slots */ 1609 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1610 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1611 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105), 1612 /* WinFast VP200 H (Teradici) user reported broken communication */ 1613 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1614 {} 1615 }; 1616 1617 #define AZX_FORCE_CODEC_MASK 0x100 1618 1619 static void check_probe_mask(struct azx *chip, int dev) 1620 { 1621 const struct snd_pci_quirk *q; 1622 1623 chip->codec_probe_mask = probe_mask[dev]; 1624 if (chip->codec_probe_mask == -1) { 1625 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1626 if (q) { 1627 dev_info(chip->card->dev, 1628 "probe_mask set to 0x%x for device %04x:%04x\n", 1629 q->value, q->subvendor, q->subdevice); 1630 chip->codec_probe_mask = q->value; 1631 } 1632 } 1633 1634 /* check forced option */ 1635 if (chip->codec_probe_mask != -1 && 1636 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1637 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1638 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1639 (int)azx_bus(chip)->codec_mask); 1640 } 1641 } 1642 1643 /* 1644 * allow/deny-list for enable_msi 1645 */ 1646 static const struct snd_pci_quirk msi_deny_list[] = { 1647 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1648 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1649 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1650 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1651 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1652 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1653 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1654 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1655 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1656 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1657 {} 1658 }; 1659 1660 static void check_msi(struct azx *chip) 1661 { 1662 const struct snd_pci_quirk *q; 1663 1664 if (enable_msi >= 0) { 1665 chip->msi = !!enable_msi; 1666 return; 1667 } 1668 chip->msi = 1; /* enable MSI as default */ 1669 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); 1670 if (q) { 1671 dev_info(chip->card->dev, 1672 "msi for device %04x:%04x set to %d\n", 1673 q->subvendor, q->subdevice, q->value); 1674 chip->msi = q->value; 1675 return; 1676 } 1677 1678 /* NVidia chipsets seem to cause troubles with MSI */ 1679 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1680 dev_info(chip->card->dev, "Disabling MSI\n"); 1681 chip->msi = 0; 1682 } 1683 } 1684 1685 /* check the snoop mode availability */ 1686 static void azx_check_snoop_available(struct azx *chip) 1687 { 1688 int snoop = hda_snoop; 1689 1690 if (snoop >= 0) { 1691 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1692 snoop ? "snoop" : "non-snoop"); 1693 chip->snoop = snoop; 1694 chip->uc_buffer = !snoop; 1695 return; 1696 } 1697 1698 snoop = true; 1699 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1700 chip->driver_type == AZX_DRIVER_VIA) { 1701 /* force to non-snoop mode for a new VIA controller 1702 * when BIOS is set 1703 */ 1704 u8 val; 1705 pci_read_config_byte(chip->pci, 0x42, &val); 1706 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1707 chip->pci->revision == 0x20)) 1708 snoop = false; 1709 } 1710 1711 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1712 snoop = false; 1713 1714 chip->snoop = snoop; 1715 if (!snoop) { 1716 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1717 /* C-Media requires non-cached pages only for CORB/RIRB */ 1718 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1719 chip->uc_buffer = true; 1720 } 1721 } 1722 1723 static void azx_probe_work(struct work_struct *work) 1724 { 1725 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work); 1726 azx_probe_continue(&hda->chip); 1727 } 1728 1729 static int default_bdl_pos_adj(struct azx *chip) 1730 { 1731 /* some exceptions: Atoms seem problematic with value 1 */ 1732 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1733 switch (chip->pci->device) { 1734 case PCI_DEVICE_ID_INTEL_HDA_BYT: 1735 case PCI_DEVICE_ID_INTEL_HDA_BSW: 1736 return 32; 1737 case PCI_DEVICE_ID_INTEL_HDA_APL: 1738 return 64; 1739 } 1740 } 1741 1742 switch (chip->driver_type) { 1743 /* 1744 * increase the bdl size for Glenfly Gpus for hardware 1745 * limitation on hdac interrupt interval 1746 */ 1747 case AZX_DRIVER_GFHDMI: 1748 return 128; 1749 case AZX_DRIVER_ICH: 1750 case AZX_DRIVER_PCH: 1751 return 1; 1752 case AZX_DRIVER_ZHAOXINHDMI: 1753 return 128; 1754 default: 1755 return 32; 1756 } 1757 } 1758 1759 /* 1760 * constructor 1761 */ 1762 static const struct hda_controller_ops pci_hda_ops; 1763 1764 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1765 int dev, unsigned int driver_caps, 1766 struct azx **rchip) 1767 { 1768 static const struct snd_device_ops ops = { 1769 .dev_disconnect = azx_dev_disconnect, 1770 .dev_free = azx_dev_free, 1771 }; 1772 struct hda_intel *hda; 1773 struct azx *chip; 1774 int err; 1775 1776 *rchip = NULL; 1777 1778 err = pcim_enable_device(pci); 1779 if (err < 0) 1780 return err; 1781 1782 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1783 if (!hda) 1784 return -ENOMEM; 1785 1786 chip = &hda->chip; 1787 mutex_init(&chip->open_mutex); 1788 chip->card = card; 1789 chip->pci = pci; 1790 chip->ops = &pci_hda_ops; 1791 chip->driver_caps = driver_caps; 1792 chip->driver_type = driver_caps & 0xff; 1793 check_msi(chip); 1794 chip->dev_index = dev; 1795 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1796 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1797 INIT_LIST_HEAD(&chip->pcm_list); 1798 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1799 INIT_LIST_HEAD(&hda->list); 1800 init_vga_switcheroo(chip); 1801 init_completion(&hda->probe_wait); 1802 1803 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1804 1805 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1806 chip->fallback_to_single_cmd = 1; 1807 else /* explicitly set to single_cmd or not */ 1808 chip->single_cmd = single_cmd; 1809 1810 azx_check_snoop_available(chip); 1811 1812 if (bdl_pos_adj[dev] < 0) 1813 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1814 else 1815 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1816 1817 err = azx_bus_init(chip, model[dev]); 1818 if (err < 0) 1819 return err; 1820 1821 /* use the non-cached pages in non-snoop mode */ 1822 if (!azx_snoop(chip)) 1823 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC; 1824 1825 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1826 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1827 chip->bus.core.needs_damn_long_delay = 1; 1828 } 1829 1830 check_probe_mask(chip, dev); 1831 1832 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1833 if (err < 0) { 1834 dev_err(card->dev, "Error creating device [card]!\n"); 1835 azx_free(chip); 1836 return err; 1837 } 1838 1839 /* continue probing in work context as may trigger request module */ 1840 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work); 1841 1842 *rchip = chip; 1843 1844 return 0; 1845 } 1846 1847 static int azx_first_init(struct azx *chip) 1848 { 1849 int dev = chip->dev_index; 1850 struct pci_dev *pci = chip->pci; 1851 struct snd_card *card = chip->card; 1852 struct hdac_bus *bus = azx_bus(chip); 1853 int err; 1854 unsigned short gcap; 1855 unsigned int dma_bits = 64; 1856 1857 #if BITS_PER_LONG != 64 1858 /* Fix up base address on ULI M5461 */ 1859 if (chip->driver_type == AZX_DRIVER_ULI) { 1860 u16 tmp3; 1861 pci_read_config_word(pci, 0x40, &tmp3); 1862 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1863 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1864 } 1865 #endif 1866 /* 1867 * Fix response write request not synced to memory when handle 1868 * hdac interrupt on Glenfly Gpus 1869 */ 1870 if (chip->driver_type == AZX_DRIVER_GFHDMI) 1871 bus->polling_mode = 1; 1872 1873 if (chip->driver_type == AZX_DRIVER_LOONGSON) { 1874 bus->polling_mode = 1; 1875 bus->not_use_interrupts = 1; 1876 bus->access_sdnctl_in_dword = 1; 1877 if (!chip->jackpoll_interval) 1878 chip->jackpoll_interval = msecs_to_jiffies(1500); 1879 } 1880 1881 if (chip->driver_type == AZX_DRIVER_ZHAOXINHDMI) 1882 bus->polling_mode = 1; 1883 1884 bus->remap_addr = pcim_iomap_region(pci, 0, "ICH HD audio"); 1885 if (IS_ERR(bus->remap_addr)) 1886 return PTR_ERR(bus->remap_addr); 1887 1888 bus->addr = pci_resource_start(pci, 0); 1889 1890 if (chip->driver_type == AZX_DRIVER_SKL) 1891 snd_hdac_bus_parse_capabilities(bus); 1892 1893 /* 1894 * Some Intel CPUs has always running timer (ART) feature and 1895 * controller may have Global time sync reporting capability, so 1896 * check both of these before declaring synchronized time reporting 1897 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1898 */ 1899 chip->gts_present = false; 1900 1901 #ifdef CONFIG_X86 1902 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1903 chip->gts_present = true; 1904 #endif 1905 1906 if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1907 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1908 pci->no_64bit_msi = true; 1909 } 1910 1911 pci_set_master(pci); 1912 1913 gcap = azx_readw(chip, GCAP); 1914 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1915 1916 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1917 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1918 dma_bits = 40; 1919 1920 /* disable SB600 64bit support for safety */ 1921 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1922 struct pci_dev *p_smbus; 1923 dma_bits = 40; 1924 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1925 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1926 NULL); 1927 if (p_smbus) { 1928 if (p_smbus->revision < 0x30) 1929 gcap &= ~AZX_GCAP_64OK; 1930 pci_dev_put(p_smbus); 1931 } 1932 } 1933 1934 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1935 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1936 dma_bits = 40; 1937 1938 /* disable 64bit DMA address on some devices */ 1939 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1940 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1941 gcap &= ~AZX_GCAP_64OK; 1942 } 1943 1944 /* disable buffer size rounding to 128-byte multiples if supported */ 1945 if (align_buffer_size >= 0) 1946 chip->align_buffer_size = !!align_buffer_size; 1947 else { 1948 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1949 chip->align_buffer_size = 0; 1950 else 1951 chip->align_buffer_size = 1; 1952 } 1953 1954 /* allow 64bit DMA address if supported by H/W */ 1955 if (!(gcap & AZX_GCAP_64OK)) 1956 dma_bits = 32; 1957 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) 1958 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1959 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1960 1961 /* read number of streams from GCAP register instead of using 1962 * hardcoded value 1963 */ 1964 chip->capture_streams = (gcap >> 8) & 0x0f; 1965 chip->playback_streams = (gcap >> 12) & 0x0f; 1966 if (!chip->playback_streams && !chip->capture_streams) { 1967 /* gcap didn't give any info, switching to old method */ 1968 1969 switch (chip->driver_type) { 1970 case AZX_DRIVER_ULI: 1971 chip->playback_streams = ULI_NUM_PLAYBACK; 1972 chip->capture_streams = ULI_NUM_CAPTURE; 1973 break; 1974 case AZX_DRIVER_ATIHDMI: 1975 case AZX_DRIVER_ATIHDMI_NS: 1976 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1977 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1978 break; 1979 case AZX_DRIVER_GFHDMI: 1980 case AZX_DRIVER_ZHAOXINHDMI: 1981 case AZX_DRIVER_GENERIC: 1982 default: 1983 chip->playback_streams = ICH6_NUM_PLAYBACK; 1984 chip->capture_streams = ICH6_NUM_CAPTURE; 1985 break; 1986 } 1987 } 1988 chip->capture_index_offset = 0; 1989 chip->playback_index_offset = chip->capture_streams; 1990 chip->num_streams = chip->playback_streams + chip->capture_streams; 1991 1992 /* sanity check for the SDxCTL.STRM field overflow */ 1993 if (chip->num_streams > 15 && 1994 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1995 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1996 "forcing separate stream tags", chip->num_streams); 1997 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1998 } 1999 2000 /* initialize streams */ 2001 err = azx_init_streams(chip); 2002 if (err < 0) 2003 return err; 2004 2005 err = azx_alloc_stream_pages(chip); 2006 if (err < 0) 2007 return err; 2008 2009 /* initialize chip */ 2010 azx_init_pci(chip); 2011 2012 snd_hdac_i915_set_bclk(bus); 2013 2014 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 2015 2016 /* codec detection */ 2017 if (!azx_bus(chip)->codec_mask) { 2018 dev_err(card->dev, "no codecs found!\n"); 2019 /* keep running the rest for the runtime PM */ 2020 } 2021 2022 if (azx_acquire_irq(chip, 0) < 0) 2023 return -EBUSY; 2024 2025 strscpy(card->driver, "HDA-Intel"); 2026 strscpy(card->shortname, driver_short_names[chip->driver_type], 2027 sizeof(card->shortname)); 2028 snprintf(card->longname, sizeof(card->longname), 2029 "%s at 0x%lx irq %i", 2030 card->shortname, bus->addr, bus->irq); 2031 2032 return 0; 2033 } 2034 2035 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2036 /* callback from request_firmware_nowait() */ 2037 static void azx_firmware_cb(const struct firmware *fw, void *context) 2038 { 2039 struct snd_card *card = context; 2040 struct azx *chip = card->private_data; 2041 2042 if (fw) 2043 chip->fw = fw; 2044 else 2045 dev_err(card->dev, "Cannot load firmware, continue without patching\n"); 2046 if (!chip->disabled) { 2047 /* continue probing */ 2048 azx_probe_continue(chip); 2049 } 2050 } 2051 #endif 2052 2053 static int disable_msi_reset_irq(struct azx *chip) 2054 { 2055 struct hdac_bus *bus = azx_bus(chip); 2056 int err; 2057 2058 free_irq(bus->irq, chip); 2059 bus->irq = -1; 2060 chip->card->sync_irq = -1; 2061 pci_free_irq_vectors(chip->pci); 2062 chip->msi = 0; 2063 err = azx_acquire_irq(chip, 1); 2064 if (err < 0) 2065 return err; 2066 2067 return 0; 2068 } 2069 2070 /* Denylist for skipping the whole probe: 2071 * some HD-audio PCI entries are exposed without any codecs, and such devices 2072 * should be ignored from the beginning. 2073 */ 2074 static const struct pci_device_id driver_denylist[] = { 2075 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2076 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2077 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2078 { PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1462, 0xee59) }, /* MSI X870E Tomahawk WiFi */ 2079 {} 2080 }; 2081 2082 static struct pci_device_id driver_denylist_ideapad_z570[] = { 2083 { PCI_DEVICE_SUB(0x10de, 0x0bea, 0x0000, 0x0000) }, /* NVIDIA GF108 HDA */ 2084 {} 2085 }; 2086 2087 /* DMI-based denylist, to be used when: 2088 * - PCI subsystem IDs are zero, impossible to distinguish from valid sound cards. 2089 * - Different modifications of the same laptop use different GPU models. 2090 */ 2091 static const struct dmi_system_id driver_denylist_dmi[] = { 2092 { 2093 /* No HDA in NVIDIA DGPU. BIOS disables it, but quirk_nvidia_hda() reenables. */ 2094 .matches = { 2095 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 2096 DMI_MATCH(DMI_PRODUCT_VERSION, "Ideapad Z570"), 2097 }, 2098 .driver_data = &driver_denylist_ideapad_z570, 2099 }, 2100 {} 2101 }; 2102 2103 static const struct hda_controller_ops pci_hda_ops = { 2104 .disable_msi_reset_irq = disable_msi_reset_irq, 2105 .position_check = azx_position_check, 2106 }; 2107 2108 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS); 2109 2110 static int azx_probe(struct pci_dev *pci, 2111 const struct pci_device_id *pci_id) 2112 { 2113 const struct dmi_system_id *dmi; 2114 struct snd_card *card; 2115 struct hda_intel *hda; 2116 struct azx *chip; 2117 bool schedule_probe; 2118 int dev; 2119 int err; 2120 2121 if (pci_match_id(driver_denylist, pci)) { 2122 dev_info(&pci->dev, "Skipping the device on the denylist\n"); 2123 return -ENODEV; 2124 } 2125 2126 dmi = dmi_first_match(driver_denylist_dmi); 2127 if (dmi && pci_match_id(dmi->driver_data, pci)) { 2128 dev_info(&pci->dev, "Skipping the device on the DMI denylist\n"); 2129 return -ENODEV; 2130 } 2131 2132 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS); 2133 if (dev >= SNDRV_CARDS) 2134 return -ENODEV; 2135 if (!enable[dev]) { 2136 set_bit(dev, probed_devs); 2137 return -ENOENT; 2138 } 2139 2140 /* 2141 * stop probe if another Intel's DSP driver should be activated 2142 */ 2143 if (dmic_detect) { 2144 err = snd_intel_dsp_driver_probe(pci); 2145 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { 2146 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); 2147 return -ENODEV; 2148 } 2149 } else { 2150 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2151 } 2152 2153 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2154 0, &card); 2155 if (err < 0) { 2156 dev_err(&pci->dev, "Error creating card!\n"); 2157 return err; 2158 } 2159 2160 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2161 if (err < 0) 2162 goto out_free; 2163 card->private_data = chip; 2164 hda = container_of(chip, struct hda_intel, chip); 2165 2166 pci_set_drvdata(pci, card); 2167 2168 #ifdef CONFIG_SND_HDA_I915 2169 /* bind with i915 if needed */ 2170 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2171 err = snd_hdac_i915_init(azx_bus(chip)); 2172 if (err < 0) { 2173 if (err == -EPROBE_DEFER) 2174 goto out_free; 2175 2176 /* if the controller is bound only with HDMI/DP 2177 * (for HSW and BDW), we need to abort the probe; 2178 * for other chips, still continue probing as other 2179 * codecs can be on the same link. 2180 */ 2181 if (HDA_CONTROLLER_IN_GPU(pci)) { 2182 dev_err_probe(card->dev, err, 2183 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2184 2185 goto out_free; 2186 } else { 2187 /* don't bother any longer */ 2188 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2189 } 2190 } 2191 2192 /* HSW/BDW controllers need this power */ 2193 if (HDA_CONTROLLER_IN_GPU(pci)) 2194 hda->need_i915_power = true; 2195 } 2196 #else 2197 if (HDA_CONTROLLER_IN_GPU(pci)) 2198 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2199 #endif 2200 2201 err = register_vga_switcheroo(chip); 2202 if (err < 0) { 2203 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2204 goto out_free; 2205 } 2206 2207 if (check_hdmi_disabled(pci)) { 2208 dev_info(card->dev, "VGA controller is disabled\n"); 2209 dev_info(card->dev, "Delaying initialization\n"); 2210 chip->disabled = true; 2211 } 2212 2213 schedule_probe = !chip->disabled; 2214 2215 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2216 if (patch[dev] && *patch[dev]) { 2217 dev_info(card->dev, "Applying patch firmware '%s'\n", 2218 patch[dev]); 2219 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2220 &pci->dev, GFP_KERNEL, card, 2221 azx_firmware_cb); 2222 if (err < 0) 2223 goto out_free; 2224 schedule_probe = false; /* continued in azx_firmware_cb() */ 2225 } 2226 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2227 2228 if (schedule_probe) 2229 schedule_delayed_work(&hda->probe_work, 0); 2230 2231 set_bit(dev, probed_devs); 2232 if (chip->disabled) 2233 complete_all(&hda->probe_wait); 2234 return 0; 2235 2236 out_free: 2237 pci_set_drvdata(pci, NULL); 2238 snd_card_free(card); 2239 return err; 2240 } 2241 2242 /* On some boards setting power_save to a non 0 value leads to clicking / 2243 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2244 * figure out how to avoid these sounds, but that is not always feasible. 2245 * So we keep a list of devices where we disable powersaving as its known 2246 * to causes problems on these devices. 2247 */ 2248 static const struct snd_pci_quirk power_save_denylist[] = { 2249 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2250 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2251 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2252 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2253 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2254 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2255 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2256 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2257 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2258 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2259 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2260 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2261 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2262 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2263 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2264 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2265 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2266 /* https://bugs.launchpad.net/bugs/1821663 */ 2267 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2268 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2269 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2270 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2271 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2272 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0), 2273 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2274 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2275 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2276 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2277 /* https://bugs.launchpad.net/bugs/1821663 */ 2278 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2279 /* KONTRON SinglePC may cause a stall at runtime resume */ 2280 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0), 2281 /* Dell ALC3271 */ 2282 SND_PCI_QUIRK(0x1028, 0x0962, "Dell ALC3271", 0), 2283 /* https://bugzilla.kernel.org/show_bug.cgi?id=220210 */ 2284 SND_PCI_QUIRK(0x17aa, 0x5079, "Lenovo Thinkpad E15", 0), 2285 {} 2286 }; 2287 2288 static void set_default_power_save(struct azx *chip) 2289 { 2290 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2291 int val = power_save; 2292 2293 if (pm_blacklist < 0) { 2294 const struct snd_pci_quirk *q; 2295 2296 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); 2297 if (q && val) { 2298 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", 2299 q->subvendor, q->subdevice); 2300 val = 0; 2301 hda->runtime_pm_disabled = 1; 2302 } 2303 } else if (pm_blacklist > 0) { 2304 dev_info(chip->card->dev, "Forcing power_save to 0 via option\n"); 2305 val = 0; 2306 } 2307 snd_hda_set_power_save(&chip->bus, val * 1000); 2308 } 2309 2310 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2311 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2312 [AZX_DRIVER_NVIDIA] = 8, 2313 [AZX_DRIVER_TERA] = 1, 2314 }; 2315 2316 static int azx_probe_continue(struct azx *chip) 2317 { 2318 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2319 struct hdac_bus *bus = azx_bus(chip); 2320 struct pci_dev *pci = chip->pci; 2321 int dev = chip->dev_index; 2322 int err; 2323 2324 if (chip->disabled || hda->init_failed) 2325 return -EIO; 2326 if (hda->probe_retry) 2327 goto probe_retry; 2328 2329 to_hda_bus(bus)->bus_probing = 1; 2330 hda->probe_continued = 1; 2331 2332 /* Request display power well for the HDA controller or codec. For 2333 * Haswell/Broadwell, both the display HDA controller and codec need 2334 * this power. For other platforms, like Baytrail/Braswell, only the 2335 * display codec needs the power and it can be released after probe. 2336 */ 2337 display_power(chip, true); 2338 2339 err = azx_first_init(chip); 2340 if (err < 0) 2341 goto out_free; 2342 2343 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2344 chip->beep_mode = beep_mode[dev]; 2345 #endif 2346 2347 chip->ctl_dev_id = ctl_dev_id; 2348 2349 /* create codec instances */ 2350 if (bus->codec_mask) { 2351 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2352 if (err < 0) 2353 goto out_free; 2354 } 2355 2356 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2357 if (chip->fw) { 2358 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2359 chip->fw->data); 2360 if (err < 0) 2361 goto out_free; 2362 } 2363 #endif 2364 2365 probe_retry: 2366 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2367 err = azx_codec_configure(chip); 2368 if (err) { 2369 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) && 2370 ++hda->probe_retry < 60) { 2371 schedule_delayed_work(&hda->probe_work, 2372 msecs_to_jiffies(1000)); 2373 return 0; /* keep things up */ 2374 } 2375 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n"); 2376 goto out_free; 2377 } 2378 } 2379 2380 err = snd_card_register(chip->card); 2381 if (err < 0) 2382 goto out_free; 2383 2384 setup_vga_switcheroo_runtime_pm(chip); 2385 2386 chip->running = 1; 2387 azx_add_card_list(chip); 2388 2389 set_default_power_save(chip); 2390 2391 if (azx_has_pm_runtime(chip)) { 2392 pm_runtime_use_autosuspend(&pci->dev); 2393 pm_runtime_allow(&pci->dev); 2394 pm_runtime_put_autosuspend(&pci->dev); 2395 } 2396 2397 out_free: 2398 if (err < 0) { 2399 pci_set_drvdata(pci, NULL); 2400 snd_card_free(chip->card); 2401 return err; 2402 } 2403 2404 if (!hda->need_i915_power) 2405 display_power(chip, false); 2406 complete_all(&hda->probe_wait); 2407 to_hda_bus(bus)->bus_probing = 0; 2408 hda->probe_retry = 0; 2409 return 0; 2410 } 2411 2412 static void azx_remove(struct pci_dev *pci) 2413 { 2414 struct snd_card *card = pci_get_drvdata(pci); 2415 struct azx *chip; 2416 struct hda_intel *hda; 2417 2418 if (card) { 2419 /* cancel the pending probing work */ 2420 chip = card->private_data; 2421 hda = container_of(chip, struct hda_intel, chip); 2422 /* FIXME: below is an ugly workaround. 2423 * Both device_release_driver() and driver_probe_device() 2424 * take *both* the device's and its parent's lock before 2425 * calling the remove() and probe() callbacks. The codec 2426 * probe takes the locks of both the codec itself and its 2427 * parent, i.e. the PCI controller dev. Meanwhile, when 2428 * the PCI controller is unbound, it takes its lock, too 2429 * ==> ouch, a deadlock! 2430 * As a workaround, we unlock temporarily here the controller 2431 * device during cancel_work_sync() call. 2432 */ 2433 device_unlock(&pci->dev); 2434 cancel_delayed_work_sync(&hda->probe_work); 2435 device_lock(&pci->dev); 2436 2437 clear_bit(chip->dev_index, probed_devs); 2438 pci_set_drvdata(pci, NULL); 2439 snd_card_free(card); 2440 } 2441 } 2442 2443 static void azx_shutdown(struct pci_dev *pci) 2444 { 2445 struct snd_card *card = pci_get_drvdata(pci); 2446 struct azx *chip; 2447 2448 if (!card) 2449 return; 2450 chip = card->private_data; 2451 if (chip && chip->running) 2452 __azx_shutdown_chip(chip, true); 2453 } 2454 2455 /* PCI IDs */ 2456 static const struct pci_device_id azx_ids[] = { 2457 /* CPT */ 2458 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2459 /* PBG */ 2460 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2461 /* Panther Point */ 2462 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2463 /* Lynx Point */ 2464 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2465 /* 9 Series */ 2466 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2467 /* Wellsburg */ 2468 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2469 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2470 /* Lewisburg */ 2471 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, 2472 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, 2473 /* Lynx Point-LP */ 2474 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2475 /* Lynx Point-LP */ 2476 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2477 /* Wildcat Point-LP */ 2478 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2479 /* Skylake (Sunrise Point) */ 2480 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2481 /* Skylake-LP (Sunrise Point-LP) */ 2482 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2483 /* Kabylake */ 2484 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2485 /* Kabylake-LP */ 2486 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2487 /* Kabylake-H */ 2488 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2489 /* Coffelake */ 2490 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2491 /* Cannonlake */ 2492 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2493 /* CometLake-LP */ 2494 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2495 /* CometLake-H */ 2496 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2497 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2498 /* CometLake-S */ 2499 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2500 /* CometLake-R */ 2501 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2502 /* Icelake */ 2503 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2504 /* Icelake-H */ 2505 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2506 /* Jasperlake */ 2507 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2508 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2509 /* Tigerlake */ 2510 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2511 /* Tigerlake-H */ 2512 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2513 /* DG1 */ 2514 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2515 /* DG2 */ 2516 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2517 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2518 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2519 /* Alderlake-S */ 2520 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2521 /* Alderlake-P */ 2522 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2523 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2524 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2525 /* Alderlake-M */ 2526 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2527 /* Alderlake-N */ 2528 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2529 /* Elkhart Lake */ 2530 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2531 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2532 /* Raptor Lake */ 2533 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2534 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2535 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2536 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2537 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2538 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2539 /* Battlemage */ 2540 { PCI_DEVICE_DATA(INTEL, HDA_BMG, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2541 /* Lunarlake-P */ 2542 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2543 /* Arrow Lake-S */ 2544 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2545 /* Arrow Lake */ 2546 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2547 /* Panther Lake */ 2548 { PCI_DEVICE_DATA(INTEL, HDA_PTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2549 /* Panther Lake-H */ 2550 { PCI_DEVICE_DATA(INTEL, HDA_PTL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2551 /* Wildcat Lake */ 2552 { PCI_DEVICE_DATA(INTEL, HDA_WCL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2553 /* Apollolake (Broxton-P) */ 2554 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, 2555 /* Gemini-Lake */ 2556 { PCI_DEVICE_DATA(INTEL, HDA_GML, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, 2557 /* Haswell */ 2558 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2559 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2560 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2561 /* Broadwell */ 2562 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) }, 2563 /* 5 Series/3400 */ 2564 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2565 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2566 /* Poulsbo */ 2567 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE | 2568 AZX_DCAPS_POSFIX_LPIB) }, 2569 /* Oaktrail */ 2570 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) }, 2571 /* BayTrail */ 2572 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) }, 2573 /* Braswell */ 2574 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) }, 2575 /* ICH6 */ 2576 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2577 /* ICH7 */ 2578 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2579 /* ESB2 */ 2580 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2581 /* ICH8 */ 2582 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2583 /* ICH9 */ 2584 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2585 /* ICH9 */ 2586 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2587 /* ICH10 */ 2588 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2589 /* ICH10 */ 2590 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2591 /* Generic Intel */ 2592 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2593 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2594 .class_mask = 0xffffff, 2595 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2596 /* ATI SB 450/600/700/800/900 */ 2597 { PCI_VDEVICE(ATI, 0x437b), 2598 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2599 { PCI_VDEVICE(ATI, 0x4383), 2600 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2601 /* AMD Hudson */ 2602 { PCI_VDEVICE(AMD, 0x780d), 2603 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2604 /* AMD, X370 & co */ 2605 { PCI_VDEVICE(AMD, 0x1457), 2606 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2607 /* AMD, X570 & co */ 2608 { PCI_VDEVICE(AMD, 0x1487), 2609 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2610 /* AMD Stoney */ 2611 { PCI_VDEVICE(AMD, 0x157a), 2612 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2613 AZX_DCAPS_PM_RUNTIME }, 2614 /* AMD Raven */ 2615 { PCI_VDEVICE(AMD, 0x15e3), 2616 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2617 /* ATI HDMI */ 2618 { PCI_VDEVICE(ATI, 0x0002), 2619 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2620 AZX_DCAPS_PM_RUNTIME }, 2621 { PCI_VDEVICE(ATI, 0x1308), 2622 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2623 { PCI_VDEVICE(ATI, 0x157a), 2624 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2625 { PCI_VDEVICE(ATI, 0x15b3), 2626 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2627 { PCI_VDEVICE(ATI, 0x793b), 2628 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2629 { PCI_VDEVICE(ATI, 0x7919), 2630 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2631 { PCI_VDEVICE(ATI, 0x960f), 2632 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2633 { PCI_VDEVICE(ATI, 0x970f), 2634 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2635 { PCI_VDEVICE(ATI, 0x9840), 2636 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2637 { PCI_VDEVICE(ATI, 0xaa00), 2638 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2639 { PCI_VDEVICE(ATI, 0xaa08), 2640 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2641 { PCI_VDEVICE(ATI, 0xaa10), 2642 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2643 { PCI_VDEVICE(ATI, 0xaa18), 2644 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2645 { PCI_VDEVICE(ATI, 0xaa20), 2646 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2647 { PCI_VDEVICE(ATI, 0xaa28), 2648 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2649 { PCI_VDEVICE(ATI, 0xaa30), 2650 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2651 { PCI_VDEVICE(ATI, 0xaa38), 2652 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2653 { PCI_VDEVICE(ATI, 0xaa40), 2654 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2655 { PCI_VDEVICE(ATI, 0xaa48), 2656 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2657 { PCI_VDEVICE(ATI, 0xaa50), 2658 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2659 { PCI_VDEVICE(ATI, 0xaa58), 2660 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2661 { PCI_VDEVICE(ATI, 0xaa60), 2662 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2663 { PCI_VDEVICE(ATI, 0xaa68), 2664 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2665 { PCI_VDEVICE(ATI, 0xaa80), 2666 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2667 { PCI_VDEVICE(ATI, 0xaa88), 2668 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2669 { PCI_VDEVICE(ATI, 0xaa90), 2670 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2671 { PCI_VDEVICE(ATI, 0xaa98), 2672 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2673 { PCI_VDEVICE(ATI, 0x9902), 2674 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2675 { PCI_VDEVICE(ATI, 0xaaa0), 2676 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2677 { PCI_VDEVICE(ATI, 0xaaa8), 2678 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2679 { PCI_VDEVICE(ATI, 0xaab0), 2680 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2681 { PCI_VDEVICE(ATI, 0xaac0), 2682 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2683 AZX_DCAPS_PM_RUNTIME }, 2684 { PCI_VDEVICE(ATI, 0xaac8), 2685 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2686 AZX_DCAPS_PM_RUNTIME }, 2687 { PCI_VDEVICE(ATI, 0xaad8), 2688 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2689 AZX_DCAPS_PM_RUNTIME }, 2690 { PCI_VDEVICE(ATI, 0xaae0), 2691 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2692 AZX_DCAPS_PM_RUNTIME }, 2693 { PCI_VDEVICE(ATI, 0xaae8), 2694 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2695 AZX_DCAPS_PM_RUNTIME }, 2696 { PCI_VDEVICE(ATI, 0xaaf0), 2697 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2698 AZX_DCAPS_PM_RUNTIME }, 2699 { PCI_VDEVICE(ATI, 0xaaf8), 2700 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2701 AZX_DCAPS_PM_RUNTIME }, 2702 { PCI_VDEVICE(ATI, 0xab00), 2703 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2704 AZX_DCAPS_PM_RUNTIME }, 2705 { PCI_VDEVICE(ATI, 0xab08), 2706 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2707 AZX_DCAPS_PM_RUNTIME }, 2708 { PCI_VDEVICE(ATI, 0xab10), 2709 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2710 AZX_DCAPS_PM_RUNTIME }, 2711 { PCI_VDEVICE(ATI, 0xab18), 2712 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2713 AZX_DCAPS_PM_RUNTIME }, 2714 { PCI_VDEVICE(ATI, 0xab20), 2715 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2716 AZX_DCAPS_PM_RUNTIME }, 2717 { PCI_VDEVICE(ATI, 0xab28), 2718 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2719 AZX_DCAPS_PM_RUNTIME }, 2720 { PCI_VDEVICE(ATI, 0xab30), 2721 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2722 AZX_DCAPS_PM_RUNTIME }, 2723 { PCI_VDEVICE(ATI, 0xab38), 2724 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2725 AZX_DCAPS_PM_RUNTIME }, 2726 { PCI_VDEVICE(ATI, 0xab40), 2727 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2728 AZX_DCAPS_PM_RUNTIME }, 2729 /* GLENFLY */ 2730 { PCI_DEVICE(PCI_VENDOR_ID_GLENFLY, PCI_ANY_ID), 2731 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2732 .class_mask = 0xffffff, 2733 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB | 2734 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2735 /* VIA VT8251/VT8237A */ 2736 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2737 /* VIA GFX VT7122/VX900 */ 2738 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2739 /* VIA GFX VT6122/VX11 */ 2740 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2741 /* SIS966 */ 2742 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2743 /* ULI M5461 */ 2744 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2745 /* NVIDIA MCP */ 2746 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2747 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2748 .class_mask = 0xffffff, 2749 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2750 /* Teradici */ 2751 { PCI_DEVICE(0x6549, 0x1200), 2752 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2753 { PCI_DEVICE(0x6549, 0x2200), 2754 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2755 /* Creative X-Fi (CA0110-IBG) */ 2756 /* CTHDA chips */ 2757 { PCI_VDEVICE(CREATIVE, 0x0010), 2758 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2759 { PCI_VDEVICE(CREATIVE, 0x0012), 2760 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2761 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2762 /* the following entry conflicts with snd-ctxfi driver, 2763 * as ctxfi driver mutates from HD-audio to native mode with 2764 * a special command sequence. 2765 */ 2766 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2767 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2768 .class_mask = 0xffffff, 2769 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2770 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2771 #else 2772 /* this entry seems still valid -- i.e. without emu20kx chip */ 2773 { PCI_VDEVICE(CREATIVE, 0x0009), 2774 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2775 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2776 #endif 2777 /* CM8888 */ 2778 { PCI_VDEVICE(CMEDIA, 0x5011), 2779 .driver_data = AZX_DRIVER_CMEDIA | 2780 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2781 /* Vortex86MX */ 2782 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2783 /* VMware HDAudio */ 2784 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2785 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2786 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2787 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2788 .class_mask = 0xffffff, 2789 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2790 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2791 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2792 .class_mask = 0xffffff, 2793 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2794 /* Zhaoxin */ 2795 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2796 { PCI_VDEVICE(ZHAOXIN, 0x9141), 2797 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB | 2798 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2799 { PCI_VDEVICE(ZHAOXIN, 0x9142), 2800 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB | 2801 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2802 { PCI_VDEVICE(ZHAOXIN, 0x9144), 2803 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB | 2804 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2805 { PCI_VDEVICE(ZHAOXIN, 0x9145), 2806 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB | 2807 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2808 { PCI_VDEVICE(ZHAOXIN, 0x9146), 2809 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB | 2810 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2811 /* Loongson HDAudio*/ 2812 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA), 2813 .driver_data = AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL }, 2814 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI), 2815 .driver_data = AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL }, 2816 { 0, } 2817 }; 2818 MODULE_DEVICE_TABLE(pci, azx_ids); 2819 2820 /* pci_driver definition */ 2821 static struct pci_driver azx_driver = { 2822 .name = KBUILD_MODNAME, 2823 .id_table = azx_ids, 2824 .probe = azx_probe, 2825 .remove = azx_remove, 2826 .shutdown = azx_shutdown, 2827 .driver = { 2828 .pm = pm_ptr(&azx_pm), 2829 }, 2830 }; 2831 2832 module_pci_driver(azx_driver); 2833