1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 #include <linux/pgtable.h> 40 #include <linux/dmi.h> 41 42 #ifdef CONFIG_X86 43 /* for snoop control */ 44 #include <asm/set_memory.h> 45 #include <asm/cpufeature.h> 46 #endif 47 #include <sound/core.h> 48 #include <sound/initval.h> 49 #include <sound/hdaudio.h> 50 #include <sound/hda_i915.h> 51 #include <sound/intel-dsp-config.h> 52 #include <linux/vgaarb.h> 53 #include <linux/vga_switcheroo.h> 54 #include <linux/apple-gmux.h> 55 #include <linux/firmware.h> 56 #include <sound/hda_codec.h> 57 #include "intel.h" 58 59 #define CREATE_TRACE_POINTS 60 #include "intel_trace.h" 61 62 /* position fix mode */ 63 enum { 64 POS_FIX_AUTO, 65 POS_FIX_LPIB, 66 POS_FIX_POSBUF, 67 POS_FIX_VIACOMBO, 68 POS_FIX_COMBO, 69 POS_FIX_SKL, 70 POS_FIX_FIFO, 71 }; 72 73 /* Defines for ATI HD Audio support in SB450 south bridge */ 74 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 75 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 76 77 /* Defines for Nvidia HDA support */ 78 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 79 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 80 #define NVIDIA_HDA_ISTRM_COH 0x4d 81 #define NVIDIA_HDA_OSTRM_COH 0x4c 82 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 83 84 /* Defines for Intel SCH HDA snoop control */ 85 #define INTEL_HDA_CGCTL 0x48 86 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 87 #define INTEL_SCH_HDA_DEVC 0x78 88 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 89 90 /* max number of SDs */ 91 /* ICH, ATI and VIA have 4 playback and 4 capture */ 92 #define ICH6_NUM_CAPTURE 4 93 #define ICH6_NUM_PLAYBACK 4 94 95 /* ULI has 6 playback and 5 capture */ 96 #define ULI_NUM_CAPTURE 5 97 #define ULI_NUM_PLAYBACK 6 98 99 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 100 #define ATIHDMI_NUM_CAPTURE 0 101 #define ATIHDMI_NUM_PLAYBACK 8 102 103 /* Hygon HD Audio controller */ 104 #define PCI_DEVICE_ID_HYGON_18H_M05H_HDA 0x14a9 105 106 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 107 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 108 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 109 static char *model[SNDRV_CARDS]; 110 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 111 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 112 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 113 static int probe_only[SNDRV_CARDS]; 114 static int jackpoll_ms[SNDRV_CARDS]; 115 static int single_cmd = -1; 116 static int enable_msi = -1; 117 #ifdef CONFIG_SND_HDA_PATCH_LOADER 118 static char *patch[SNDRV_CARDS]; 119 #endif 120 #ifdef CONFIG_SND_HDA_INPUT_BEEP 121 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 122 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 123 #endif 124 static bool dmic_detect = 1; 125 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0; 126 127 module_param_array(index, int, NULL, 0444); 128 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 129 module_param_array(id, charp, NULL, 0444); 130 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 131 module_param_array(enable, bool, NULL, 0444); 132 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 133 module_param_array(model, charp, NULL, 0444); 134 MODULE_PARM_DESC(model, "Use the given board model."); 135 module_param_array(position_fix, int, NULL, 0444); 136 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 137 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 138 module_param_array(bdl_pos_adj, int, NULL, 0644); 139 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 140 module_param_array(probe_mask, int, NULL, 0444); 141 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 142 module_param_array(probe_only, int, NULL, 0444); 143 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 144 module_param_array(jackpoll_ms, int, NULL, 0444); 145 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 146 module_param(single_cmd, bint, 0444); 147 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 148 "(for debugging only)."); 149 module_param(enable_msi, bint, 0444); 150 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 151 #ifdef CONFIG_SND_HDA_PATCH_LOADER 152 module_param_array(patch, charp, NULL, 0444); 153 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 154 #endif 155 #ifdef CONFIG_SND_HDA_INPUT_BEEP 156 module_param_array(beep_mode, bool, NULL, 0444); 157 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 158 "(0=off, 1=on) (default=1)."); 159 #endif 160 module_param(dmic_detect, bool, 0444); 161 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 162 "(0=off, 1=on) (default=1); " 163 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 164 module_param(ctl_dev_id, bool, 0444); 165 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address)."); 166 167 #ifdef CONFIG_PM 168 static int param_set_xint(const char *val, const struct kernel_param *kp); 169 static const struct kernel_param_ops param_ops_xint = { 170 .set = param_set_xint, 171 .get = param_get_int, 172 }; 173 #define param_check_xint param_check_int 174 175 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 176 module_param(power_save, xint, 0644); 177 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 178 "(in second, 0 = disable)."); 179 180 static int pm_blacklist = -1; 181 module_param(pm_blacklist, bint, 0644); 182 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); 183 184 /* reset the HD-audio controller in power save mode. 185 * this may give more power-saving, but will take longer time to 186 * wake up. 187 */ 188 static bool power_save_controller = 1; 189 module_param(power_save_controller, bool, 0644); 190 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 191 #else /* CONFIG_PM */ 192 #define power_save 0 193 #define pm_blacklist 0 194 #define power_save_controller false 195 #endif /* CONFIG_PM */ 196 197 static int align_buffer_size = -1; 198 module_param(align_buffer_size, bint, 0644); 199 MODULE_PARM_DESC(align_buffer_size, 200 "Force buffer and period sizes to be multiple of 128 bytes."); 201 202 #ifdef CONFIG_X86 203 static int hda_snoop = -1; 204 module_param_named(snoop, hda_snoop, bint, 0444); 205 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 206 #else 207 #define hda_snoop true 208 #endif 209 210 211 MODULE_LICENSE("GPL"); 212 MODULE_DESCRIPTION("Intel HDA driver"); 213 214 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 215 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 216 #define SUPPORT_VGA_SWITCHEROO 217 #endif 218 #endif 219 220 221 /* 222 */ 223 224 /* driver types */ 225 enum { 226 AZX_DRIVER_ICH, 227 AZX_DRIVER_PCH, 228 AZX_DRIVER_SCH, 229 AZX_DRIVER_SKL, 230 AZX_DRIVER_HDMI, 231 AZX_DRIVER_ATI, 232 AZX_DRIVER_ATIHDMI, 233 AZX_DRIVER_ATIHDMI_NS, 234 AZX_DRIVER_GFHDMI, 235 AZX_DRIVER_VIA, 236 AZX_DRIVER_SIS, 237 AZX_DRIVER_ULI, 238 AZX_DRIVER_NVIDIA, 239 AZX_DRIVER_TERA, 240 AZX_DRIVER_CTX, 241 AZX_DRIVER_CTHDA, 242 AZX_DRIVER_CMEDIA, 243 AZX_DRIVER_ZHAOXIN, 244 AZX_DRIVER_ZHAOXINHDMI, 245 AZX_DRIVER_LOONGSON, 246 AZX_DRIVER_HYGON, 247 AZX_DRIVER_GENERIC, 248 AZX_NUM_DRIVERS, /* keep this as last entry */ 249 }; 250 251 #define azx_get_snoop_type(chip) \ 252 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 253 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 254 255 /* quirks for old Intel chipsets */ 256 #define AZX_DCAPS_INTEL_ICH \ 257 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 258 259 /* quirks for Intel PCH */ 260 #define AZX_DCAPS_INTEL_PCH_BASE \ 261 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 262 AZX_DCAPS_SNOOP_TYPE(SCH)) 263 264 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 265 #define AZX_DCAPS_INTEL_PCH_NOPM \ 266 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 267 268 /* PCH for HSW/BDW; with runtime PM */ 269 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 270 #define AZX_DCAPS_INTEL_PCH \ 271 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 272 273 /* HSW HDMI */ 274 #define AZX_DCAPS_INTEL_HASWELL \ 275 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 276 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 277 AZX_DCAPS_SNOOP_TYPE(SCH)) 278 279 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 280 #define AZX_DCAPS_INTEL_BROADWELL \ 281 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 282 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 283 AZX_DCAPS_SNOOP_TYPE(SCH)) 284 285 #define AZX_DCAPS_INTEL_BAYTRAIL \ 286 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 287 288 #define AZX_DCAPS_INTEL_BRASWELL \ 289 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 290 AZX_DCAPS_I915_COMPONENT) 291 292 #define AZX_DCAPS_INTEL_SKYLAKE \ 293 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 294 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 295 296 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 297 298 #define AZX_DCAPS_INTEL_LNL \ 299 (AZX_DCAPS_INTEL_SKYLAKE | AZX_DCAPS_PIO_COMMANDS) 300 301 #define AZX_DCAPS_INTEL_NVL \ 302 (AZX_DCAPS_INTEL_LNL & ~AZX_DCAPS_NO_ALIGN_BUFSIZE) 303 304 /* quirks for ATI SB / AMD Hudson */ 305 #define AZX_DCAPS_PRESET_ATI_SB \ 306 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ 307 AZX_DCAPS_SNOOP_TYPE(ATI)) 308 309 /* quirks for ATI/AMD HDMI */ 310 #define AZX_DCAPS_PRESET_ATI_HDMI \ 311 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ 312 AZX_DCAPS_NO_MSI64) 313 314 /* quirks for ATI HDMI with snoop off */ 315 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 316 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 317 318 /* quirks for AMD SB */ 319 #define AZX_DCAPS_PRESET_AMD_SB \ 320 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ 321 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\ 322 AZX_DCAPS_RETRY_PROBE) 323 324 /* quirks for Nvidia */ 325 #define AZX_DCAPS_PRESET_NVIDIA \ 326 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 327 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 328 329 #define AZX_DCAPS_PRESET_CTHDA \ 330 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 331 AZX_DCAPS_NO_64BIT |\ 332 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 333 334 /* 335 * vga_switcheroo support 336 */ 337 #ifdef SUPPORT_VGA_SWITCHEROO 338 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 339 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 340 #else 341 #define use_vga_switcheroo(chip) 0 342 #define needs_eld_notify_link(chip) false 343 #endif 344 345 static const char * const driver_short_names[] = { 346 [AZX_DRIVER_ICH] = "HDA Intel", 347 [AZX_DRIVER_PCH] = "HDA Intel PCH", 348 [AZX_DRIVER_SCH] = "HDA Intel MID", 349 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 350 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 351 [AZX_DRIVER_ATI] = "HDA ATI SB", 352 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 353 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 354 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI", 355 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 356 [AZX_DRIVER_SIS] = "HDA SIS966", 357 [AZX_DRIVER_ULI] = "HDA ULI M5461", 358 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 359 [AZX_DRIVER_TERA] = "HDA Teradici", 360 [AZX_DRIVER_CTX] = "HDA Creative", 361 [AZX_DRIVER_CTHDA] = "HDA Creative", 362 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 363 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 364 [AZX_DRIVER_ZHAOXINHDMI] = "HDA Zhaoxin HDMI", 365 [AZX_DRIVER_LOONGSON] = "HDA Loongson", 366 [AZX_DRIVER_HYGON] = "HDA Hygon", 367 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 368 }; 369 370 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 371 static void set_default_power_save(struct azx *chip); 372 373 /* 374 * initialize the PCI registers 375 */ 376 /* update bits in a PCI register byte */ 377 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 378 unsigned char mask, unsigned char val) 379 { 380 unsigned char data; 381 382 pci_read_config_byte(pci, reg, &data); 383 data &= ~mask; 384 data |= (val & mask); 385 pci_write_config_byte(pci, reg, data); 386 } 387 388 static void azx_init_pci(struct azx *chip) 389 { 390 int snoop_type = azx_get_snoop_type(chip); 391 392 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 393 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 394 * Ensuring these bits are 0 clears playback static on some HD Audio 395 * codecs. 396 * The PCI register TCSEL is defined in the Intel manuals. 397 */ 398 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 399 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 400 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 401 } 402 403 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 404 * we need to enable snoop. 405 */ 406 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 407 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 408 azx_snoop(chip)); 409 update_pci_byte(chip->pci, 410 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 411 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 412 } 413 414 /* For NVIDIA HDA, enable snoop */ 415 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 416 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 417 azx_snoop(chip)); 418 update_pci_byte(chip->pci, 419 NVIDIA_HDA_TRANSREG_ADDR, 420 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 421 update_pci_byte(chip->pci, 422 NVIDIA_HDA_ISTRM_COH, 423 0x01, NVIDIA_HDA_ENABLE_COHBIT); 424 update_pci_byte(chip->pci, 425 NVIDIA_HDA_OSTRM_COH, 426 0x01, NVIDIA_HDA_ENABLE_COHBIT); 427 } 428 429 /* Enable SCH/PCH snoop if needed */ 430 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 431 unsigned short snoop; 432 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 433 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 434 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 435 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 436 if (!azx_snoop(chip)) 437 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 438 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 439 pci_read_config_word(chip->pci, 440 INTEL_SCH_HDA_DEVC, &snoop); 441 } 442 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 443 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 444 "Disabled" : "Enabled"); 445 } 446 } 447 448 /* 449 * In BXT-P A0, HD-Audio DMA requests is later than expected, 450 * and makes an audio stream sensitive to system latencies when 451 * 24/32 bits are playing. 452 * Adjusting threshold of DMA fifo to force the DMA request 453 * sooner to improve latency tolerance at the expense of power. 454 */ 455 static void bxt_reduce_dma_latency(struct azx *chip) 456 { 457 u32 val; 458 459 val = azx_readl(chip, VS_EM4L); 460 val &= (0x3 << 20); 461 azx_writel(chip, VS_EM4L, val); 462 } 463 464 /* 465 * ML_LCAP bits: 466 * bit 0: 6 MHz Supported 467 * bit 1: 12 MHz Supported 468 * bit 2: 24 MHz Supported 469 * bit 3: 48 MHz Supported 470 * bit 4: 96 MHz Supported 471 * bit 5: 192 MHz Supported 472 */ 473 static int intel_get_lctl_scf(struct azx *chip) 474 { 475 struct hdac_bus *bus = azx_bus(chip); 476 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 477 u32 val, t; 478 int i; 479 480 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 481 482 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 483 t = preferred_bits[i]; 484 if (val & (1 << t)) 485 return t; 486 } 487 488 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 489 return 0; 490 } 491 492 static int intel_ml_lctl_set_power(struct azx *chip, int state) 493 { 494 struct hdac_bus *bus = azx_bus(chip); 495 u32 val; 496 int timeout; 497 498 /* 499 * Changes to LCTL.SCF are only needed for the first multi-link dealing 500 * with external codecs 501 */ 502 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 503 val &= ~AZX_ML_LCTL_SPA; 504 val |= state << AZX_ML_LCTL_SPA_SHIFT; 505 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 506 /* wait for CPA */ 507 timeout = 50; 508 while (timeout) { 509 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 510 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT)) 511 return 0; 512 timeout--; 513 udelay(10); 514 } 515 516 return -1; 517 } 518 519 static void intel_init_lctl(struct azx *chip) 520 { 521 struct hdac_bus *bus = azx_bus(chip); 522 u32 val; 523 int ret; 524 525 /* 0. check lctl register value is correct or not */ 526 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 527 /* only perform additional configurations if the SCF is initially based on 6MHz */ 528 if ((val & AZX_ML_LCTL_SCF) != 0) 529 return; 530 531 /* 532 * Before operating on SPA, CPA must match SPA. 533 * Any deviation may result in undefined behavior. 534 */ 535 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) != 536 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT)) 537 return; 538 539 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 540 ret = intel_ml_lctl_set_power(chip, 0); 541 udelay(100); 542 if (ret) 543 goto set_spa; 544 545 /* 2. update SCF to select an audio clock different from 6MHz */ 546 val &= ~AZX_ML_LCTL_SCF; 547 val |= intel_get_lctl_scf(chip); 548 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 549 550 set_spa: 551 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 552 intel_ml_lctl_set_power(chip, 1); 553 udelay(100); 554 } 555 556 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 557 { 558 struct hdac_bus *bus = azx_bus(chip); 559 struct pci_dev *pci = chip->pci; 560 u32 val; 561 562 snd_hdac_set_codec_wakeup(bus, true); 563 if (chip->driver_type == AZX_DRIVER_SKL) { 564 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 565 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 566 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 567 } 568 azx_init_chip(chip, full_reset); 569 if (chip->driver_type == AZX_DRIVER_SKL) { 570 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 571 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 572 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 573 } 574 575 snd_hdac_set_codec_wakeup(bus, false); 576 577 /* reduce dma latency to avoid noise */ 578 if (HDA_CONTROLLER_IS_APL(pci)) 579 bxt_reduce_dma_latency(chip); 580 581 if (bus->mlcap != NULL) 582 intel_init_lctl(chip); 583 } 584 585 /* calculate runtime delay from LPIB */ 586 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 587 unsigned int pos) 588 { 589 struct snd_pcm_substream *substream = azx_dev->core.substream; 590 int stream = substream->stream; 591 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 592 int delay; 593 594 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 595 delay = pos - lpib_pos; 596 else 597 delay = lpib_pos - pos; 598 if (delay < 0) { 599 if (delay >= azx_dev->core.delay_negative_threshold) 600 delay = 0; 601 else 602 delay += azx_dev->core.bufsize; 603 } 604 605 if (delay >= azx_dev->core.period_bytes) { 606 dev_info(chip->card->dev, 607 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 608 delay, azx_dev->core.period_bytes); 609 delay = 0; 610 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 611 chip->get_delay[stream] = NULL; 612 } 613 614 return bytes_to_frames(substream->runtime, delay); 615 } 616 617 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 618 619 /* called from IRQ */ 620 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 621 { 622 struct hda_intel_stream *istream = azx_dev_to_istream(azx_dev); 623 int ok; 624 625 ok = azx_position_ok(chip, azx_dev); 626 if (ok == 1) { 627 istream->irq_pending = false; 628 return ok; 629 } else if (ok == 0) { 630 /* bogus IRQ, process it later */ 631 istream->irq_pending = true; 632 schedule_work(&istream->irq_pending_work); 633 } 634 return 0; 635 } 636 637 #define display_power(chip, enable) \ 638 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 639 640 /* 641 * Check whether the current DMA position is acceptable for updating 642 * periods. Returns non-zero if it's OK. 643 * 644 * Many HD-audio controllers appear pretty inaccurate about 645 * the update-IRQ timing. The IRQ is issued before actually the 646 * data is processed. So, we need to process it afterwords in a 647 * workqueue. 648 * 649 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update 650 */ 651 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 652 { 653 struct snd_pcm_substream *substream = azx_dev->core.substream; 654 struct snd_pcm_runtime *runtime = substream->runtime; 655 int stream = substream->stream; 656 u32 wallclk; 657 unsigned int pos; 658 snd_pcm_uframes_t hwptr, target; 659 660 /* 661 * The value of the WALLCLK register is always 0 662 * on the Loongson controller, so we return directly. 663 */ 664 if (chip->driver_type == AZX_DRIVER_LOONGSON) 665 return 1; 666 667 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 668 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 669 return -1; /* bogus (too early) interrupt */ 670 671 if (chip->get_position[stream]) 672 pos = chip->get_position[stream](chip, azx_dev); 673 else { /* use the position buffer as default */ 674 pos = azx_get_pos_posbuf(chip, azx_dev); 675 if (!pos || pos == (u32)-1) { 676 dev_info(chip->card->dev, 677 "Invalid position buffer, using LPIB read method instead.\n"); 678 chip->get_position[stream] = azx_get_pos_lpib; 679 if (chip->get_position[0] == azx_get_pos_lpib && 680 chip->get_position[1] == azx_get_pos_lpib) 681 azx_bus(chip)->use_posbuf = false; 682 pos = azx_get_pos_lpib(chip, azx_dev); 683 chip->get_delay[stream] = NULL; 684 } else { 685 chip->get_position[stream] = azx_get_pos_posbuf; 686 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 687 chip->get_delay[stream] = azx_get_delay_from_lpib; 688 } 689 } 690 691 if (pos >= azx_dev->core.bufsize) 692 pos = 0; 693 694 if (WARN_ONCE(!azx_dev->core.period_bytes, 695 "hda-intel: zero azx_dev->period_bytes")) 696 return -1; /* this shouldn't happen! */ 697 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 698 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 699 /* NG - it's below the first next period boundary */ 700 return chip->bdl_pos_adj ? 0 : -1; 701 azx_dev->core.start_wallclk += wallclk; 702 703 if (azx_dev->core.no_period_wakeup) 704 return 1; /* OK, no need to check period boundary */ 705 706 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt) 707 return 1; /* OK, already in hwptr updating process */ 708 709 /* check whether the period gets really elapsed */ 710 pos = bytes_to_frames(runtime, pos); 711 hwptr = runtime->hw_ptr_base + pos; 712 if (hwptr < runtime->status->hw_ptr) 713 hwptr += runtime->buffer_size; 714 target = runtime->hw_ptr_interrupt + runtime->period_size; 715 if (hwptr < target) { 716 /* too early wakeup, process it later */ 717 return chip->bdl_pos_adj ? 0 : -1; 718 } 719 720 return 1; /* OK, it's fine */ 721 } 722 723 /* 724 * The work for pending PCM period updates. 725 */ 726 static void azx_irq_pending_work(struct work_struct *work) 727 { 728 struct hda_intel_stream *istream = 729 container_of(work, struct hda_intel_stream, irq_pending_work); 730 struct azx_dev *azx_dev = &istream->azx_dev; 731 struct hda_intel *hda = istream->hda; 732 struct azx *chip = &hda->chip; 733 struct hdac_bus *bus = azx_bus(chip); 734 int ok; 735 736 if (!hda->irq_pending_warned) { 737 dev_info(chip->card->dev, 738 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 739 chip->card->number); 740 hda->irq_pending_warned = 1; 741 } 742 743 for (;;) { 744 scoped_guard(spinlock_irq, &bus->reg_lock) { 745 if (!istream->irq_pending || 746 !azx_dev->core.substream || 747 !azx_dev->core.running) { 748 return; 749 } 750 751 ok = azx_position_ok(chip, azx_dev); 752 if (ok < 0) 753 return; /* too early */ 754 if (ok > 0) 755 istream->irq_pending = false; 756 } 757 758 if (ok) { 759 snd_pcm_period_elapsed(azx_dev->core.substream); 760 return; 761 } 762 763 msleep(1); 764 } 765 } 766 767 /* clear irq_pending flags and assure no on-going workq */ 768 static void hda_intel_stream_clear_irq_pending(struct azx_dev *azx_dev) 769 { 770 struct hda_intel_stream *istream = azx_dev_to_istream(azx_dev); 771 772 istream->irq_pending = false; 773 cancel_work_sync(&istream->irq_pending_work); 774 } 775 776 /* called at PCM close */ 777 static void hda_intel_pcm_close(struct azx *chip, struct azx_dev *azx_dev) 778 { 779 hda_intel_stream_clear_irq_pending(azx_dev); 780 } 781 782 static void azx_clear_irq_pending(struct azx *chip) 783 { 784 struct hdac_bus *bus = azx_bus(chip); 785 struct hdac_stream *s; 786 787 list_for_each_entry(s, &bus->stream_list, list) { 788 hda_intel_stream_clear_irq_pending(stream_to_azx_dev(s)); 789 } 790 } 791 792 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 793 { 794 struct hdac_bus *bus = azx_bus(chip); 795 int ret; 796 797 if (!chip->msi || pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_MSI) < 0) { 798 ret = pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_INTX); 799 if (ret < 0) 800 return ret; 801 chip->msi = 0; 802 } 803 804 if (request_irq(chip->pci->irq, azx_interrupt, 805 chip->msi ? 0 : IRQF_SHARED, 806 chip->card->irq_descr, chip)) { 807 dev_err(chip->card->dev, 808 "unable to grab IRQ %d, disabling device\n", 809 chip->pci->irq); 810 if (do_disconnect) 811 snd_card_disconnect(chip->card); 812 return -1; 813 } 814 bus->irq = chip->pci->irq; 815 chip->card->sync_irq = bus->irq; 816 return 0; 817 } 818 819 /* get the current DMA position with correction on VIA chips */ 820 static unsigned int azx_via_get_position(struct azx *chip, 821 struct azx_dev *azx_dev) 822 { 823 unsigned int link_pos, mini_pos, bound_pos; 824 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 825 unsigned int fifo_size; 826 827 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 828 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 829 /* Playback, no problem using link position */ 830 return link_pos; 831 } 832 833 /* Capture */ 834 /* For new chipset, 835 * use mod to get the DMA position just like old chipset 836 */ 837 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 838 mod_dma_pos %= azx_dev->core.period_bytes; 839 840 fifo_size = azx_stream(azx_dev)->fifo_size; 841 842 if (azx_dev->insufficient) { 843 /* Link position never gather than FIFO size */ 844 if (link_pos <= fifo_size) 845 return 0; 846 847 azx_dev->insufficient = 0; 848 } 849 850 if (link_pos <= fifo_size) 851 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 852 else 853 mini_pos = link_pos - fifo_size; 854 855 /* Find nearest previous boudary */ 856 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 857 mod_link_pos = link_pos % azx_dev->core.period_bytes; 858 if (mod_link_pos >= fifo_size) 859 bound_pos = link_pos - mod_link_pos; 860 else if (mod_dma_pos >= mod_mini_pos) 861 bound_pos = mini_pos - mod_mini_pos; 862 else { 863 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 864 if (bound_pos >= azx_dev->core.bufsize) 865 bound_pos = 0; 866 } 867 868 /* Calculate real DMA position we want */ 869 return bound_pos + mod_dma_pos; 870 } 871 872 #define AMD_FIFO_SIZE 32 873 874 /* get the current DMA position with FIFO size correction */ 875 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 876 { 877 struct snd_pcm_substream *substream = azx_dev->core.substream; 878 struct snd_pcm_runtime *runtime = substream->runtime; 879 unsigned int pos, delay; 880 881 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 882 if (!runtime) 883 return pos; 884 885 runtime->delay = AMD_FIFO_SIZE; 886 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 887 if (azx_dev->insufficient) { 888 if (pos < delay) { 889 delay = pos; 890 runtime->delay = bytes_to_frames(runtime, pos); 891 } else { 892 azx_dev->insufficient = 0; 893 } 894 } 895 896 /* correct the DMA position for capture stream */ 897 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 898 if (pos < delay) 899 pos += azx_dev->core.bufsize; 900 pos -= delay; 901 } 902 903 return pos; 904 } 905 906 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 907 unsigned int pos) 908 { 909 struct snd_pcm_substream *substream = azx_dev->core.substream; 910 911 /* just read back the calculated value in the above */ 912 return substream->runtime->delay; 913 } 914 915 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset) 916 { 917 azx_stop_chip(chip); 918 if (!skip_link_reset) 919 azx_enter_link_reset(chip); 920 azx_clear_irq_pending(chip); 921 display_power(chip, false); 922 } 923 924 static DEFINE_MUTEX(card_list_lock); 925 static LIST_HEAD(card_list); 926 927 static void azx_shutdown_chip(struct azx *chip) 928 { 929 __azx_shutdown_chip(chip, false); 930 } 931 932 static void azx_add_card_list(struct azx *chip) 933 { 934 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 935 936 guard(mutex)(&card_list_lock); 937 list_add(&hda->list, &card_list); 938 } 939 940 static void azx_del_card_list(struct azx *chip) 941 { 942 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 943 944 guard(mutex)(&card_list_lock); 945 list_del_init(&hda->list); 946 } 947 948 /* trigger power-save check at writing parameter */ 949 static int __maybe_unused param_set_xint(const char *val, const struct kernel_param *kp) 950 { 951 struct hda_intel *hda; 952 struct azx *chip; 953 int prev = power_save; 954 int ret = param_set_int(val, kp); 955 956 if (ret || prev == power_save) 957 return ret; 958 959 if (pm_blacklist > 0) 960 return 0; 961 962 guard(mutex)(&card_list_lock); 963 list_for_each_entry(hda, &card_list, list) { 964 chip = &hda->chip; 965 if (!hda->probe_continued || chip->disabled || 966 hda->runtime_pm_disabled) 967 continue; 968 snd_hda_set_power_save(&chip->bus, power_save * 1000); 969 } 970 return 0; 971 } 972 973 /* 974 * power management 975 */ 976 static bool azx_is_pm_ready(struct snd_card *card) 977 { 978 struct azx *chip; 979 struct hda_intel *hda; 980 981 if (!card) 982 return false; 983 chip = card->private_data; 984 hda = container_of(chip, struct hda_intel, chip); 985 if (chip->disabled || hda->init_failed || !chip->running) 986 return false; 987 return true; 988 } 989 990 static void __azx_runtime_resume(struct azx *chip) 991 { 992 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 993 struct hdac_bus *bus = azx_bus(chip); 994 struct hda_codec *codec; 995 int status; 996 997 display_power(chip, true); 998 if (hda->need_i915_power) 999 snd_hdac_i915_set_bclk(bus); 1000 1001 /* Read STATESTS before controller reset */ 1002 status = azx_readw(chip, STATESTS); 1003 1004 azx_init_pci(chip); 1005 hda_intel_init_chip(chip, true); 1006 1007 /* Avoid codec resume if runtime resume is for system suspend */ 1008 if (!chip->pm_prepared) { 1009 list_for_each_codec(codec, &chip->bus) { 1010 if (codec->relaxed_resume) 1011 continue; 1012 1013 if (codec->forced_resume || (status & (1 << codec->addr))) 1014 pm_request_resume(hda_codec_dev(codec)); 1015 } 1016 } 1017 1018 /* power down again for link-controlled chips */ 1019 if (!hda->need_i915_power) 1020 display_power(chip, false); 1021 } 1022 1023 static int azx_prepare(struct device *dev) 1024 { 1025 struct snd_card *card = dev_get_drvdata(dev); 1026 struct azx *chip; 1027 1028 if (!azx_is_pm_ready(card)) 1029 return 0; 1030 1031 chip = card->private_data; 1032 chip->pm_prepared = 1; 1033 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1034 1035 flush_work(&azx_bus(chip)->unsol_work); 1036 1037 /* HDA controller always requires different WAKEEN for runtime suspend 1038 * and system suspend, so don't use direct-complete here. 1039 */ 1040 return 0; 1041 } 1042 1043 static void azx_complete(struct device *dev) 1044 { 1045 struct snd_card *card = dev_get_drvdata(dev); 1046 struct azx *chip; 1047 1048 if (!azx_is_pm_ready(card)) 1049 return; 1050 1051 chip = card->private_data; 1052 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1053 chip->pm_prepared = 0; 1054 } 1055 1056 static int azx_suspend(struct device *dev) 1057 { 1058 struct snd_card *card = dev_get_drvdata(dev); 1059 struct azx *chip; 1060 1061 if (!azx_is_pm_ready(card)) 1062 return 0; 1063 1064 chip = card->private_data; 1065 azx_shutdown_chip(chip); 1066 1067 trace_azx_suspend(chip); 1068 return 0; 1069 } 1070 1071 static int azx_resume(struct device *dev) 1072 { 1073 struct snd_card *card = dev_get_drvdata(dev); 1074 struct azx *chip; 1075 1076 if (!azx_is_pm_ready(card)) 1077 return 0; 1078 1079 chip = card->private_data; 1080 1081 __azx_runtime_resume(chip); 1082 1083 trace_azx_resume(chip); 1084 return 0; 1085 } 1086 1087 /* put codec down to D3 at hibernation for Intel SKL+; 1088 * otherwise BIOS may still access the codec and screw up the driver 1089 */ 1090 static int azx_freeze_noirq(struct device *dev) 1091 { 1092 struct snd_card *card = dev_get_drvdata(dev); 1093 struct azx *chip = card->private_data; 1094 struct pci_dev *pci = to_pci_dev(dev); 1095 1096 if (!azx_is_pm_ready(card)) 1097 return 0; 1098 if (chip->driver_type == AZX_DRIVER_SKL) 1099 pci_set_power_state(pci, PCI_D3hot); 1100 1101 return 0; 1102 } 1103 1104 static int azx_thaw_noirq(struct device *dev) 1105 { 1106 struct snd_card *card = dev_get_drvdata(dev); 1107 struct azx *chip = card->private_data; 1108 struct pci_dev *pci = to_pci_dev(dev); 1109 1110 if (!azx_is_pm_ready(card)) 1111 return 0; 1112 if (chip->driver_type == AZX_DRIVER_SKL) 1113 pci_set_power_state(pci, PCI_D0); 1114 1115 return 0; 1116 } 1117 1118 static int azx_runtime_suspend(struct device *dev) 1119 { 1120 struct snd_card *card = dev_get_drvdata(dev); 1121 struct azx *chip; 1122 1123 if (!azx_is_pm_ready(card)) 1124 return 0; 1125 chip = card->private_data; 1126 1127 /* enable controller wake up event */ 1128 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); 1129 1130 azx_shutdown_chip(chip); 1131 trace_azx_runtime_suspend(chip); 1132 return 0; 1133 } 1134 1135 static int azx_runtime_resume(struct device *dev) 1136 { 1137 struct snd_card *card = dev_get_drvdata(dev); 1138 struct azx *chip; 1139 1140 if (!azx_is_pm_ready(card)) 1141 return 0; 1142 chip = card->private_data; 1143 __azx_runtime_resume(chip); 1144 1145 /* disable controller Wake Up event*/ 1146 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); 1147 1148 trace_azx_runtime_resume(chip); 1149 return 0; 1150 } 1151 1152 static int azx_runtime_idle(struct device *dev) 1153 { 1154 struct snd_card *card = dev_get_drvdata(dev); 1155 struct azx *chip; 1156 struct hda_intel *hda; 1157 1158 if (!card) 1159 return 0; 1160 1161 chip = card->private_data; 1162 hda = container_of(chip, struct hda_intel, chip); 1163 if (chip->disabled || hda->init_failed) 1164 return 0; 1165 1166 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1167 azx_bus(chip)->codec_powered || !chip->running) 1168 return -EBUSY; 1169 1170 /* ELD notification gets broken when HD-audio bus is off */ 1171 if (needs_eld_notify_link(chip)) 1172 return -EBUSY; 1173 1174 return 0; 1175 } 1176 1177 static const struct dev_pm_ops azx_pm = { 1178 SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1179 .prepare = pm_sleep_ptr(azx_prepare), 1180 .complete = pm_sleep_ptr(azx_complete), 1181 .freeze_noirq = pm_sleep_ptr(azx_freeze_noirq), 1182 .thaw_noirq = pm_sleep_ptr(azx_thaw_noirq), 1183 RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1184 }; 1185 1186 1187 static int azx_probe_continue(struct azx *chip); 1188 1189 #ifdef SUPPORT_VGA_SWITCHEROO 1190 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1191 1192 static void azx_vs_set_state(struct pci_dev *pci, 1193 enum vga_switcheroo_state state) 1194 { 1195 struct snd_card *card = pci_get_drvdata(pci); 1196 struct azx *chip = card->private_data; 1197 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1198 struct hda_codec *codec; 1199 bool disabled; 1200 1201 wait_for_completion(&hda->probe_wait); 1202 if (hda->init_failed) 1203 return; 1204 1205 disabled = (state == VGA_SWITCHEROO_OFF); 1206 if (chip->disabled == disabled) 1207 return; 1208 1209 if (!hda->probe_continued) { 1210 chip->disabled = disabled; 1211 if (!disabled) { 1212 dev_info(chip->card->dev, 1213 "Start delayed initialization\n"); 1214 if (azx_probe_continue(chip) < 0) 1215 dev_err(chip->card->dev, "initialization error\n"); 1216 } 1217 } else { 1218 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1219 disabled ? "Disabling" : "Enabling"); 1220 if (disabled) { 1221 list_for_each_codec(codec, &chip->bus) { 1222 pm_runtime_suspend(hda_codec_dev(codec)); 1223 pm_runtime_disable(hda_codec_dev(codec)); 1224 } 1225 pm_runtime_suspend(card->dev); 1226 pm_runtime_disable(card->dev); 1227 /* when we get suspended by vga_switcheroo we end up in D3cold, 1228 * however we have no ACPI handle, so pci/acpi can't put us there, 1229 * put ourselves there */ 1230 pci->current_state = PCI_D3cold; 1231 chip->disabled = true; 1232 if (snd_hda_lock_devices(&chip->bus)) 1233 dev_warn(chip->card->dev, 1234 "Cannot lock devices!\n"); 1235 } else { 1236 snd_hda_unlock_devices(&chip->bus); 1237 chip->disabled = false; 1238 pm_runtime_enable(card->dev); 1239 list_for_each_codec(codec, &chip->bus) { 1240 pm_runtime_enable(hda_codec_dev(codec)); 1241 pm_runtime_resume(hda_codec_dev(codec)); 1242 } 1243 } 1244 } 1245 } 1246 1247 static bool azx_vs_can_switch(struct pci_dev *pci) 1248 { 1249 struct snd_card *card = pci_get_drvdata(pci); 1250 struct azx *chip = card->private_data; 1251 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1252 1253 wait_for_completion(&hda->probe_wait); 1254 if (hda->init_failed) 1255 return false; 1256 if (chip->disabled || !hda->probe_continued) 1257 return true; 1258 if (snd_hda_lock_devices(&chip->bus)) 1259 return false; 1260 snd_hda_unlock_devices(&chip->bus); 1261 return true; 1262 } 1263 1264 /* 1265 * The discrete GPU cannot power down unless the HDA controller runtime 1266 * suspends, so activate runtime PM on codecs even if power_save == 0. 1267 */ 1268 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1269 { 1270 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1271 struct hda_codec *codec; 1272 1273 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1274 list_for_each_codec(codec, &chip->bus) 1275 codec->auto_runtime_pm = 1; 1276 /* reset the power save setup */ 1277 if (chip->running) 1278 set_default_power_save(chip); 1279 } 1280 } 1281 1282 static void azx_vs_gpu_bound(struct pci_dev *pci, 1283 enum vga_switcheroo_client_id client_id) 1284 { 1285 struct snd_card *card = pci_get_drvdata(pci); 1286 struct azx *chip = card->private_data; 1287 1288 if (client_id == VGA_SWITCHEROO_DIS) 1289 chip->bus.keep_power = 0; 1290 setup_vga_switcheroo_runtime_pm(chip); 1291 } 1292 1293 static void init_vga_switcheroo(struct azx *chip) 1294 { 1295 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1296 struct pci_dev *p = get_bound_vga(chip->pci); 1297 struct pci_dev *parent; 1298 if (p) { 1299 dev_info(chip->card->dev, 1300 "Handle vga_switcheroo audio client\n"); 1301 hda->use_vga_switcheroo = 1; 1302 1303 /* cleared in either gpu_bound op or codec probe, or when its 1304 * upstream port has _PR3 (i.e. dGPU). 1305 */ 1306 parent = pci_upstream_bridge(p); 1307 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1308 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1309 pci_dev_put(p); 1310 } 1311 } 1312 1313 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1314 .set_gpu_state = azx_vs_set_state, 1315 .can_switch = azx_vs_can_switch, 1316 .gpu_bound = azx_vs_gpu_bound, 1317 }; 1318 1319 static int register_vga_switcheroo(struct azx *chip) 1320 { 1321 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1322 struct pci_dev *p; 1323 int err; 1324 1325 if (!hda->use_vga_switcheroo) 1326 return 0; 1327 1328 p = get_bound_vga(chip->pci); 1329 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1330 pci_dev_put(p); 1331 1332 if (err < 0) 1333 return err; 1334 hda->vga_switcheroo_registered = 1; 1335 1336 return 0; 1337 } 1338 #else 1339 #define init_vga_switcheroo(chip) /* NOP */ 1340 #define register_vga_switcheroo(chip) 0 1341 #define check_hdmi_disabled(pci) false 1342 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1343 #endif /* SUPPORT_VGA_SWITCHER */ 1344 1345 /* 1346 * destructor 1347 */ 1348 static void azx_free(struct azx *chip) 1349 { 1350 struct pci_dev *pci = chip->pci; 1351 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1352 struct hdac_bus *bus = azx_bus(chip); 1353 1354 if (hda->freed) 1355 return; 1356 1357 if (azx_has_pm_runtime(chip) && chip->running) { 1358 pm_runtime_get_noresume(&pci->dev); 1359 pm_runtime_forbid(&pci->dev); 1360 pm_runtime_dont_use_autosuspend(&pci->dev); 1361 } 1362 1363 chip->running = 0; 1364 1365 azx_del_card_list(chip); 1366 1367 hda->init_failed = 1; /* to be sure */ 1368 complete_all(&hda->probe_wait); 1369 1370 if (use_vga_switcheroo(hda)) { 1371 if (chip->disabled && hda->probe_continued) 1372 snd_hda_unlock_devices(&chip->bus); 1373 if (hda->vga_switcheroo_registered) { 1374 vga_switcheroo_unregister_client(chip->pci); 1375 1376 /* Some GPUs don't have sound, and azx_first_init fails, 1377 * leaving the device probed but non-functional. As long 1378 * as it's probed, the PCI subsystem keeps its runtime 1379 * PM status as active. Force it to suspended (as we 1380 * actually stop the chip) to allow GPU to suspend via 1381 * vga_switcheroo, and print a warning. 1382 */ 1383 dev_warn(&pci->dev, "GPU sound probed, but not operational: please add a quirk to driver_denylist\n"); 1384 pm_runtime_disable(&pci->dev); 1385 pm_runtime_set_suspended(&pci->dev); 1386 pm_runtime_enable(&pci->dev); 1387 } 1388 } 1389 1390 if (bus->chip_init) { 1391 azx_clear_irq_pending(chip); 1392 azx_stop_all_streams(chip); 1393 azx_stop_chip(chip); 1394 } 1395 1396 if (bus->irq >= 0) 1397 free_irq(bus->irq, (void*)chip); 1398 1399 azx_free_stream_pages(chip); 1400 azx_free_streams(chip); 1401 snd_hdac_bus_exit(bus); 1402 1403 display_power(chip, false); 1404 1405 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1406 snd_hdac_i915_exit(bus); 1407 1408 hda->freed = 1; 1409 } 1410 1411 static int azx_dev_disconnect(struct snd_device *device) 1412 { 1413 struct azx *chip = device->device_data; 1414 struct hdac_bus *bus = azx_bus(chip); 1415 1416 chip->bus.shutdown = 1; 1417 cancel_work_sync(&bus->unsol_work); 1418 1419 return 0; 1420 } 1421 1422 static int azx_dev_free(struct snd_device *device) 1423 { 1424 azx_free(device->device_data); 1425 return 0; 1426 } 1427 1428 #ifdef SUPPORT_VGA_SWITCHEROO 1429 #ifdef CONFIG_ACPI 1430 /* ATPX is in the integrated GPU's namespace */ 1431 static bool atpx_present(void) 1432 { 1433 struct pci_dev *pdev = NULL; 1434 acpi_handle dhandle, atpx_handle; 1435 acpi_status status; 1436 1437 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) { 1438 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) && 1439 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8)) 1440 continue; 1441 1442 dhandle = ACPI_HANDLE(&pdev->dev); 1443 if (dhandle) { 1444 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1445 if (ACPI_SUCCESS(status)) { 1446 pci_dev_put(pdev); 1447 return true; 1448 } 1449 } 1450 } 1451 return false; 1452 } 1453 #else 1454 static bool atpx_present(void) 1455 { 1456 return false; 1457 } 1458 #endif 1459 1460 /* 1461 * Check of disabled HDMI controller by vga_switcheroo 1462 */ 1463 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1464 { 1465 struct pci_dev *p; 1466 1467 /* check only discrete GPU */ 1468 switch (pci->vendor) { 1469 case PCI_VENDOR_ID_ATI: 1470 case PCI_VENDOR_ID_AMD: 1471 if (pci->devfn == 1) { 1472 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1473 pci->bus->number, 0); 1474 if (p) { 1475 /* ATPX is in the integrated GPU's ACPI namespace 1476 * rather than the dGPU's namespace. However, 1477 * the dGPU is the one who is involved in 1478 * vgaswitcheroo. 1479 */ 1480 if (pci_is_display(p) && 1481 (atpx_present() || apple_gmux_detect(NULL, NULL))) 1482 return p; 1483 pci_dev_put(p); 1484 } 1485 } 1486 break; 1487 case PCI_VENDOR_ID_NVIDIA: 1488 if (pci->devfn == 1) { 1489 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1490 pci->bus->number, 0); 1491 if (p) { 1492 if (pci_is_display(p)) 1493 return p; 1494 pci_dev_put(p); 1495 } 1496 } 1497 break; 1498 } 1499 return NULL; 1500 } 1501 1502 static bool check_hdmi_disabled(struct pci_dev *pci) 1503 { 1504 bool vga_inactive = false; 1505 struct pci_dev *p = get_bound_vga(pci); 1506 1507 if (p) { 1508 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1509 vga_inactive = true; 1510 pci_dev_put(p); 1511 } 1512 return vga_inactive; 1513 } 1514 #endif /* SUPPORT_VGA_SWITCHEROO */ 1515 1516 /* 1517 * allow/deny-listing for position_fix 1518 */ 1519 static const struct snd_pci_quirk position_fix_list[] = { 1520 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1521 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1522 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1523 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1524 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1525 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1526 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1527 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1528 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1529 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1530 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1531 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1532 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1533 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1534 {} 1535 }; 1536 1537 static int check_position_fix(struct azx *chip, int fix) 1538 { 1539 const struct snd_pci_quirk *q; 1540 1541 switch (fix) { 1542 case POS_FIX_AUTO: 1543 case POS_FIX_LPIB: 1544 case POS_FIX_POSBUF: 1545 case POS_FIX_VIACOMBO: 1546 case POS_FIX_COMBO: 1547 case POS_FIX_SKL: 1548 case POS_FIX_FIFO: 1549 return fix; 1550 } 1551 1552 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1553 if (q) { 1554 dev_info(chip->card->dev, 1555 "position_fix set to %d for device %04x:%04x\n", 1556 q->value, q->subvendor, q->subdevice); 1557 return q->value; 1558 } 1559 1560 /* Check VIA/ATI HD Audio Controller exist */ 1561 if (chip->driver_type == AZX_DRIVER_VIA) { 1562 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1563 return POS_FIX_VIACOMBO; 1564 } 1565 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1566 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1567 return POS_FIX_FIFO; 1568 } 1569 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1570 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1571 return POS_FIX_LPIB; 1572 } 1573 if (chip->driver_type == AZX_DRIVER_SKL) { 1574 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1575 return POS_FIX_SKL; 1576 } 1577 return POS_FIX_AUTO; 1578 } 1579 1580 static void assign_position_fix(struct azx *chip, int fix) 1581 { 1582 static const azx_get_pos_callback_t callbacks[] = { 1583 [POS_FIX_AUTO] = NULL, 1584 [POS_FIX_LPIB] = azx_get_pos_lpib, 1585 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1586 [POS_FIX_VIACOMBO] = azx_via_get_position, 1587 [POS_FIX_COMBO] = azx_get_pos_lpib, 1588 [POS_FIX_SKL] = azx_get_pos_posbuf, 1589 [POS_FIX_FIFO] = azx_get_pos_fifo, 1590 }; 1591 1592 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1593 1594 /* combo mode uses LPIB only for playback */ 1595 if (fix == POS_FIX_COMBO) 1596 chip->get_position[1] = NULL; 1597 1598 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1599 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1600 chip->get_delay[0] = chip->get_delay[1] = 1601 azx_get_delay_from_lpib; 1602 } 1603 1604 if (fix == POS_FIX_FIFO) 1605 chip->get_delay[0] = chip->get_delay[1] = 1606 azx_get_delay_from_fifo; 1607 } 1608 1609 /* 1610 * deny-lists for probe_mask 1611 */ 1612 static const struct snd_pci_quirk probe_mask_list[] = { 1613 /* Thinkpad often breaks the controller communication when accessing 1614 * to the non-working (or non-existing) modem codec slot. 1615 */ 1616 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1617 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1618 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1619 /* broken BIOS */ 1620 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1621 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1622 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1623 /* forced codec slots */ 1624 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1625 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1626 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105), 1627 /* WinFast VP200 H (Teradici) user reported broken communication */ 1628 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1629 {} 1630 }; 1631 1632 #define AZX_FORCE_CODEC_MASK 0x100 1633 1634 static void check_probe_mask(struct azx *chip, int dev) 1635 { 1636 const struct snd_pci_quirk *q; 1637 1638 chip->codec_probe_mask = probe_mask[dev]; 1639 if (chip->codec_probe_mask == -1) { 1640 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1641 if (q) { 1642 dev_info(chip->card->dev, 1643 "probe_mask set to 0x%x for device %04x:%04x\n", 1644 q->value, q->subvendor, q->subdevice); 1645 chip->codec_probe_mask = q->value; 1646 } 1647 } 1648 1649 /* check forced option */ 1650 if (chip->codec_probe_mask != -1 && 1651 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1652 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1653 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1654 (int)azx_bus(chip)->codec_mask); 1655 } 1656 } 1657 1658 /* 1659 * allow/deny-list for enable_msi 1660 */ 1661 static const struct snd_pci_quirk msi_deny_list[] = { 1662 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1663 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1664 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1665 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1666 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1667 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1668 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1669 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1670 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1671 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1672 {} 1673 }; 1674 1675 static void check_msi(struct azx *chip) 1676 { 1677 const struct snd_pci_quirk *q; 1678 1679 if (enable_msi >= 0) { 1680 chip->msi = !!enable_msi; 1681 return; 1682 } 1683 chip->msi = 1; /* enable MSI as default */ 1684 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); 1685 if (q) { 1686 dev_info(chip->card->dev, 1687 "msi for device %04x:%04x set to %d\n", 1688 q->subvendor, q->subdevice, q->value); 1689 chip->msi = q->value; 1690 return; 1691 } 1692 1693 /* NVidia chipsets seem to cause troubles with MSI */ 1694 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1695 dev_info(chip->card->dev, "Disabling MSI\n"); 1696 chip->msi = 0; 1697 } 1698 } 1699 1700 /* check the snoop mode availability */ 1701 static void azx_check_snoop_available(struct azx *chip) 1702 { 1703 int snoop = hda_snoop; 1704 1705 if (snoop >= 0) { 1706 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1707 snoop ? "snoop" : "non-snoop"); 1708 chip->snoop = snoop; 1709 chip->uc_buffer = !snoop; 1710 return; 1711 } 1712 1713 snoop = true; 1714 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1715 chip->driver_type == AZX_DRIVER_VIA) { 1716 /* force to non-snoop mode for a new VIA controller 1717 * when BIOS is set 1718 */ 1719 u8 val; 1720 pci_read_config_byte(chip->pci, 0x42, &val); 1721 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1722 chip->pci->revision == 0x20)) 1723 snoop = false; 1724 } 1725 1726 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1727 snoop = false; 1728 1729 chip->snoop = snoop; 1730 if (!snoop) { 1731 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1732 /* C-Media requires non-cached pages only for CORB/RIRB */ 1733 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1734 chip->uc_buffer = true; 1735 } 1736 } 1737 1738 static void azx_probe_work(struct work_struct *work) 1739 { 1740 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work); 1741 azx_probe_continue(&hda->chip); 1742 } 1743 1744 static int default_bdl_pos_adj(struct azx *chip) 1745 { 1746 /* some exceptions: Atoms seem problematic with value 1 */ 1747 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1748 switch (chip->pci->device) { 1749 case PCI_DEVICE_ID_INTEL_HDA_BYT: 1750 case PCI_DEVICE_ID_INTEL_HDA_BSW: 1751 return 32; 1752 case PCI_DEVICE_ID_INTEL_HDA_APL: 1753 return 64; 1754 } 1755 } 1756 1757 switch (chip->driver_type) { 1758 /* 1759 * increase the bdl size for Glenfly Gpus for hardware 1760 * limitation on hdac interrupt interval 1761 */ 1762 case AZX_DRIVER_GFHDMI: 1763 return 128; 1764 case AZX_DRIVER_ICH: 1765 case AZX_DRIVER_PCH: 1766 return 1; 1767 case AZX_DRIVER_ZHAOXINHDMI: 1768 return 128; 1769 case AZX_DRIVER_NVIDIA: 1770 return 64; 1771 default: 1772 return 32; 1773 } 1774 } 1775 1776 /* 1777 * constructor 1778 */ 1779 static const struct hda_controller_ops pci_hda_ops; 1780 1781 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1782 int dev, unsigned int driver_caps, 1783 struct azx **rchip) 1784 { 1785 static const struct snd_device_ops ops = { 1786 .dev_disconnect = azx_dev_disconnect, 1787 .dev_free = azx_dev_free, 1788 }; 1789 struct hda_intel *hda; 1790 struct azx *chip; 1791 int err; 1792 1793 *rchip = NULL; 1794 1795 err = pcim_enable_device(pci); 1796 if (err < 0) 1797 return err; 1798 1799 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1800 if (!hda) 1801 return -ENOMEM; 1802 1803 chip = &hda->chip; 1804 mutex_init(&chip->open_mutex); 1805 chip->card = card; 1806 chip->pci = pci; 1807 chip->ops = &pci_hda_ops; 1808 chip->driver_caps = driver_caps; 1809 chip->driver_type = driver_caps & 0xff; 1810 check_msi(chip); 1811 chip->dev_index = dev; 1812 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1813 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1814 INIT_LIST_HEAD(&chip->pcm_list); 1815 INIT_LIST_HEAD(&hda->list); 1816 init_vga_switcheroo(chip); 1817 init_completion(&hda->probe_wait); 1818 1819 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1820 1821 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1822 chip->fallback_to_single_cmd = 1; 1823 else /* explicitly set to single_cmd or not */ 1824 chip->single_cmd = single_cmd; 1825 1826 azx_check_snoop_available(chip); 1827 1828 if (bdl_pos_adj[dev] < 0) 1829 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1830 else 1831 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1832 1833 err = azx_bus_init(chip, model[dev]); 1834 if (err < 0) 1835 return err; 1836 1837 /* use the non-cached pages in non-snoop mode */ 1838 if (!azx_snoop(chip)) 1839 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC; 1840 1841 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1842 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1843 chip->bus.core.needs_damn_long_delay = 1; 1844 } 1845 1846 check_probe_mask(chip, dev); 1847 1848 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1849 if (err < 0) { 1850 dev_err(card->dev, "Error creating device [card]!\n"); 1851 azx_free(chip); 1852 return err; 1853 } 1854 1855 /* continue probing in work context as may trigger request module */ 1856 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work); 1857 1858 *rchip = chip; 1859 1860 return 0; 1861 } 1862 1863 /* create and assign streams */ 1864 static int hda_init_streams(struct azx *chip) 1865 { 1866 int i; 1867 int stream_tags[2] = { 0, 0 }; 1868 1869 for (i = 0; i < chip->num_streams; i++) { 1870 struct hda_intel_stream *s = kzalloc_obj(*s); 1871 int tag, dir; 1872 1873 if (!s) 1874 return -ENOMEM; 1875 1876 s->hda = container_of(chip, struct hda_intel, chip); 1877 INIT_WORK(&s->irq_pending_work, azx_irq_pending_work); 1878 1879 /* stream tag must be unique throughout 1880 * the stream direction group, 1881 * valid values 1...15 1882 * use separate stream tag if the flag 1883 * AZX_DCAPS_SEPARATE_STREAM_TAG is used 1884 */ 1885 dir = azx_stream_direction(chip, i); 1886 if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) 1887 tag = ++stream_tags[dir]; 1888 else 1889 tag = i + 1; 1890 azx_add_stream(chip, &s->azx_dev, i, tag); 1891 } 1892 1893 return 0; 1894 } 1895 1896 static int azx_first_init(struct azx *chip) 1897 { 1898 int dev = chip->dev_index; 1899 struct pci_dev *pci = chip->pci; 1900 struct snd_card *card = chip->card; 1901 struct hdac_bus *bus = azx_bus(chip); 1902 int err; 1903 unsigned short gcap; 1904 unsigned int dma_bits = 64; 1905 1906 #if BITS_PER_LONG != 64 1907 /* Fix up base address on ULI M5461 */ 1908 if (chip->driver_type == AZX_DRIVER_ULI) { 1909 u16 tmp3; 1910 pci_read_config_word(pci, 0x40, &tmp3); 1911 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1912 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1913 } 1914 #endif 1915 /* 1916 * Fix response write request not synced to memory when handle 1917 * hdac interrupt on Glenfly Gpus 1918 */ 1919 if (chip->driver_type == AZX_DRIVER_GFHDMI) 1920 bus->polling_mode = 1; 1921 1922 if (chip->driver_type == AZX_DRIVER_LOONGSON) { 1923 bus->polling_mode = 1; 1924 bus->not_use_interrupts = 1; 1925 bus->access_sdnctl_in_dword = 1; 1926 if (!chip->jackpoll_interval) 1927 chip->jackpoll_interval = msecs_to_jiffies(1500); 1928 } 1929 1930 if (chip->driver_type == AZX_DRIVER_ZHAOXINHDMI) 1931 bus->polling_mode = 1; 1932 1933 if (chip->driver_type == AZX_DRIVER_HYGON && 1934 chip->pci->device == PCI_DEVICE_ID_HYGON_18H_M05H_HDA) 1935 bus->access_sdnctl_in_dword = 1; 1936 1937 bus->remap_addr = pcim_iomap_region(pci, 0, "ICH HD audio"); 1938 if (IS_ERR(bus->remap_addr)) 1939 return PTR_ERR(bus->remap_addr); 1940 1941 bus->addr = pci_resource_start(pci, 0); 1942 1943 if (chip->driver_type == AZX_DRIVER_SKL) 1944 snd_hdac_bus_parse_capabilities(bus); 1945 1946 /* 1947 * Some Intel CPUs has always running timer (ART) feature and 1948 * controller may have Global time sync reporting capability, so 1949 * check both of these before declaring synchronized time reporting 1950 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1951 */ 1952 chip->gts_present = false; 1953 1954 #ifdef CONFIG_X86 1955 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1956 chip->gts_present = true; 1957 #endif 1958 1959 pci_set_master(pci); 1960 1961 gcap = azx_readw(chip, GCAP); 1962 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1963 1964 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1965 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1966 dma_bits = 40; 1967 1968 /* disable SB600 64bit support for safety */ 1969 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1970 struct pci_dev *p_smbus; 1971 dma_bits = 40; 1972 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1973 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1974 NULL); 1975 if (p_smbus) { 1976 if (p_smbus->revision < 0x30) 1977 gcap &= ~AZX_GCAP_64OK; 1978 pci_dev_put(p_smbus); 1979 } 1980 } 1981 1982 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1983 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1984 dma_bits = 40; 1985 1986 /* disable 64bit DMA address on some devices */ 1987 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1988 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1989 gcap &= ~AZX_GCAP_64OK; 1990 } 1991 1992 /* disable buffer size rounding to 128-byte multiples if supported */ 1993 if (align_buffer_size >= 0) 1994 chip->align_buffer_size = !!align_buffer_size; 1995 else { 1996 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1997 chip->align_buffer_size = 0; 1998 else 1999 chip->align_buffer_size = 1; 2000 } 2001 2002 /* allow 64bit DMA address if supported by H/W */ 2003 if (!(gcap & AZX_GCAP_64OK)) 2004 dma_bits = 32; 2005 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) 2006 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 2007 dma_set_max_seg_size(&pci->dev, UINT_MAX); 2008 2009 if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { 2010 dev_dbg(card->dev, "Restricting MSI to %u-bit\n", dma_bits); 2011 pci->msi_addr_mask = DMA_BIT_MASK(dma_bits); 2012 } 2013 2014 /* read number of streams from GCAP register instead of using 2015 * hardcoded value 2016 */ 2017 chip->capture_streams = (gcap >> 8) & 0x0f; 2018 chip->playback_streams = (gcap >> 12) & 0x0f; 2019 if (!chip->playback_streams && !chip->capture_streams) { 2020 /* gcap didn't give any info, switching to old method */ 2021 2022 switch (chip->driver_type) { 2023 case AZX_DRIVER_ULI: 2024 chip->playback_streams = ULI_NUM_PLAYBACK; 2025 chip->capture_streams = ULI_NUM_CAPTURE; 2026 break; 2027 case AZX_DRIVER_ATIHDMI: 2028 case AZX_DRIVER_ATIHDMI_NS: 2029 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 2030 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 2031 break; 2032 case AZX_DRIVER_GFHDMI: 2033 case AZX_DRIVER_ZHAOXINHDMI: 2034 case AZX_DRIVER_GENERIC: 2035 default: 2036 chip->playback_streams = ICH6_NUM_PLAYBACK; 2037 chip->capture_streams = ICH6_NUM_CAPTURE; 2038 break; 2039 } 2040 } 2041 chip->capture_index_offset = 0; 2042 chip->playback_index_offset = chip->capture_streams; 2043 chip->num_streams = chip->playback_streams + chip->capture_streams; 2044 2045 /* sanity check for the SDxCTL.STRM field overflow */ 2046 if (chip->num_streams > 15 && 2047 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 2048 dev_warn(chip->card->dev, "number of I/O streams is %d, " 2049 "forcing separate stream tags", chip->num_streams); 2050 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 2051 } 2052 2053 /* initialize streams */ 2054 err = hda_init_streams(chip); 2055 if (err < 0) 2056 return err; 2057 2058 err = azx_alloc_stream_pages(chip); 2059 if (err < 0) 2060 return err; 2061 2062 /* initialize chip */ 2063 azx_init_pci(chip); 2064 2065 snd_hdac_i915_set_bclk(bus); 2066 2067 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 2068 2069 /* codec detection */ 2070 if (!azx_bus(chip)->codec_mask) { 2071 dev_err(card->dev, "no codecs found!\n"); 2072 /* keep running the rest for the runtime PM */ 2073 } 2074 2075 if (azx_acquire_irq(chip, 0) < 0) 2076 return -EBUSY; 2077 2078 strscpy(card->driver, "HDA-Intel"); 2079 strscpy(card->shortname, driver_short_names[chip->driver_type], 2080 sizeof(card->shortname)); 2081 snprintf(card->longname, sizeof(card->longname), 2082 "%s at 0x%lx irq %i", 2083 card->shortname, bus->addr, bus->irq); 2084 2085 return 0; 2086 } 2087 2088 static int disable_msi_reset_irq(struct azx *chip) 2089 { 2090 struct hdac_bus *bus = azx_bus(chip); 2091 int err; 2092 2093 free_irq(bus->irq, chip); 2094 bus->irq = -1; 2095 chip->card->sync_irq = -1; 2096 pci_free_irq_vectors(chip->pci); 2097 chip->msi = 0; 2098 err = azx_acquire_irq(chip, 1); 2099 if (err < 0) 2100 return err; 2101 2102 return 0; 2103 } 2104 2105 /* Denylist for skipping the whole probe: 2106 * some HD-audio PCI entries are exposed without any codecs, and such devices 2107 * should be ignored from the beginning. 2108 */ 2109 static const struct pci_device_id driver_denylist[] = { 2110 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2111 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2112 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2113 {} 2114 }; 2115 2116 static struct pci_device_id driver_denylist_ideapad_z570[] = { 2117 { PCI_DEVICE_SUB(0x10de, 0x0bea, 0x0000, 0x0000) }, /* NVIDIA GF108 HDA */ 2118 {} 2119 }; 2120 2121 static struct pci_device_id driver_denylist_msi_x870e[] = { 2122 { PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1462, 0xee59) }, /* MSI X870E Tomahawk WiFi */ 2123 {} 2124 }; 2125 2126 /* DMI-based denylist, to be used when: 2127 * - PCI subsystem IDs are zero, impossible to distinguish from valid sound cards. 2128 * - Different modifications of the same laptop use different GPU models. 2129 */ 2130 static const struct dmi_system_id driver_denylist_dmi[] = { 2131 { 2132 /* No HDA in NVIDIA DGPU. BIOS disables it, but quirk_nvidia_hda() reenables. */ 2133 .matches = { 2134 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 2135 DMI_MATCH(DMI_PRODUCT_VERSION, "Ideapad Z570"), 2136 }, 2137 .driver_data = &driver_denylist_ideapad_z570, 2138 }, 2139 { 2140 /* PCI device matching alone incorrectly matches some laptops */ 2141 .matches = { 2142 DMI_MATCH(DMI_BOARD_VENDOR, "Micro-Star International Co., Ltd."), 2143 DMI_MATCH(DMI_BOARD_NAME, "MAG X870E TOMAHAWK WIFI (MS-7E59)"), 2144 }, 2145 .driver_data = &driver_denylist_msi_x870e, 2146 }, 2147 {} 2148 }; 2149 2150 static const struct hda_controller_ops pci_hda_ops = { 2151 .disable_msi_reset_irq = disable_msi_reset_irq, 2152 .position_check = azx_position_check, 2153 .pcm_close = hda_intel_pcm_close, 2154 }; 2155 2156 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS); 2157 2158 static int azx_probe(struct pci_dev *pci, 2159 const struct pci_device_id *pci_id) 2160 { 2161 const struct dmi_system_id *dmi; 2162 struct snd_card *card; 2163 struct hda_intel *hda; 2164 struct azx *chip; 2165 int dev; 2166 int err; 2167 2168 if (pci_match_id(driver_denylist, pci)) { 2169 dev_info(&pci->dev, "Skipping the device on the denylist\n"); 2170 return -ENODEV; 2171 } 2172 2173 dmi = dmi_first_match(driver_denylist_dmi); 2174 if (dmi && pci_match_id(dmi->driver_data, pci)) { 2175 dev_info(&pci->dev, "Skipping the device on the DMI denylist\n"); 2176 return -ENODEV; 2177 } 2178 2179 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS); 2180 if (dev >= SNDRV_CARDS) 2181 return -ENODEV; 2182 if (!enable[dev]) { 2183 set_bit(dev, probed_devs); 2184 return -ENOENT; 2185 } 2186 2187 /* 2188 * stop probe if another Intel's DSP driver should be activated 2189 */ 2190 if (dmic_detect) { 2191 err = snd_intel_dsp_driver_probe(pci); 2192 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { 2193 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); 2194 return -ENODEV; 2195 } 2196 } else { 2197 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2198 } 2199 2200 /* A sanity check against wild device binding; 2201 * here the range 0x200 is enough for the registers used at probe, 2202 * but it doesn't mean covering all HD-audio registers 2203 */ 2204 if (pci_resource_len(pci, 0) < 0x200) { 2205 dev_err(&pci->dev, "Too small PCI BAR0\n"); 2206 return -EINVAL; 2207 } 2208 2209 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2210 0, &card); 2211 if (err < 0) { 2212 dev_err(&pci->dev, "Error creating card!\n"); 2213 return err; 2214 } 2215 2216 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2217 if (err < 0) 2218 goto out_free; 2219 card->private_data = chip; 2220 hda = container_of(chip, struct hda_intel, chip); 2221 2222 pci_set_drvdata(pci, card); 2223 2224 #ifdef CONFIG_SND_HDA_I915 2225 /* bind with i915 if needed */ 2226 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2227 err = snd_hdac_i915_init(azx_bus(chip)); 2228 if (err < 0) { 2229 if (err == -EPROBE_DEFER) 2230 goto out_free; 2231 2232 /* if the controller is bound only with HDMI/DP 2233 * (for HSW and BDW), we need to abort the probe; 2234 * for other chips, still continue probing as other 2235 * codecs can be on the same link. 2236 */ 2237 if (HDA_CONTROLLER_IN_GPU(pci)) { 2238 dev_err_probe(card->dev, err, 2239 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2240 2241 goto out_free; 2242 } else { 2243 /* don't bother any longer */ 2244 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2245 } 2246 } 2247 2248 /* HSW/BDW controllers need this power */ 2249 if (HDA_CONTROLLER_IN_GPU(pci)) 2250 hda->need_i915_power = true; 2251 } 2252 #else 2253 if (HDA_CONTROLLER_IN_GPU(pci)) 2254 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2255 #endif 2256 2257 err = register_vga_switcheroo(chip); 2258 if (err < 0) { 2259 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2260 goto out_free; 2261 } 2262 2263 if (check_hdmi_disabled(pci)) { 2264 dev_info(card->dev, "VGA controller is disabled\n"); 2265 dev_info(card->dev, "Delaying initialization\n"); 2266 chip->disabled = true; 2267 } 2268 2269 if (!chip->disabled) 2270 schedule_delayed_work(&hda->probe_work, 0); 2271 2272 set_bit(dev, probed_devs); 2273 if (chip->disabled) 2274 complete_all(&hda->probe_wait); 2275 return 0; 2276 2277 out_free: 2278 pci_set_drvdata(pci, NULL); 2279 snd_card_free(card); 2280 return err; 2281 } 2282 2283 /* On some boards setting power_save to a non 0 value leads to clicking / 2284 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2285 * figure out how to avoid these sounds, but that is not always feasible. 2286 * So we keep a list of devices where we disable powersaving as its known 2287 * to causes problems on these devices. 2288 */ 2289 static const struct snd_pci_quirk power_save_denylist[] = { 2290 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2291 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2292 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2293 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2294 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2295 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2296 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2297 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2298 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2299 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2300 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2301 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2302 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2303 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2304 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2305 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2306 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2307 /* https://bugs.launchpad.net/bugs/1821663 */ 2308 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2309 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2310 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2311 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2312 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2313 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0), 2314 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2315 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2316 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2317 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2318 /* https://bugs.launchpad.net/bugs/1821663 */ 2319 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2320 /* KONTRON SinglePC may cause a stall at runtime resume */ 2321 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0), 2322 /* Dell ALC3271 */ 2323 SND_PCI_QUIRK(0x1028, 0x0962, "Dell ALC3271", 0), 2324 /* https://bugzilla.kernel.org/show_bug.cgi?id=220210 */ 2325 SND_PCI_QUIRK(0x17aa, 0x5079, "Lenovo Thinkpad E15", 0), 2326 /* https://bugzilla.kernel.org/show_bug.cgi?id=220694 */ 2327 SND_PCI_QUIRK(0x103c, 0x8a6b, "HP 89E9", 0), 2328 {} 2329 }; 2330 2331 static void set_default_power_save(struct azx *chip) 2332 { 2333 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2334 int val = power_save; 2335 2336 if (pm_blacklist < 0) { 2337 const struct snd_pci_quirk *q; 2338 2339 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); 2340 if (q && val) { 2341 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", 2342 q->subvendor, q->subdevice); 2343 val = 0; 2344 hda->runtime_pm_disabled = 1; 2345 } 2346 } else if (pm_blacklist > 0) { 2347 dev_info(chip->card->dev, "Forcing power_save to 0 via option\n"); 2348 val = 0; 2349 } 2350 snd_hda_set_power_save(&chip->bus, val * 1000); 2351 } 2352 2353 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2354 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2355 [AZX_DRIVER_NVIDIA] = 8, 2356 [AZX_DRIVER_TERA] = 1, 2357 }; 2358 2359 static int azx_probe_continue(struct azx *chip) 2360 { 2361 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2362 struct hdac_bus *bus = azx_bus(chip); 2363 struct pci_dev *pci = chip->pci; 2364 int dev = chip->dev_index; 2365 int err; 2366 2367 if (chip->disabled || hda->init_failed) 2368 return -EIO; 2369 if (hda->probe_retry) 2370 goto probe_retry; 2371 2372 to_hda_bus(bus)->bus_probing = 1; 2373 hda->probe_continued = 1; 2374 2375 /* Request display power well for the HDA controller or codec. For 2376 * Haswell/Broadwell, both the display HDA controller and codec need 2377 * this power. For other platforms, like Baytrail/Braswell, only the 2378 * display codec needs the power and it can be released after probe. 2379 */ 2380 display_power(chip, true); 2381 2382 err = azx_first_init(chip); 2383 if (err < 0) 2384 goto out_free; 2385 2386 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2387 chip->beep_mode = beep_mode[dev]; 2388 #endif 2389 2390 chip->ctl_dev_id = ctl_dev_id; 2391 2392 /* create codec instances */ 2393 if (bus->codec_mask) { 2394 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2395 if (err < 0) 2396 goto out_free; 2397 } 2398 2399 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2400 if (patch[dev] && *patch[dev]) { 2401 const struct firmware *fw __free(firmware) = NULL; 2402 2403 dev_info(&pci->dev, "Applying patch firmware '%s'\n", 2404 patch[dev]); 2405 if (request_firmware(&fw, patch[dev], &pci->dev) < 0) { 2406 dev_err(&pci->dev, 2407 "Cannot load firmware, continue without patching\n"); 2408 } else { 2409 err = snd_hda_load_patch(&chip->bus, fw->size, fw->data); 2410 if (err < 0) 2411 goto out_free; 2412 } 2413 } 2414 #endif 2415 2416 probe_retry: 2417 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2418 err = azx_codec_configure(chip); 2419 if (err) { 2420 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) && 2421 ++hda->probe_retry < 60) { 2422 schedule_delayed_work(&hda->probe_work, 2423 msecs_to_jiffies(1000)); 2424 return 0; /* keep things up */ 2425 } 2426 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n"); 2427 goto out_free; 2428 } 2429 } 2430 2431 err = snd_card_register(chip->card); 2432 if (err < 0) 2433 goto out_free; 2434 2435 setup_vga_switcheroo_runtime_pm(chip); 2436 2437 chip->running = 1; 2438 azx_add_card_list(chip); 2439 2440 set_default_power_save(chip); 2441 2442 if (azx_has_pm_runtime(chip)) { 2443 pm_runtime_use_autosuspend(&pci->dev); 2444 pm_runtime_allow(&pci->dev); 2445 pm_runtime_put_autosuspend(&pci->dev); 2446 } 2447 2448 out_free: 2449 if (err < 0) { 2450 pci_set_drvdata(pci, NULL); 2451 snd_card_free(chip->card); 2452 return err; 2453 } 2454 2455 if (!hda->need_i915_power) 2456 display_power(chip, false); 2457 complete_all(&hda->probe_wait); 2458 to_hda_bus(bus)->bus_probing = 0; 2459 hda->probe_retry = 0; 2460 return 0; 2461 } 2462 2463 static void azx_remove(struct pci_dev *pci) 2464 { 2465 struct snd_card *card = pci_get_drvdata(pci); 2466 struct azx *chip; 2467 struct hda_intel *hda; 2468 2469 if (card) { 2470 /* cancel the pending probing work */ 2471 chip = card->private_data; 2472 hda = container_of(chip, struct hda_intel, chip); 2473 cancel_delayed_work_sync(&hda->probe_work); 2474 2475 clear_bit(chip->dev_index, probed_devs); 2476 pci_set_drvdata(pci, NULL); 2477 snd_card_free(card); 2478 } 2479 } 2480 2481 static void azx_shutdown(struct pci_dev *pci) 2482 { 2483 struct snd_card *card = pci_get_drvdata(pci); 2484 struct azx *chip; 2485 2486 if (!card) 2487 return; 2488 chip = card->private_data; 2489 if (chip && chip->running) 2490 __azx_shutdown_chip(chip, true); 2491 } 2492 2493 /* PCI IDs */ 2494 static const struct pci_device_id azx_ids[] = { 2495 /* CPT */ 2496 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2497 /* PBG */ 2498 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2499 /* Panther Point */ 2500 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2501 /* Lynx Point */ 2502 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2503 /* 9 Series */ 2504 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2505 /* Wellsburg */ 2506 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2507 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2508 /* Lewisburg */ 2509 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, 2510 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, 2511 /* Lynx Point-LP */ 2512 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2513 /* Lynx Point-LP */ 2514 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2515 /* Wildcat Point-LP */ 2516 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2517 /* Skylake (Sunrise Point) */ 2518 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2519 /* Skylake-LP (Sunrise Point-LP) */ 2520 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2521 /* Kabylake */ 2522 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2523 /* Kabylake-LP */ 2524 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2525 /* Kabylake-H */ 2526 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2527 /* Coffelake */ 2528 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2529 /* Cannonlake */ 2530 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2531 /* CometLake-LP */ 2532 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2533 /* CometLake-H */ 2534 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2535 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2536 /* CometLake-S */ 2537 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2538 /* CometLake-R */ 2539 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2540 /* Icelake */ 2541 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2542 /* Icelake-H */ 2543 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2544 /* Jasperlake */ 2545 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2546 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2547 /* Tigerlake */ 2548 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2549 /* Tigerlake-H */ 2550 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2551 /* DG1 */ 2552 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2553 /* DG2 */ 2554 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2555 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2556 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2557 /* Alderlake-S */ 2558 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2559 /* Alderlake-P */ 2560 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2561 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2562 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2563 /* Alderlake-M */ 2564 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2565 /* Alderlake-N */ 2566 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2567 /* Elkhart Lake */ 2568 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2569 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2570 /* Raptor Lake */ 2571 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2572 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2573 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2574 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2575 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2576 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2577 /* Battlemage */ 2578 { PCI_DEVICE_DATA(INTEL, HDA_BMG, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2579 /* Lunarlake-P */ 2580 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2581 /* Arrow Lake-S */ 2582 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2583 /* Arrow Lake */ 2584 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2585 /* Panther Lake */ 2586 { PCI_DEVICE_DATA(INTEL, HDA_PTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2587 /* Panther Lake-H */ 2588 { PCI_DEVICE_DATA(INTEL, HDA_PTL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2589 /* Wildcat Lake */ 2590 { PCI_DEVICE_DATA(INTEL, HDA_WCL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2591 /* Nova Lake */ 2592 { PCI_DEVICE_DATA(INTEL, HDA_NVL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_NVL) }, 2593 { PCI_DEVICE_DATA(INTEL, HDA_NVL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_NVL) }, 2594 /* Apollolake (Broxton-P) */ 2595 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, 2596 /* Gemini-Lake */ 2597 { PCI_DEVICE_DATA(INTEL, HDA_GLK, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, 2598 /* Haswell */ 2599 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2600 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2601 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2602 /* Broadwell */ 2603 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) }, 2604 /* 5 Series/3400 */ 2605 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2606 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2607 /* Poulsbo */ 2608 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE | 2609 AZX_DCAPS_POSFIX_LPIB) }, 2610 /* Oaktrail */ 2611 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) }, 2612 /* BayTrail */ 2613 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) }, 2614 /* Braswell */ 2615 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) }, 2616 /* ICH6 */ 2617 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2618 /* ICH7 */ 2619 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2620 /* ESB2 */ 2621 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2622 /* ICH8 */ 2623 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2624 /* ICH9 */ 2625 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2626 /* ICH9 */ 2627 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2628 /* ICH10 */ 2629 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2630 /* ICH10 */ 2631 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2632 /* Generic Intel */ 2633 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2634 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2635 .class_mask = 0xffffff, 2636 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2637 /* ATI SB 450/600/700/800/900 */ 2638 { PCI_VDEVICE(ATI, 0x437b), 2639 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2640 { PCI_VDEVICE(ATI, 0x4383), 2641 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2642 /* AMD Hudson */ 2643 { PCI_VDEVICE(AMD, 0x780d), 2644 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2645 /* AMD, X370 & co */ 2646 { PCI_VDEVICE(AMD, 0x1457), 2647 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2648 /* AMD, X570 & co */ 2649 { PCI_VDEVICE(AMD, 0x1487), 2650 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2651 /* AMD Stoney */ 2652 { PCI_VDEVICE(AMD, 0x157a), 2653 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2654 AZX_DCAPS_PM_RUNTIME }, 2655 /* AMD Raven */ 2656 { PCI_VDEVICE(AMD, 0x15e3), 2657 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2658 /* ATI HDMI */ 2659 { PCI_VDEVICE(ATI, 0x0002), 2660 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2661 AZX_DCAPS_PM_RUNTIME }, 2662 { PCI_VDEVICE(ATI, 0x1308), 2663 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2664 { PCI_VDEVICE(ATI, 0x157a), 2665 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2666 { PCI_VDEVICE(ATI, 0x15b3), 2667 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2668 { PCI_VDEVICE(ATI, 0x793b), 2669 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2670 { PCI_VDEVICE(ATI, 0x7919), 2671 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2672 { PCI_VDEVICE(ATI, 0x960f), 2673 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2674 { PCI_VDEVICE(ATI, 0x970f), 2675 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2676 { PCI_VDEVICE(ATI, 0x9840), 2677 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2678 { PCI_VDEVICE(ATI, 0xaa00), 2679 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2680 { PCI_VDEVICE(ATI, 0xaa08), 2681 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2682 { PCI_VDEVICE(ATI, 0xaa10), 2683 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2684 { PCI_VDEVICE(ATI, 0xaa18), 2685 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2686 { PCI_VDEVICE(ATI, 0xaa20), 2687 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2688 { PCI_VDEVICE(ATI, 0xaa28), 2689 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2690 { PCI_VDEVICE(ATI, 0xaa30), 2691 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2692 { PCI_VDEVICE(ATI, 0xaa38), 2693 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2694 { PCI_VDEVICE(ATI, 0xaa40), 2695 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2696 { PCI_VDEVICE(ATI, 0xaa48), 2697 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2698 { PCI_VDEVICE(ATI, 0xaa50), 2699 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2700 { PCI_VDEVICE(ATI, 0xaa58), 2701 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2702 { PCI_VDEVICE(ATI, 0xaa60), 2703 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2704 { PCI_VDEVICE(ATI, 0xaa68), 2705 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2706 { PCI_VDEVICE(ATI, 0xaa80), 2707 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2708 { PCI_VDEVICE(ATI, 0xaa88), 2709 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2710 { PCI_VDEVICE(ATI, 0xaa90), 2711 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2712 { PCI_VDEVICE(ATI, 0xaa98), 2713 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2714 { PCI_VDEVICE(ATI, 0x9902), 2715 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2716 { PCI_VDEVICE(ATI, 0xaaa0), 2717 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2718 { PCI_VDEVICE(ATI, 0xaaa8), 2719 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2720 { PCI_VDEVICE(ATI, 0xaab0), 2721 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2722 { PCI_VDEVICE(ATI, 0xaac0), 2723 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2724 AZX_DCAPS_PM_RUNTIME }, 2725 { PCI_VDEVICE(ATI, 0xaac8), 2726 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2727 AZX_DCAPS_PM_RUNTIME }, 2728 { PCI_VDEVICE(ATI, 0xaad8), 2729 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2730 AZX_DCAPS_PM_RUNTIME }, 2731 { PCI_VDEVICE(ATI, 0xaae0), 2732 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2733 AZX_DCAPS_PM_RUNTIME }, 2734 { PCI_VDEVICE(ATI, 0xaae8), 2735 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2736 AZX_DCAPS_PM_RUNTIME }, 2737 { PCI_VDEVICE(ATI, 0xaaf0), 2738 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2739 AZX_DCAPS_PM_RUNTIME }, 2740 { PCI_VDEVICE(ATI, 0xaaf8), 2741 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2742 AZX_DCAPS_PM_RUNTIME }, 2743 { PCI_VDEVICE(ATI, 0xab00), 2744 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2745 AZX_DCAPS_PM_RUNTIME }, 2746 { PCI_VDEVICE(ATI, 0xab08), 2747 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2748 AZX_DCAPS_PM_RUNTIME }, 2749 { PCI_VDEVICE(ATI, 0xab10), 2750 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2751 AZX_DCAPS_PM_RUNTIME }, 2752 { PCI_VDEVICE(ATI, 0xab18), 2753 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2754 AZX_DCAPS_PM_RUNTIME }, 2755 { PCI_VDEVICE(ATI, 0xab20), 2756 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2757 AZX_DCAPS_PM_RUNTIME }, 2758 { PCI_VDEVICE(ATI, 0xab28), 2759 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2760 AZX_DCAPS_PM_RUNTIME }, 2761 { PCI_VDEVICE(ATI, 0xab30), 2762 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2763 AZX_DCAPS_PM_RUNTIME }, 2764 { PCI_VDEVICE(ATI, 0xab38), 2765 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2766 AZX_DCAPS_PM_RUNTIME }, 2767 { PCI_VDEVICE(ATI, 0xab40), 2768 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2769 AZX_DCAPS_PM_RUNTIME }, 2770 /* GLENFLY */ 2771 { PCI_DEVICE(PCI_VENDOR_ID_GLENFLY, PCI_ANY_ID), 2772 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2773 .class_mask = 0xffffff, 2774 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB | 2775 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2776 /* VIA VT8251/VT8237A */ 2777 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2778 /* VIA GFX VT7122/VX900 */ 2779 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2780 /* VIA GFX VT6122/VX11 */ 2781 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2782 /* SIS966 */ 2783 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2784 /* ULI M5461 */ 2785 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2786 /* NVIDIA MCP */ 2787 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2788 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2789 .class_mask = 0xffffff, 2790 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2791 /* Teradici */ 2792 { PCI_DEVICE(0x6549, 0x1200), 2793 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2794 { PCI_DEVICE(0x6549, 0x2200), 2795 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2796 /* Creative X-Fi (CA0110-IBG) */ 2797 /* CTHDA chips */ 2798 { PCI_VDEVICE(CREATIVE, 0x0010), 2799 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2800 { PCI_VDEVICE(CREATIVE, 0x0012), 2801 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2802 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2803 /* the following entry conflicts with snd-ctxfi driver, 2804 * as ctxfi driver mutates from HD-audio to native mode with 2805 * a special command sequence. 2806 */ 2807 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2808 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2809 .class_mask = 0xffffff, 2810 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2811 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2812 #else 2813 /* this entry seems still valid -- i.e. without emu20kx chip */ 2814 { PCI_VDEVICE(CREATIVE, 0x0009), 2815 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2816 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2817 #endif 2818 /* CM8888 */ 2819 { PCI_VDEVICE(CMEDIA, 0x5011), 2820 .driver_data = AZX_DRIVER_CMEDIA | 2821 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2822 /* Vortex86MX */ 2823 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2824 /* VMware HDAudio */ 2825 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2826 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2827 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2828 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2829 .class_mask = 0xffffff, 2830 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2831 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2832 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2833 .class_mask = 0xffffff, 2834 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2835 /* Zhaoxin */ 2836 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2837 { PCI_VDEVICE(ZHAOXIN, 0x9141), 2838 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB | 2839 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2840 { PCI_VDEVICE(ZHAOXIN, 0x9142), 2841 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB | 2842 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2843 { PCI_VDEVICE(ZHAOXIN, 0x9144), 2844 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB | 2845 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2846 { PCI_VDEVICE(ZHAOXIN, 0x9145), 2847 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB | 2848 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2849 { PCI_VDEVICE(ZHAOXIN, 0x9146), 2850 .driver_data = AZX_DRIVER_ZHAOXINHDMI | AZX_DCAPS_POSFIX_LPIB | 2851 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2852 /* Loongson HDAudio*/ 2853 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA), 2854 .driver_data = AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL }, 2855 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI), 2856 .driver_data = AZX_DRIVER_LOONGSON | AZX_DCAPS_NO_TCSEL }, 2857 /* Hygon HDAudio */ 2858 { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_HYGON_18H_M05H_HDA), 2859 .driver_data = AZX_DRIVER_HYGON | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_NO_MSI }, 2860 /* Lisuan HD-audio */ 2861 { PCI_DEVICE(0x4c54, 0x5010), .driver_data = AZX_DRIVER_GENERIC }, 2862 { 0, } 2863 }; 2864 MODULE_DEVICE_TABLE(pci, azx_ids); 2865 2866 /* pci_driver definition */ 2867 static struct pci_driver azx_driver = { 2868 .name = KBUILD_MODNAME, 2869 .id_table = azx_ids, 2870 .probe = azx_probe, 2871 .remove = azx_remove, 2872 .shutdown = azx_shutdown, 2873 .driver = { 2874 .pm = pm_ptr(&azx_pm), 2875 }, 2876 }; 2877 2878 module_pci_driver(azx_driver); 2879