1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HD audio codec driver for Creative CA0132 chip 4 * 5 * Copyright (c) 2011, Creative Technology Ltd. 6 * 7 * Based on ca0110.c 8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/mutex.h> 15 #include <linux/module.h> 16 #include <linux/firmware.h> 17 #include <linux/kernel.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <asm/io.h> 22 #include <sound/core.h> 23 #include <sound/hda_codec.h> 24 #include "hda_local.h" 25 #include "hda_auto_parser.h" 26 #include "hda_jack.h" 27 28 #include "ca0132_regs.h" 29 30 /* Enable this to see controls for tuning purpose. */ 31 #define ENABLE_TUNING_CONTROLS 32 33 #ifdef ENABLE_TUNING_CONTROLS 34 #include <sound/tlv.h> 35 #endif 36 37 #define FLOAT_ZERO 0x00000000 38 #define FLOAT_ONE 0x3f800000 39 #define FLOAT_TWO 0x40000000 40 #define FLOAT_THREE 0x40400000 41 #define FLOAT_FIVE 0x40a00000 42 #define FLOAT_SIX 0x40c00000 43 #define FLOAT_EIGHT 0x41000000 44 #define FLOAT_MINUS_5 0xc0a00000 45 46 #define UNSOL_TAG_DSP 0x16 47 48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 50 51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 54 55 #define MASTERCONTROL 0x80 56 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 58 59 #define WIDGET_CHIP_CTRL 0x15 60 #define WIDGET_DSP_CTRL 0x16 61 62 #define MEM_CONNID_MICIN1 3 63 #define MEM_CONNID_MICIN2 5 64 #define MEM_CONNID_MICOUT1 12 65 #define MEM_CONNID_MICOUT2 14 66 #define MEM_CONNID_WUH 10 67 #define MEM_CONNID_DSP 16 68 #define MEM_CONNID_DMIC 100 69 70 #define SCP_SET 0 71 #define SCP_GET 1 72 73 #define EFX_FILE "ctefx.bin" 74 #define DESKTOP_EFX_FILE "ctefx-desktop.bin" 75 #define R3DI_EFX_FILE "ctefx-r3di.bin" 76 77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 78 MODULE_FIRMWARE(EFX_FILE); 79 MODULE_FIRMWARE(DESKTOP_EFX_FILE); 80 MODULE_FIRMWARE(R3DI_EFX_FILE); 81 #endif 82 83 static const char *const dirstr[2] = { "Playback", "Capture" }; 84 85 #define NUM_OF_OUTPUTS 2 86 static const char *const out_type_str[2] = { "Speakers", "Headphone" }; 87 enum { 88 SPEAKER_OUT, 89 HEADPHONE_OUT, 90 }; 91 92 enum { 93 DIGITAL_MIC, 94 LINE_MIC_IN 95 }; 96 97 /* Strings for Input Source Enum Control */ 98 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" }; 99 #define IN_SRC_NUM_OF_INPUTS 3 100 enum { 101 REAR_MIC, 102 REAR_LINE_IN, 103 FRONT_MIC, 104 }; 105 106 enum { 107 #define VNODE_START_NID 0x80 108 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 109 VNID_MIC, 110 VNID_HP_SEL, 111 VNID_AMIC1_SEL, 112 VNID_HP_ASEL, 113 VNID_AMIC1_ASEL, 114 VNODE_END_NID, 115 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 116 117 #define EFFECT_START_NID 0x90 118 #define OUT_EFFECT_START_NID EFFECT_START_NID 119 SURROUND = OUT_EFFECT_START_NID, 120 CRYSTALIZER, 121 DIALOG_PLUS, 122 SMART_VOLUME, 123 X_BASS, 124 EQUALIZER, 125 OUT_EFFECT_END_NID, 126 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 127 128 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 129 ECHO_CANCELLATION = IN_EFFECT_START_NID, 130 VOICE_FOCUS, 131 MIC_SVM, 132 NOISE_REDUCTION, 133 IN_EFFECT_END_NID, 134 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 135 136 VOICEFX = IN_EFFECT_END_NID, 137 PLAY_ENHANCEMENT, 138 CRYSTAL_VOICE, 139 EFFECT_END_NID, 140 OUTPUT_SOURCE_ENUM, 141 INPUT_SOURCE_ENUM, 142 XBASS_XOVER, 143 EQ_PRESET_ENUM, 144 SMART_VOLUME_ENUM, 145 MIC_BOOST_ENUM, 146 AE5_HEADPHONE_GAIN_ENUM, 147 AE5_SOUND_FILTER_ENUM, 148 ZXR_HEADPHONE_GAIN, 149 SPEAKER_CHANNEL_CFG_ENUM, 150 SPEAKER_FULL_RANGE_FRONT, 151 SPEAKER_FULL_RANGE_REAR, 152 BASS_REDIRECTION, 153 BASS_REDIRECTION_XOVER, 154 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 155 }; 156 157 /* Effects values size*/ 158 #define EFFECT_VALS_MAX_COUNT 12 159 160 /* 161 * Default values for the effect slider controls, they are in order of their 162 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 163 * X-bass. 164 */ 165 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 166 /* Amount of effect level sliders for ca0132_alt controls. */ 167 #define EFFECT_LEVEL_SLIDERS 5 168 169 /* Latency introduced by DSP blocks in milliseconds. */ 170 #define DSP_CAPTURE_INIT_LATENCY 0 171 #define DSP_CRYSTAL_VOICE_LATENCY 124 172 #define DSP_PLAYBACK_INIT_LATENCY 13 173 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 174 #define DSP_SPEAKER_OUT_LATENCY 7 175 176 struct ct_effect { 177 const char *name; 178 hda_nid_t nid; 179 int mid; /*effect module ID*/ 180 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 181 int direct; /* 0:output; 1:input*/ 182 int params; /* number of default non-on/off params */ 183 /*effect default values, 1st is on/off. */ 184 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 185 }; 186 187 #define EFX_DIR_OUT 0 188 #define EFX_DIR_IN 1 189 190 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 191 { .name = "Surround", 192 .nid = SURROUND, 193 .mid = 0x96, 194 .reqs = {0, 1}, 195 .direct = EFX_DIR_OUT, 196 .params = 1, 197 .def_vals = {0x3F800000, 0x3F2B851F} 198 }, 199 { .name = "Crystalizer", 200 .nid = CRYSTALIZER, 201 .mid = 0x96, 202 .reqs = {7, 8}, 203 .direct = EFX_DIR_OUT, 204 .params = 1, 205 .def_vals = {0x3F800000, 0x3F266666} 206 }, 207 { .name = "Dialog Plus", 208 .nid = DIALOG_PLUS, 209 .mid = 0x96, 210 .reqs = {2, 3}, 211 .direct = EFX_DIR_OUT, 212 .params = 1, 213 .def_vals = {0x00000000, 0x3F000000} 214 }, 215 { .name = "Smart Volume", 216 .nid = SMART_VOLUME, 217 .mid = 0x96, 218 .reqs = {4, 5, 6}, 219 .direct = EFX_DIR_OUT, 220 .params = 2, 221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 222 }, 223 { .name = "X-Bass", 224 .nid = X_BASS, 225 .mid = 0x96, 226 .reqs = {24, 23, 25}, 227 .direct = EFX_DIR_OUT, 228 .params = 2, 229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 230 }, 231 { .name = "Equalizer", 232 .nid = EQUALIZER, 233 .mid = 0x96, 234 .reqs = {9, 10, 11, 12, 13, 14, 235 15, 16, 17, 18, 19, 20}, 236 .direct = EFX_DIR_OUT, 237 .params = 11, 238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 239 0x00000000, 0x00000000, 0x00000000, 0x00000000, 240 0x00000000, 0x00000000, 0x00000000, 0x00000000} 241 }, 242 { .name = "Echo Cancellation", 243 .nid = ECHO_CANCELLATION, 244 .mid = 0x95, 245 .reqs = {0, 1, 2, 3}, 246 .direct = EFX_DIR_IN, 247 .params = 3, 248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 249 }, 250 { .name = "Voice Focus", 251 .nid = VOICE_FOCUS, 252 .mid = 0x95, 253 .reqs = {6, 7, 8, 9}, 254 .direct = EFX_DIR_IN, 255 .params = 3, 256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 257 }, 258 { .name = "Mic SVM", 259 .nid = MIC_SVM, 260 .mid = 0x95, 261 .reqs = {44, 45}, 262 .direct = EFX_DIR_IN, 263 .params = 1, 264 .def_vals = {0x00000000, 0x3F3D70A4} 265 }, 266 { .name = "Noise Reduction", 267 .nid = NOISE_REDUCTION, 268 .mid = 0x95, 269 .reqs = {4, 5}, 270 .direct = EFX_DIR_IN, 271 .params = 1, 272 .def_vals = {0x3F800000, 0x3F000000} 273 }, 274 { .name = "VoiceFX", 275 .nid = VOICEFX, 276 .mid = 0x95, 277 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 278 .direct = EFX_DIR_IN, 279 .params = 8, 280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 282 0x00000000} 283 } 284 }; 285 286 /* Tuning controls */ 287 #ifdef ENABLE_TUNING_CONTROLS 288 289 enum { 290 #define TUNING_CTL_START_NID 0xC0 291 WEDGE_ANGLE = TUNING_CTL_START_NID, 292 SVM_LEVEL, 293 EQUALIZER_BAND_0, 294 EQUALIZER_BAND_1, 295 EQUALIZER_BAND_2, 296 EQUALIZER_BAND_3, 297 EQUALIZER_BAND_4, 298 EQUALIZER_BAND_5, 299 EQUALIZER_BAND_6, 300 EQUALIZER_BAND_7, 301 EQUALIZER_BAND_8, 302 EQUALIZER_BAND_9, 303 TUNING_CTL_END_NID 304 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 305 }; 306 307 struct ct_tuning_ctl { 308 const char *name; 309 hda_nid_t parent_nid; 310 hda_nid_t nid; 311 int mid; /*effect module ID*/ 312 int req; /*effect module request*/ 313 int direct; /* 0:output; 1:input*/ 314 unsigned int def_val;/*effect default values*/ 315 }; 316 317 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 318 { .name = "Wedge Angle", 319 .parent_nid = VOICE_FOCUS, 320 .nid = WEDGE_ANGLE, 321 .mid = 0x95, 322 .req = 8, 323 .direct = EFX_DIR_IN, 324 .def_val = 0x41F00000 325 }, 326 { .name = "SVM Level", 327 .parent_nid = MIC_SVM, 328 .nid = SVM_LEVEL, 329 .mid = 0x95, 330 .req = 45, 331 .direct = EFX_DIR_IN, 332 .def_val = 0x3F3D70A4 333 }, 334 { .name = "EQ Band0", 335 .parent_nid = EQUALIZER, 336 .nid = EQUALIZER_BAND_0, 337 .mid = 0x96, 338 .req = 11, 339 .direct = EFX_DIR_OUT, 340 .def_val = 0x00000000 341 }, 342 { .name = "EQ Band1", 343 .parent_nid = EQUALIZER, 344 .nid = EQUALIZER_BAND_1, 345 .mid = 0x96, 346 .req = 12, 347 .direct = EFX_DIR_OUT, 348 .def_val = 0x00000000 349 }, 350 { .name = "EQ Band2", 351 .parent_nid = EQUALIZER, 352 .nid = EQUALIZER_BAND_2, 353 .mid = 0x96, 354 .req = 13, 355 .direct = EFX_DIR_OUT, 356 .def_val = 0x00000000 357 }, 358 { .name = "EQ Band3", 359 .parent_nid = EQUALIZER, 360 .nid = EQUALIZER_BAND_3, 361 .mid = 0x96, 362 .req = 14, 363 .direct = EFX_DIR_OUT, 364 .def_val = 0x00000000 365 }, 366 { .name = "EQ Band4", 367 .parent_nid = EQUALIZER, 368 .nid = EQUALIZER_BAND_4, 369 .mid = 0x96, 370 .req = 15, 371 .direct = EFX_DIR_OUT, 372 .def_val = 0x00000000 373 }, 374 { .name = "EQ Band5", 375 .parent_nid = EQUALIZER, 376 .nid = EQUALIZER_BAND_5, 377 .mid = 0x96, 378 .req = 16, 379 .direct = EFX_DIR_OUT, 380 .def_val = 0x00000000 381 }, 382 { .name = "EQ Band6", 383 .parent_nid = EQUALIZER, 384 .nid = EQUALIZER_BAND_6, 385 .mid = 0x96, 386 .req = 17, 387 .direct = EFX_DIR_OUT, 388 .def_val = 0x00000000 389 }, 390 { .name = "EQ Band7", 391 .parent_nid = EQUALIZER, 392 .nid = EQUALIZER_BAND_7, 393 .mid = 0x96, 394 .req = 18, 395 .direct = EFX_DIR_OUT, 396 .def_val = 0x00000000 397 }, 398 { .name = "EQ Band8", 399 .parent_nid = EQUALIZER, 400 .nid = EQUALIZER_BAND_8, 401 .mid = 0x96, 402 .req = 19, 403 .direct = EFX_DIR_OUT, 404 .def_val = 0x00000000 405 }, 406 { .name = "EQ Band9", 407 .parent_nid = EQUALIZER, 408 .nid = EQUALIZER_BAND_9, 409 .mid = 0x96, 410 .req = 20, 411 .direct = EFX_DIR_OUT, 412 .def_val = 0x00000000 413 } 414 }; 415 #endif 416 417 /* Voice FX Presets */ 418 #define VOICEFX_MAX_PARAM_COUNT 9 419 420 struct ct_voicefx { 421 const char *name; 422 hda_nid_t nid; 423 int mid; 424 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 425 }; 426 427 struct ct_voicefx_preset { 428 const char *name; /*preset name*/ 429 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 430 }; 431 432 static const struct ct_voicefx ca0132_voicefx = { 433 .name = "VoiceFX Capture Switch", 434 .nid = VOICEFX, 435 .mid = 0x95, 436 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 437 }; 438 439 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 440 { .name = "Neutral", 441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 442 0x44FA0000, 0x3F800000, 0x3F800000, 443 0x3F800000, 0x00000000, 0x00000000 } 444 }, 445 { .name = "Female2Male", 446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 447 0x44FA0000, 0x3F19999A, 0x3F866666, 448 0x3F800000, 0x00000000, 0x00000000 } 449 }, 450 { .name = "Male2Female", 451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 452 0x450AC000, 0x4017AE14, 0x3F6B851F, 453 0x3F800000, 0x00000000, 0x00000000 } 454 }, 455 { .name = "ScrappyKid", 456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 457 0x44FA0000, 0x40400000, 0x3F28F5C3, 458 0x3F800000, 0x00000000, 0x00000000 } 459 }, 460 { .name = "Elderly", 461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 462 0x44E10000, 0x3FB33333, 0x3FB9999A, 463 0x3F800000, 0x3E3A2E43, 0x00000000 } 464 }, 465 { .name = "Orc", 466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 467 0x45098000, 0x3F266666, 0x3FC00000, 468 0x3F800000, 0x00000000, 0x00000000 } 469 }, 470 { .name = "Elf", 471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 472 0x45193000, 0x3F8E147B, 0x3F75C28F, 473 0x3F800000, 0x00000000, 0x00000000 } 474 }, 475 { .name = "Dwarf", 476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 477 0x45007000, 0x3F451EB8, 0x3F7851EC, 478 0x3F800000, 0x00000000, 0x00000000 } 479 }, 480 { .name = "AlienBrute", 481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 482 0x451F6000, 0x3F266666, 0x3FA7D945, 483 0x3F800000, 0x3CF5C28F, 0x00000000 } 484 }, 485 { .name = "Robot", 486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 487 0x44FA0000, 0x3FB2718B, 0x3F800000, 488 0xBC07010E, 0x00000000, 0x00000000 } 489 }, 490 { .name = "Marine", 491 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 493 0x3F0A3D71, 0x00000000, 0x00000000 } 494 }, 495 { .name = "Emo", 496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 497 0x44FA0000, 0x3F800000, 0x3F800000, 498 0x3E4CCCCD, 0x00000000, 0x00000000 } 499 }, 500 { .name = "DeepVoice", 501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 503 0x3F800000, 0x00000000, 0x00000000 } 504 }, 505 { .name = "Munchkin", 506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 507 0x44FA0000, 0x3F800000, 0x3F1A043C, 508 0x3F800000, 0x00000000, 0x00000000 } 509 } 510 }; 511 512 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 513 514 #define EQ_PRESET_MAX_PARAM_COUNT 11 515 516 struct ct_eq { 517 const char *name; 518 hda_nid_t nid; 519 int mid; 520 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 521 }; 522 523 struct ct_eq_preset { 524 const char *name; /*preset name*/ 525 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 526 }; 527 528 static const struct ct_eq ca0132_alt_eq_enum = { 529 .name = "FX: Equalizer Preset Switch", 530 .nid = EQ_PRESET_ENUM, 531 .mid = 0x96, 532 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 533 }; 534 535 536 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 537 { .name = "Flat", 538 .vals = { 0x00000000, 0x00000000, 0x00000000, 539 0x00000000, 0x00000000, 0x00000000, 540 0x00000000, 0x00000000, 0x00000000, 541 0x00000000, 0x00000000 } 542 }, 543 { .name = "Acoustic", 544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 545 0x40000000, 0x00000000, 0x00000000, 546 0x00000000, 0x00000000, 0x40000000, 547 0x40000000, 0x40000000 } 548 }, 549 { .name = "Classical", 550 .vals = { 0x00000000, 0x00000000, 0x40C00000, 551 0x40C00000, 0x40466666, 0x00000000, 552 0x00000000, 0x00000000, 0x00000000, 553 0x40466666, 0x40466666 } 554 }, 555 { .name = "Country", 556 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 558 0x00000000, 0x00000000, 0x40000000, 559 0x40466666, 0x40800000 } 560 }, 561 { .name = "Dance", 562 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 563 0x40466666, 0x40866666, 0xBF99999A, 564 0xBF99999A, 0x00000000, 0x00000000, 565 0x40800000, 0x40800000 } 566 }, 567 { .name = "Jazz", 568 .vals = { 0x00000000, 0x00000000, 0x00000000, 569 0x3F8CCCCD, 0x40800000, 0x40800000, 570 0x40800000, 0x00000000, 0x3F8CCCCD, 571 0x40466666, 0x40466666 } 572 }, 573 { .name = "New Age", 574 .vals = { 0x00000000, 0x00000000, 0x40000000, 575 0x40000000, 0x00000000, 0x00000000, 576 0x00000000, 0x3F8CCCCD, 0x40000000, 577 0x40000000, 0x40000000 } 578 }, 579 { .name = "Pop", 580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 581 0x40000000, 0x40000000, 0x00000000, 582 0xBF99999A, 0xBF99999A, 0x00000000, 583 0x40466666, 0x40C00000 } 584 }, 585 { .name = "Rock", 586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 587 0x3F8CCCCD, 0x40000000, 0xBF99999A, 588 0xBF99999A, 0x00000000, 0x00000000, 589 0x40800000, 0x40800000 } 590 }, 591 { .name = "Vocal", 592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 593 0xBF99999A, 0x00000000, 0x40466666, 594 0x40800000, 0x40466666, 0x00000000, 595 0x00000000, 0x3F8CCCCD } 596 } 597 }; 598 599 /* 600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is 601 * set as not being full range, and bass redirection is enabled, all 602 * frequencies below the crossover frequency are redirected to the LFE 603 * channel. If the surround configuration has no LFE channel, this can't be 604 * enabled. X-Bass must be disabled when using these. 605 */ 606 enum speaker_range_reqs { 607 SPEAKER_BASS_REDIRECT = 0x15, 608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16, 609 /* Between 0x16-0x1a are the X-Bass reqs. */ 610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a, 611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b, 612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c, 613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d, 614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e, 615 }; 616 617 /* 618 * Definitions for the DSP req's to handle speaker tuning. These all belong to 619 * module ID 0x96, the output effects module. 620 */ 621 enum speaker_tuning_reqs { 622 /* 623 * Currently, this value is always set to 0.0f. However, on Windows, 624 * when selecting certain headphone profiles on the new Sound Blaster 625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is 626 * sent. This gets the speaker EQ address area, which is then used to 627 * send over (presumably) an equalizer profile for the specific 628 * headphone setup. It is sent using the same method the DSP 629 * firmware is uploaded with, which I believe is why the 'ctspeq.bin' 630 * file exists in linux firmware tree but goes unused. It would also 631 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused. 632 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is 633 * set to 1.0f. 634 */ 635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f, 636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20, 637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21, 638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22, 639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23, 640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24, 641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25, 642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26, 643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27, 644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28, 645 /* 646 * Inversion is used when setting headphone virtualization to line 647 * out. Not sure why this is, but it's the only place it's ever used. 648 */ 649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29, 650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a, 651 SPEAKER_TUNING_CENTER_INVERT = 0x2b, 652 SPEAKER_TUNING_LFE_INVERT = 0x2c, 653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d, 654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e, 655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f, 656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30, 657 /* Delay is used when setting surround speaker distance in Windows. */ 658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31, 659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32, 660 SPEAKER_TUNING_CENTER_DELAY = 0x33, 661 SPEAKER_TUNING_LFE_DELAY = 0x34, 662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35, 663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36, 664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37, 665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38, 666 /* Of these two, only mute seems to ever be used. */ 667 SPEAKER_TUNING_MAIN_VOLUME = 0x39, 668 SPEAKER_TUNING_MUTE = 0x3a, 669 }; 670 671 /* Surround output channel count configuration structures. */ 672 #define SPEAKER_CHANNEL_CFG_COUNT 5 673 enum { 674 SPEAKER_CHANNELS_2_0, 675 SPEAKER_CHANNELS_2_1, 676 SPEAKER_CHANNELS_4_0, 677 SPEAKER_CHANNELS_4_1, 678 SPEAKER_CHANNELS_5_1, 679 }; 680 681 struct ca0132_alt_speaker_channel_cfg { 682 const char *name; 683 unsigned int val; 684 }; 685 686 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = { 687 { .name = "2.0", 688 .val = FLOAT_ONE 689 }, 690 { .name = "2.1", 691 .val = FLOAT_TWO 692 }, 693 { .name = "4.0", 694 .val = FLOAT_FIVE 695 }, 696 { .name = "4.1", 697 .val = FLOAT_SIX 698 }, 699 { .name = "5.1", 700 .val = FLOAT_EIGHT 701 } 702 }; 703 704 /* 705 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 706 * and I don't know what the third req is, but it's always zero. I assume it's 707 * some sort of update or set command to tell the DSP there's new volume info. 708 */ 709 #define DSP_VOL_OUT 0 710 #define DSP_VOL_IN 1 711 712 struct ct_dsp_volume_ctl { 713 hda_nid_t vnid; 714 int mid; /* module ID*/ 715 unsigned int reqs[3]; /* scp req ID */ 716 }; 717 718 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 719 { .vnid = VNID_SPK, 720 .mid = 0x32, 721 .reqs = {3, 4, 2} 722 }, 723 { .vnid = VNID_MIC, 724 .mid = 0x37, 725 .reqs = {2, 3, 1} 726 } 727 }; 728 729 /* Values for ca0113_mmio_command_set for selecting output. */ 730 #define AE_CA0113_OUT_SET_COMMANDS 6 731 struct ae_ca0113_output_set { 732 unsigned int group[AE_CA0113_OUT_SET_COMMANDS]; 733 unsigned int target[AE_CA0113_OUT_SET_COMMANDS]; 734 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS]; 735 }; 736 737 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = { 738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 740 /* Speakers. */ 741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 742 /* Headphones. */ 743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } }, 744 }; 745 746 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = { 747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 749 /* Speakers. */ 750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f }, 751 /* Headphones. */ 752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } }, 753 }; 754 755 /* ae5 ca0113 command sequences to set headphone gain levels. */ 756 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 757 struct ae5_headphone_gain_set { 758 const char *name; 759 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 760 }; 761 762 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 763 { .name = "Low (16-31", 764 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 765 }, 766 { .name = "Medium (32-149", 767 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 768 }, 769 { .name = "High (150-600", 770 .vals = { 0xff, 0xff, 0xff, 0x7f } 771 } 772 }; 773 774 struct ae5_filter_set { 775 const char *name; 776 unsigned int val; 777 }; 778 779 static const struct ae5_filter_set ae5_filter_presets[] = { 780 { .name = "Slow Roll Off", 781 .val = 0xa0 782 }, 783 { .name = "Minimum Phase", 784 .val = 0xc0 785 }, 786 { .name = "Fast Roll Off", 787 .val = 0x80 788 } 789 }; 790 791 /* 792 * Data structures for storing audio router remapping data. These are used to 793 * remap a currently active streams ports. 794 */ 795 struct chipio_stream_remap_data { 796 unsigned int stream_id; 797 unsigned int count; 798 799 unsigned int offset[16]; 800 unsigned int value[16]; 801 }; 802 803 static const struct chipio_stream_remap_data stream_remap_data[] = { 804 { .stream_id = 0x14, 805 .count = 0x04, 806 .offset = { 0x00, 0x04, 0x08, 0x0c }, 807 .value = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 }, 808 }, 809 { .stream_id = 0x0c, 810 .count = 0x0c, 811 .offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 812 0x20, 0x24, 0x28, 0x2c }, 813 .value = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 814 0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7, 815 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb }, 816 }, 817 { .stream_id = 0x0c, 818 .count = 0x08, 819 .offset = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c }, 820 .value = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5, 821 0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb }, 822 } 823 }; 824 825 enum hda_cmd_vendor_io { 826 /* for DspIO node */ 827 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 828 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 829 830 VENDOR_DSPIO_STATUS = 0xF01, 831 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 832 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 833 VENDOR_DSPIO_DSP_INIT = 0x703, 834 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 835 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 836 837 /* for ChipIO node */ 838 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 839 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 840 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 841 VENDOR_CHIPIO_DATA_LOW = 0x300, 842 VENDOR_CHIPIO_DATA_HIGH = 0x400, 843 844 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 845 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 846 847 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 848 VENDOR_CHIPIO_STATUS = 0xF01, 849 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 850 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 851 852 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 853 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 854 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 855 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 856 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 857 858 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 859 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 860 861 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 862 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 863 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 864 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 865 VENDOR_CHIPIO_FLAG_SET = 0x70F, 866 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 867 VENDOR_CHIPIO_PARAM_SET = 0x710, 868 VENDOR_CHIPIO_PARAM_GET = 0xF10, 869 870 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 871 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 872 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 873 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 874 875 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 876 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 877 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 878 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 879 880 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 881 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 882 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 883 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 884 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 885 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 886 887 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 888 }; 889 890 /* 891 * Control flag IDs 892 */ 893 enum control_flag_id { 894 /* Connection manager stream setup is bypassed/enabled */ 895 CONTROL_FLAG_C_MGR = 0, 896 /* DSP DMA is bypassed/enabled */ 897 CONTROL_FLAG_DMA = 1, 898 /* 8051 'idle' mode is disabled/enabled */ 899 CONTROL_FLAG_IDLE_ENABLE = 2, 900 /* Tracker for the SPDIF-in path is bypassed/enabled */ 901 CONTROL_FLAG_TRACKER = 3, 902 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 903 CONTROL_FLAG_SPDIF2OUT = 4, 904 /* Digital Microphone is disabled/enabled */ 905 CONTROL_FLAG_DMIC = 5, 906 /* ADC_B rate is 48 kHz/96 kHz */ 907 CONTROL_FLAG_ADC_B_96KHZ = 6, 908 /* ADC_C rate is 48 kHz/96 kHz */ 909 CONTROL_FLAG_ADC_C_96KHZ = 7, 910 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 911 CONTROL_FLAG_DAC_96KHZ = 8, 912 /* DSP rate is 48 kHz/96 kHz */ 913 CONTROL_FLAG_DSP_96KHZ = 9, 914 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 915 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 916 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 917 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 918 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 919 CONTROL_FLAG_DECODE_LOOP = 12, 920 /* De-emphasis filter on DAC-1 disabled/enabled */ 921 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 922 /* De-emphasis filter on DAC-2 disabled/enabled */ 923 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 924 /* De-emphasis filter on DAC-3 disabled/enabled */ 925 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 926 /* High-pass filter on ADC_B disabled/enabled */ 927 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 928 /* High-pass filter on ADC_C disabled/enabled */ 929 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 930 /* Common mode on Port_A disabled/enabled */ 931 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 932 /* Common mode on Port_D disabled/enabled */ 933 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 934 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 935 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 936 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 937 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 938 /* ASI rate is 48kHz/96kHz */ 939 CONTROL_FLAG_ASI_96KHZ = 22, 940 /* DAC power settings able to control attached ports no/yes */ 941 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 942 /* Clock Stop OK reporting is disabled/enabled */ 943 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 944 /* Number of control flags */ 945 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 946 }; 947 948 /* 949 * Control parameter IDs 950 */ 951 enum control_param_id { 952 /* 0: None, 1: Mic1In*/ 953 CONTROL_PARAM_VIP_SOURCE = 1, 954 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 955 CONTROL_PARAM_SPDIF1_SOURCE = 2, 956 /* Port A output stage gain setting to use when 16 Ohm output 957 * impedance is selected*/ 958 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 959 /* Port D output stage gain setting to use when 16 Ohm output 960 * impedance is selected*/ 961 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 962 963 /* 964 * This control param name was found in the 8051 memory, and makes 965 * sense given the fact the AE-5 uses it and has the ASI flag set. 966 */ 967 CONTROL_PARAM_ASI = 23, 968 969 /* Stream Control */ 970 971 /* Select stream with the given ID */ 972 CONTROL_PARAM_STREAM_ID = 24, 973 /* Source connection point for the selected stream */ 974 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 975 /* Destination connection point for the selected stream */ 976 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 977 /* Number of audio channels in the selected stream */ 978 CONTROL_PARAM_STREAMS_CHANNELS = 27, 979 /*Enable control for the selected stream */ 980 CONTROL_PARAM_STREAM_CONTROL = 28, 981 982 /* Connection Point Control */ 983 984 /* Select connection point with the given ID */ 985 CONTROL_PARAM_CONN_POINT_ID = 29, 986 /* Connection point sample rate */ 987 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 988 989 /* Node Control */ 990 991 /* Select HDA node with the given ID */ 992 CONTROL_PARAM_NODE_ID = 31 993 }; 994 995 /* 996 * Dsp Io Status codes 997 */ 998 enum hda_vendor_status_dspio { 999 /* Success */ 1000 VENDOR_STATUS_DSPIO_OK = 0x00, 1001 /* Busy, unable to accept new command, the host must retry */ 1002 VENDOR_STATUS_DSPIO_BUSY = 0x01, 1003 /* SCP command queue is full */ 1004 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 1005 /* SCP response queue is empty */ 1006 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 1007 }; 1008 1009 /* 1010 * Chip Io Status codes 1011 */ 1012 enum hda_vendor_status_chipio { 1013 /* Success */ 1014 VENDOR_STATUS_CHIPIO_OK = 0x00, 1015 /* Busy, unable to accept new command, the host must retry */ 1016 VENDOR_STATUS_CHIPIO_BUSY = 0x01 1017 }; 1018 1019 /* 1020 * CA0132 sample rate 1021 */ 1022 enum ca0132_sample_rate { 1023 SR_6_000 = 0x00, 1024 SR_8_000 = 0x01, 1025 SR_9_600 = 0x02, 1026 SR_11_025 = 0x03, 1027 SR_16_000 = 0x04, 1028 SR_22_050 = 0x05, 1029 SR_24_000 = 0x06, 1030 SR_32_000 = 0x07, 1031 SR_44_100 = 0x08, 1032 SR_48_000 = 0x09, 1033 SR_88_200 = 0x0A, 1034 SR_96_000 = 0x0B, 1035 SR_144_000 = 0x0C, 1036 SR_176_400 = 0x0D, 1037 SR_192_000 = 0x0E, 1038 SR_384_000 = 0x0F, 1039 1040 SR_COUNT = 0x10, 1041 1042 SR_RATE_UNKNOWN = 0x1F 1043 }; 1044 1045 enum dsp_download_state { 1046 DSP_DOWNLOAD_FAILED = -1, 1047 DSP_DOWNLOAD_INIT = 0, 1048 DSP_DOWNLOADING = 1, 1049 DSP_DOWNLOADED = 2 1050 }; 1051 1052 /* retrieve parameters from hda format */ 1053 #define get_hdafmt_chs(fmt) (fmt & 0xf) 1054 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 1055 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 1056 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 1057 1058 /* 1059 * CA0132 specific 1060 */ 1061 1062 struct ca0132_spec { 1063 const struct snd_kcontrol_new *mixers[5]; 1064 unsigned int num_mixers; 1065 const struct hda_verb *base_init_verbs; 1066 const struct hda_verb *base_exit_verbs; 1067 const struct hda_verb *chip_init_verbs; 1068 const struct hda_verb *desktop_init_verbs; 1069 struct hda_verb *spec_init_verbs; 1070 struct auto_pin_cfg autocfg; 1071 1072 /* Nodes configurations */ 1073 struct hda_multi_out multiout; 1074 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 1075 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 1076 unsigned int num_outputs; 1077 hda_nid_t input_pins[AUTO_PIN_LAST]; 1078 hda_nid_t adcs[AUTO_PIN_LAST]; 1079 hda_nid_t dig_out; 1080 hda_nid_t dig_in; 1081 unsigned int num_inputs; 1082 hda_nid_t shared_mic_nid; 1083 hda_nid_t shared_out_nid; 1084 hda_nid_t unsol_tag_hp; 1085 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 1086 hda_nid_t unsol_tag_amic1; 1087 1088 /* chip access */ 1089 struct mutex chipio_mutex; /* chip access mutex */ 1090 u32 curr_chip_addx; 1091 1092 /* DSP download related */ 1093 enum dsp_download_state dsp_state; 1094 unsigned int dsp_stream_id; 1095 unsigned int wait_scp; 1096 unsigned int wait_scp_header; 1097 unsigned int wait_num_data; 1098 unsigned int scp_resp_header; 1099 unsigned int scp_resp_data[4]; 1100 unsigned int scp_resp_count; 1101 bool startup_check_entered; 1102 bool dsp_reload; 1103 1104 /* mixer and effects related */ 1105 unsigned char dmic_ctl; 1106 int cur_out_type; 1107 int cur_mic_type; 1108 long vnode_lvol[VNODES_COUNT]; 1109 long vnode_rvol[VNODES_COUNT]; 1110 long vnode_lswitch[VNODES_COUNT]; 1111 long vnode_rswitch[VNODES_COUNT]; 1112 long effects_switch[EFFECTS_COUNT]; 1113 long voicefx_val; 1114 long cur_mic_boost; 1115 /* ca0132_alt control related values */ 1116 unsigned char in_enum_val; 1117 unsigned char out_enum_val; 1118 unsigned char channel_cfg_val; 1119 unsigned char speaker_range_val[2]; 1120 unsigned char mic_boost_enum_val; 1121 unsigned char smart_volume_setting; 1122 unsigned char bass_redirection_val; 1123 long bass_redirect_xover_freq; 1124 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1125 long xbass_xover_freq; 1126 long eq_preset_val; 1127 unsigned int tlv[4]; 1128 struct hda_vmaster_mute_hook vmaster_mute; 1129 /* AE-5 Control values */ 1130 unsigned char ae5_headphone_gain_val; 1131 unsigned char ae5_filter_val; 1132 /* ZxR Control Values */ 1133 unsigned char zxr_gain_set; 1134 1135 struct hda_codec *codec; 1136 struct delayed_work unsol_hp_work; 1137 1138 #ifdef ENABLE_TUNING_CONTROLS 1139 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1140 #endif 1141 /* 1142 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1143 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1144 * things. 1145 */ 1146 bool use_pci_mmio; 1147 void __iomem *mem_base; 1148 1149 /* 1150 * Whether or not to use the alt functions like alt_select_out, 1151 * alt_select_in, etc. Only used on desktop codecs for now, because of 1152 * surround sound support. 1153 */ 1154 bool use_alt_functions; 1155 1156 /* 1157 * Whether or not to use alt controls: volume effect sliders, EQ 1158 * presets, smart volume presets, and new control names with FX prefix. 1159 * Renames PlayEnhancement and CrystalVoice too. 1160 */ 1161 bool use_alt_controls; 1162 }; 1163 1164 /* 1165 * CA0132 quirks table 1166 */ 1167 enum { 1168 QUIRK_ALIENWARE, 1169 QUIRK_ALIENWARE_M17XR4, 1170 QUIRK_SBZ, 1171 QUIRK_ZXR, 1172 QUIRK_ZXR_DBPRO, 1173 QUIRK_R3DI, 1174 QUIRK_R3D, 1175 QUIRK_AE5, 1176 QUIRK_AE7, 1177 QUIRK_NONE = HDA_FIXUP_ID_NOT_SET, 1178 }; 1179 1180 #ifdef CONFIG_PCI 1181 #define ca0132_quirk(spec) ((spec)->codec->fixup_id) 1182 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) 1183 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) 1184 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) 1185 #else 1186 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) 1187 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) 1188 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) 1189 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) 1190 #endif 1191 1192 static const struct hda_pintbl alienware_pincfgs[] = { 1193 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1194 { 0x0c, 0x411111f0 }, /* N/A */ 1195 { 0x0d, 0x411111f0 }, /* N/A */ 1196 { 0x0e, 0x411111f0 }, /* N/A */ 1197 { 0x0f, 0x0321101f }, /* HP */ 1198 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1199 { 0x11, 0x03a11021 }, /* Mic */ 1200 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1201 { 0x13, 0x411111f0 }, /* N/A */ 1202 { 0x18, 0x411111f0 }, /* N/A */ 1203 {} 1204 }; 1205 1206 /* Sound Blaster Z pin configs taken from Windows Driver */ 1207 static const struct hda_pintbl sbz_pincfgs[] = { 1208 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1209 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1210 { 0x0d, 0x014510f0 }, /* Digital Out */ 1211 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1212 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1213 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1214 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1215 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1216 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1217 { 0x18, 0x50d000f0 }, /* N/A */ 1218 {} 1219 }; 1220 1221 /* Sound Blaster ZxR pin configs taken from Windows Driver */ 1222 static const struct hda_pintbl zxr_pincfgs[] = { 1223 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1224 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1225 { 0x0d, 0x014510f0 }, /* Digital Out */ 1226 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1227 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1228 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1229 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1230 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1231 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1232 { 0x18, 0x50d000f0 }, /* N/A */ 1233 {} 1234 }; 1235 1236 /* Recon3D pin configs taken from Windows Driver */ 1237 static const struct hda_pintbl r3d_pincfgs[] = { 1238 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1239 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1240 { 0x0d, 0x014510f0 }, /* Digital Out */ 1241 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1242 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1243 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1244 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1245 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1246 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1247 { 0x18, 0x50d000f0 }, /* N/A */ 1248 {} 1249 }; 1250 1251 /* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1252 static const struct hda_pintbl ae5_pincfgs[] = { 1253 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1254 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1255 { 0x0d, 0x014510f0 }, /* Digital Out */ 1256 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1257 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1258 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1259 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1260 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1261 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1262 { 0x18, 0x50d000f0 }, /* N/A */ 1263 {} 1264 }; 1265 1266 /* Recon3D integrated pin configs taken from Windows Driver */ 1267 static const struct hda_pintbl r3di_pincfgs[] = { 1268 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1269 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1270 { 0x0d, 0x014510f0 }, /* Digital Out */ 1271 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1272 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1273 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1274 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1275 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1276 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1277 { 0x18, 0x500000f0 }, /* N/A */ 1278 {} 1279 }; 1280 1281 static const struct hda_pintbl ae7_pincfgs[] = { 1282 { 0x0b, 0x01017010 }, 1283 { 0x0c, 0x014510f0 }, 1284 { 0x0d, 0x414510f0 }, 1285 { 0x0e, 0x01c520f0 }, 1286 { 0x0f, 0x01017114 }, 1287 { 0x10, 0x01017011 }, 1288 { 0x11, 0x018170ff }, 1289 { 0x12, 0x01a170f0 }, 1290 { 0x13, 0x908700f0 }, 1291 { 0x18, 0x500000f0 }, 1292 {} 1293 }; 1294 1295 static const struct hda_quirk ca0132_quirks[] = { 1296 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1297 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1298 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1299 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1300 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1301 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1302 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ), 1303 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), 1304 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1305 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1306 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1307 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI), 1308 SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI), 1309 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI), 1310 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1311 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D), 1312 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1313 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5), 1314 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7), 1315 {} 1316 }; 1317 1318 static const struct hda_model_fixup ca0132_quirk_models[] = { 1319 { .id = QUIRK_ALIENWARE, .name = "alienware" }, 1320 { .id = QUIRK_ALIENWARE_M17XR4, .name = "alienware-m17xr4" }, 1321 { .id = QUIRK_SBZ, .name = "sbz" }, 1322 { .id = QUIRK_ZXR, .name = "zxr" }, 1323 { .id = QUIRK_ZXR_DBPRO, .name = "zxr-dbpro" }, 1324 { .id = QUIRK_R3DI, .name = "r3di" }, 1325 { .id = QUIRK_R3D, .name = "r3d" }, 1326 { .id = QUIRK_AE5, .name = "ae5" }, 1327 { .id = QUIRK_AE7, .name = "ae7" }, 1328 {} 1329 }; 1330 1331 /* Output selection quirk info structures. */ 1332 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3 1333 #define MAX_QUIRK_SCP_SET_VALS 2 1334 struct ca0132_alt_out_set_info { 1335 unsigned int dac2port; /* ParamID 0x0d value. */ 1336 1337 bool has_hda_gpio; 1338 char hda_gpio_pin; 1339 char hda_gpio_set; 1340 1341 unsigned int mmio_gpio_count; 1342 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1343 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS]; 1344 1345 unsigned int scp_cmds_count; 1346 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS]; 1347 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS]; 1348 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS]; 1349 1350 bool has_chipio_write; 1351 unsigned int chipio_write_addr; 1352 unsigned int chipio_write_data; 1353 }; 1354 1355 struct ca0132_alt_out_set_quirk_data { 1356 int quirk_id; 1357 1358 bool has_headphone_gain; 1359 bool is_ae_series; 1360 1361 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS]; 1362 }; 1363 1364 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = { 1365 { .quirk_id = QUIRK_R3DI, 1366 .has_headphone_gain = false, 1367 .is_ae_series = false, 1368 .out_set_info = { 1369 /* Speakers. */ 1370 { .dac2port = 0x24, 1371 .has_hda_gpio = true, 1372 .hda_gpio_pin = 2, 1373 .hda_gpio_set = 1, 1374 .mmio_gpio_count = 0, 1375 .scp_cmds_count = 0, 1376 .has_chipio_write = false, 1377 }, 1378 /* Headphones. */ 1379 { .dac2port = 0x21, 1380 .has_hda_gpio = true, 1381 .hda_gpio_pin = 2, 1382 .hda_gpio_set = 0, 1383 .mmio_gpio_count = 0, 1384 .scp_cmds_count = 0, 1385 .has_chipio_write = false, 1386 } }, 1387 }, 1388 { .quirk_id = QUIRK_R3D, 1389 .has_headphone_gain = false, 1390 .is_ae_series = false, 1391 .out_set_info = { 1392 /* Speakers. */ 1393 { .dac2port = 0x24, 1394 .has_hda_gpio = false, 1395 .mmio_gpio_count = 1, 1396 .mmio_gpio_pin = { 1 }, 1397 .mmio_gpio_set = { 1 }, 1398 .scp_cmds_count = 0, 1399 .has_chipio_write = false, 1400 }, 1401 /* Headphones. */ 1402 { .dac2port = 0x21, 1403 .has_hda_gpio = false, 1404 .mmio_gpio_count = 1, 1405 .mmio_gpio_pin = { 1 }, 1406 .mmio_gpio_set = { 0 }, 1407 .scp_cmds_count = 0, 1408 .has_chipio_write = false, 1409 } }, 1410 }, 1411 { .quirk_id = QUIRK_SBZ, 1412 .has_headphone_gain = false, 1413 .is_ae_series = false, 1414 .out_set_info = { 1415 /* Speakers. */ 1416 { .dac2port = 0x18, 1417 .has_hda_gpio = false, 1418 .mmio_gpio_count = 3, 1419 .mmio_gpio_pin = { 7, 4, 1 }, 1420 .mmio_gpio_set = { 0, 1, 1 }, 1421 .scp_cmds_count = 0, 1422 .has_chipio_write = false, }, 1423 /* Headphones. */ 1424 { .dac2port = 0x12, 1425 .has_hda_gpio = false, 1426 .mmio_gpio_count = 3, 1427 .mmio_gpio_pin = { 7, 4, 1 }, 1428 .mmio_gpio_set = { 1, 1, 0 }, 1429 .scp_cmds_count = 0, 1430 .has_chipio_write = false, 1431 } }, 1432 }, 1433 { .quirk_id = QUIRK_ZXR, 1434 .has_headphone_gain = true, 1435 .is_ae_series = false, 1436 .out_set_info = { 1437 /* Speakers. */ 1438 { .dac2port = 0x24, 1439 .has_hda_gpio = false, 1440 .mmio_gpio_count = 3, 1441 .mmio_gpio_pin = { 2, 3, 5 }, 1442 .mmio_gpio_set = { 1, 1, 0 }, 1443 .scp_cmds_count = 0, 1444 .has_chipio_write = false, 1445 }, 1446 /* Headphones. */ 1447 { .dac2port = 0x21, 1448 .has_hda_gpio = false, 1449 .mmio_gpio_count = 3, 1450 .mmio_gpio_pin = { 2, 3, 5 }, 1451 .mmio_gpio_set = { 0, 1, 1 }, 1452 .scp_cmds_count = 0, 1453 .has_chipio_write = false, 1454 } }, 1455 }, 1456 { .quirk_id = QUIRK_AE5, 1457 .has_headphone_gain = true, 1458 .is_ae_series = true, 1459 .out_set_info = { 1460 /* Speakers. */ 1461 { .dac2port = 0xa4, 1462 .has_hda_gpio = false, 1463 .mmio_gpio_count = 0, 1464 .scp_cmds_count = 2, 1465 .scp_cmd_mid = { 0x96, 0x96 }, 1466 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1467 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1468 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1469 .has_chipio_write = true, 1470 .chipio_write_addr = 0x0018b03c, 1471 .chipio_write_data = 0x00000012 1472 }, 1473 /* Headphones. */ 1474 { .dac2port = 0xa1, 1475 .has_hda_gpio = false, 1476 .mmio_gpio_count = 0, 1477 .scp_cmds_count = 2, 1478 .scp_cmd_mid = { 0x96, 0x96 }, 1479 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1480 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1481 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1482 .has_chipio_write = true, 1483 .chipio_write_addr = 0x0018b03c, 1484 .chipio_write_data = 0x00000012 1485 } }, 1486 }, 1487 { .quirk_id = QUIRK_AE7, 1488 .has_headphone_gain = true, 1489 .is_ae_series = true, 1490 .out_set_info = { 1491 /* Speakers. */ 1492 { .dac2port = 0x58, 1493 .has_hda_gpio = false, 1494 .mmio_gpio_count = 1, 1495 .mmio_gpio_pin = { 0 }, 1496 .mmio_gpio_set = { 1 }, 1497 .scp_cmds_count = 2, 1498 .scp_cmd_mid = { 0x96, 0x96 }, 1499 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1500 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1501 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO }, 1502 .has_chipio_write = true, 1503 .chipio_write_addr = 0x0018b03c, 1504 .chipio_write_data = 0x00000000 1505 }, 1506 /* Headphones. */ 1507 { .dac2port = 0x58, 1508 .has_hda_gpio = false, 1509 .mmio_gpio_count = 1, 1510 .mmio_gpio_pin = { 0 }, 1511 .mmio_gpio_set = { 1 }, 1512 .scp_cmds_count = 2, 1513 .scp_cmd_mid = { 0x96, 0x96 }, 1514 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT, 1515 SPEAKER_TUNING_FRONT_RIGHT_INVERT }, 1516 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE }, 1517 .has_chipio_write = true, 1518 .chipio_write_addr = 0x0018b03c, 1519 .chipio_write_data = 0x00000010 1520 } }, 1521 } 1522 }; 1523 1524 /* 1525 * CA0132 codec access 1526 */ 1527 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1528 unsigned int verb, unsigned int parm, unsigned int *res) 1529 { 1530 unsigned int response; 1531 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1532 *res = response; 1533 1534 return ((response == -1) ? -1 : 0); 1535 } 1536 1537 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1538 unsigned short converter_format, unsigned int *res) 1539 { 1540 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1541 converter_format & 0xffff, res); 1542 } 1543 1544 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1545 hda_nid_t nid, unsigned char stream, 1546 unsigned char channel, unsigned int *res) 1547 { 1548 unsigned char converter_stream_channel = 0; 1549 1550 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1551 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1552 converter_stream_channel, res); 1553 } 1554 1555 /* Chip access helper function */ 1556 static int chipio_send(struct hda_codec *codec, 1557 unsigned int reg, 1558 unsigned int data) 1559 { 1560 unsigned int res; 1561 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1562 1563 /* send bits of data specified by reg */ 1564 do { 1565 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1566 reg, data); 1567 if (res == VENDOR_STATUS_CHIPIO_OK) 1568 return 0; 1569 msleep(20); 1570 } while (time_before(jiffies, timeout)); 1571 1572 return -EIO; 1573 } 1574 1575 /* 1576 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1577 */ 1578 static int chipio_write_address(struct hda_codec *codec, 1579 unsigned int chip_addx) 1580 { 1581 struct ca0132_spec *spec = codec->spec; 1582 int res; 1583 1584 if (spec->curr_chip_addx == chip_addx) 1585 return 0; 1586 1587 /* send low 16 bits of the address */ 1588 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1589 chip_addx & 0xffff); 1590 1591 if (res != -EIO) { 1592 /* send high 16 bits of the address */ 1593 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1594 chip_addx >> 16); 1595 } 1596 1597 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1598 1599 return res; 1600 } 1601 1602 /* 1603 * Write data through the vendor widget -- NOT protected by the Mutex! 1604 */ 1605 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1606 { 1607 struct ca0132_spec *spec = codec->spec; 1608 int res; 1609 1610 /* send low 16 bits of the data */ 1611 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1612 1613 if (res != -EIO) { 1614 /* send high 16 bits of the data */ 1615 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1616 data >> 16); 1617 } 1618 1619 /*If no error encountered, automatically increment the address 1620 as per chip behaviour*/ 1621 spec->curr_chip_addx = (res != -EIO) ? 1622 (spec->curr_chip_addx + 4) : ~0U; 1623 return res; 1624 } 1625 1626 /* 1627 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1628 */ 1629 static int chipio_write_data_multiple(struct hda_codec *codec, 1630 const u32 *data, 1631 unsigned int count) 1632 { 1633 int status = 0; 1634 1635 if (data == NULL) { 1636 codec_dbg(codec, "chipio_write_data null ptr\n"); 1637 return -EINVAL; 1638 } 1639 1640 while ((count-- != 0) && (status == 0)) 1641 status = chipio_write_data(codec, *data++); 1642 1643 return status; 1644 } 1645 1646 1647 /* 1648 * Read data through the vendor widget -- NOT protected by the Mutex! 1649 */ 1650 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1651 { 1652 struct ca0132_spec *spec = codec->spec; 1653 int res; 1654 1655 /* post read */ 1656 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1657 1658 if (res != -EIO) { 1659 /* read status */ 1660 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1661 } 1662 1663 if (res != -EIO) { 1664 /* read data */ 1665 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1666 VENDOR_CHIPIO_HIC_READ_DATA, 1667 0); 1668 } 1669 1670 /*If no error encountered, automatically increment the address 1671 as per chip behaviour*/ 1672 spec->curr_chip_addx = (res != -EIO) ? 1673 (spec->curr_chip_addx + 4) : ~0U; 1674 return res; 1675 } 1676 1677 /* 1678 * Write given value to the given address through the chip I/O widget. 1679 * protected by the Mutex 1680 */ 1681 static int chipio_write(struct hda_codec *codec, 1682 unsigned int chip_addx, const unsigned int data) 1683 { 1684 struct ca0132_spec *spec = codec->spec; 1685 int err; 1686 1687 guard(mutex)(&spec->chipio_mutex); 1688 1689 /* write the address, and if successful proceed to write data */ 1690 err = chipio_write_address(codec, chip_addx); 1691 if (err < 0) 1692 return err; 1693 1694 return chipio_write_data(codec, data); 1695 } 1696 1697 /* 1698 * Write given value to the given address through the chip I/O widget. 1699 * not protected by the Mutex 1700 */ 1701 static int chipio_write_no_mutex(struct hda_codec *codec, 1702 unsigned int chip_addx, const unsigned int data) 1703 { 1704 int err; 1705 1706 1707 /* write the address, and if successful proceed to write data */ 1708 err = chipio_write_address(codec, chip_addx); 1709 if (err < 0) 1710 goto exit; 1711 1712 err = chipio_write_data(codec, data); 1713 if (err < 0) 1714 goto exit; 1715 1716 exit: 1717 return err; 1718 } 1719 1720 /* 1721 * Write multiple values to the given address through the chip I/O widget. 1722 * protected by the Mutex 1723 */ 1724 static int chipio_write_multiple(struct hda_codec *codec, 1725 u32 chip_addx, 1726 const u32 *data, 1727 unsigned int count) 1728 { 1729 struct ca0132_spec *spec = codec->spec; 1730 int status; 1731 1732 guard(mutex)(&spec->chipio_mutex); 1733 status = chipio_write_address(codec, chip_addx); 1734 if (status < 0) 1735 return status; 1736 1737 return chipio_write_data_multiple(codec, data, count); 1738 } 1739 1740 /* 1741 * Read the given address through the chip I/O widget 1742 * protected by the Mutex 1743 */ 1744 static int chipio_read(struct hda_codec *codec, 1745 unsigned int chip_addx, unsigned int *data) 1746 { 1747 struct ca0132_spec *spec = codec->spec; 1748 int err; 1749 1750 guard(mutex)(&spec->chipio_mutex); 1751 1752 /* write the address, and if successful proceed to write data */ 1753 err = chipio_write_address(codec, chip_addx); 1754 if (err < 0) 1755 return err; 1756 1757 return chipio_read_data(codec, data); 1758 } 1759 1760 /* 1761 * Set chip control flags through the chip I/O widget. 1762 */ 1763 static void chipio_set_control_flag(struct hda_codec *codec, 1764 enum control_flag_id flag_id, 1765 bool flag_state) 1766 { 1767 unsigned int val; 1768 unsigned int flag_bit; 1769 1770 flag_bit = (flag_state ? 1 : 0); 1771 val = (flag_bit << 7) | (flag_id); 1772 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1773 VENDOR_CHIPIO_FLAG_SET, val); 1774 } 1775 1776 /* 1777 * Set chip parameters through the chip I/O widget. 1778 */ 1779 static void chipio_set_control_param(struct hda_codec *codec, 1780 enum control_param_id param_id, int param_val) 1781 { 1782 struct ca0132_spec *spec = codec->spec; 1783 int val; 1784 1785 if ((param_id < 32) && (param_val < 8)) { 1786 val = (param_val << 5) | (param_id); 1787 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1788 VENDOR_CHIPIO_PARAM_SET, val); 1789 } else { 1790 guard(mutex)(&spec->chipio_mutex); 1791 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1792 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1793 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1794 param_id); 1795 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1796 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1797 param_val); 1798 } 1799 } 1800 } 1801 1802 /* 1803 * Set chip parameters through the chip I/O widget. NO MUTEX. 1804 */ 1805 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1806 enum control_param_id param_id, int param_val) 1807 { 1808 int val; 1809 1810 if ((param_id < 32) && (param_val < 8)) { 1811 val = (param_val << 5) | (param_id); 1812 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1813 VENDOR_CHIPIO_PARAM_SET, val); 1814 } else { 1815 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1816 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1817 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1818 param_id); 1819 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1820 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1821 param_val); 1822 } 1823 } 1824 } 1825 /* 1826 * Connect stream to a source point, and then connect 1827 * that source point to a destination point. 1828 */ 1829 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1830 int streamid, int source_point, int dest_point) 1831 { 1832 chipio_set_control_param_no_mutex(codec, 1833 CONTROL_PARAM_STREAM_ID, streamid); 1834 chipio_set_control_param_no_mutex(codec, 1835 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1836 chipio_set_control_param_no_mutex(codec, 1837 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1838 } 1839 1840 /* 1841 * Set number of channels in the selected stream. 1842 */ 1843 static void chipio_set_stream_channels(struct hda_codec *codec, 1844 int streamid, unsigned int channels) 1845 { 1846 chipio_set_control_param_no_mutex(codec, 1847 CONTROL_PARAM_STREAM_ID, streamid); 1848 chipio_set_control_param_no_mutex(codec, 1849 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1850 } 1851 1852 /* 1853 * Enable/Disable audio stream. 1854 */ 1855 static void chipio_set_stream_control(struct hda_codec *codec, 1856 int streamid, int enable) 1857 { 1858 chipio_set_control_param_no_mutex(codec, 1859 CONTROL_PARAM_STREAM_ID, streamid); 1860 chipio_set_control_param_no_mutex(codec, 1861 CONTROL_PARAM_STREAM_CONTROL, enable); 1862 } 1863 1864 /* 1865 * Get ChipIO audio stream's status. 1866 */ 1867 static void chipio_get_stream_control(struct hda_codec *codec, 1868 int streamid, unsigned int *enable) 1869 { 1870 chipio_set_control_param_no_mutex(codec, 1871 CONTROL_PARAM_STREAM_ID, streamid); 1872 *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1873 VENDOR_CHIPIO_PARAM_GET, 1874 CONTROL_PARAM_STREAM_CONTROL); 1875 } 1876 1877 /* 1878 * Set sampling rate of the connection point. NO MUTEX. 1879 */ 1880 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1881 int connid, enum ca0132_sample_rate rate) 1882 { 1883 chipio_set_control_param_no_mutex(codec, 1884 CONTROL_PARAM_CONN_POINT_ID, connid); 1885 chipio_set_control_param_no_mutex(codec, 1886 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1887 } 1888 1889 /* 1890 * Set sampling rate of the connection point. 1891 */ 1892 static void chipio_set_conn_rate(struct hda_codec *codec, 1893 int connid, enum ca0132_sample_rate rate) 1894 { 1895 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1896 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1897 rate); 1898 } 1899 1900 /* 1901 * Writes to the 8051's internal address space directly instead of indirectly, 1902 * giving access to the special function registers located at addresses 1903 * 0x80-0xFF. 1904 */ 1905 static void chipio_8051_write_direct(struct hda_codec *codec, 1906 unsigned int addr, unsigned int data) 1907 { 1908 unsigned int verb; 1909 1910 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1911 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1912 } 1913 1914 /* 1915 * Writes to the 8051's exram, which has 16-bits of address space. 1916 * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff. 1917 * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by 1918 * setting the pmem bank selection SFR. 1919 * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff 1920 * being writable. 1921 */ 1922 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr) 1923 { 1924 unsigned int tmp; 1925 1926 /* Lower 8-bits. */ 1927 tmp = addr & 0xff; 1928 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1929 VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp); 1930 1931 /* Upper 8-bits. */ 1932 tmp = (addr >> 8) & 0xff; 1933 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1934 VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp); 1935 } 1936 1937 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data) 1938 { 1939 /* 8-bits of data. */ 1940 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1941 VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff); 1942 } 1943 1944 static unsigned int chipio_8051_get_data(struct hda_codec *codec) 1945 { 1946 return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1947 VENDOR_CHIPIO_8051_DATA_READ, 0); 1948 } 1949 1950 /* PLL_PMU writes share the lower address register of the 8051 exram writes. */ 1951 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data) 1952 { 1953 /* 8-bits of data. */ 1954 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1955 VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff); 1956 } 1957 1958 static void chipio_8051_write_exram(struct hda_codec *codec, 1959 unsigned int addr, unsigned int data) 1960 { 1961 struct ca0132_spec *spec = codec->spec; 1962 1963 guard(mutex)(&spec->chipio_mutex); 1964 1965 chipio_8051_set_address(codec, addr); 1966 chipio_8051_set_data(codec, data); 1967 } 1968 1969 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec, 1970 unsigned int addr, unsigned int data) 1971 { 1972 chipio_8051_set_address(codec, addr); 1973 chipio_8051_set_data(codec, data); 1974 } 1975 1976 /* Readback data from the 8051's exram. No mutex. */ 1977 static void chipio_8051_read_exram(struct hda_codec *codec, 1978 unsigned int addr, unsigned int *data) 1979 { 1980 chipio_8051_set_address(codec, addr); 1981 *data = chipio_8051_get_data(codec); 1982 } 1983 1984 static void chipio_8051_write_pll_pmu(struct hda_codec *codec, 1985 unsigned int addr, unsigned int data) 1986 { 1987 struct ca0132_spec *spec = codec->spec; 1988 1989 guard(mutex)(&spec->chipio_mutex); 1990 1991 chipio_8051_set_address(codec, addr & 0xff); 1992 chipio_8051_set_data_pll(codec, data); 1993 } 1994 1995 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec, 1996 unsigned int addr, unsigned int data) 1997 { 1998 chipio_8051_set_address(codec, addr & 0xff); 1999 chipio_8051_set_data_pll(codec, data); 2000 } 2001 2002 /* 2003 * Enable clocks. 2004 */ 2005 static void chipio_enable_clocks(struct hda_codec *codec) 2006 { 2007 struct ca0132_spec *spec = codec->spec; 2008 2009 guard(mutex)(&spec->chipio_mutex); 2010 2011 chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff); 2012 chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b); 2013 chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff); 2014 } 2015 2016 /* 2017 * CA0132 DSP IO stuffs 2018 */ 2019 static int dspio_send(struct hda_codec *codec, unsigned int reg, 2020 unsigned int data) 2021 { 2022 int res; 2023 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2024 2025 /* send bits of data specified by reg to dsp */ 2026 do { 2027 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 2028 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 2029 return res; 2030 msleep(20); 2031 } while (time_before(jiffies, timeout)); 2032 2033 return -EIO; 2034 } 2035 2036 /* 2037 * Wait for DSP to be ready for commands 2038 */ 2039 static void dspio_write_wait(struct hda_codec *codec) 2040 { 2041 int status; 2042 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2043 2044 do { 2045 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2046 VENDOR_DSPIO_STATUS, 0); 2047 if ((status == VENDOR_STATUS_DSPIO_OK) || 2048 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 2049 break; 2050 msleep(1); 2051 } while (time_before(jiffies, timeout)); 2052 } 2053 2054 /* 2055 * Write SCP data to DSP 2056 */ 2057 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 2058 { 2059 struct ca0132_spec *spec = codec->spec; 2060 int status; 2061 2062 dspio_write_wait(codec); 2063 2064 guard(mutex)(&spec->chipio_mutex); 2065 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 2066 scp_data & 0xffff); 2067 if (status < 0) 2068 return status; 2069 2070 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 2071 scp_data >> 16); 2072 if (status < 0) 2073 return status; 2074 2075 /* OK, now check if the write itself has executed*/ 2076 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2077 VENDOR_DSPIO_STATUS, 0); 2078 2079 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 2080 -EIO : 0; 2081 } 2082 2083 /* 2084 * Write multiple SCP data to DSP 2085 */ 2086 static int dspio_write_multiple(struct hda_codec *codec, 2087 unsigned int *buffer, unsigned int size) 2088 { 2089 int status = 0; 2090 unsigned int count; 2091 2092 if (buffer == NULL) 2093 return -EINVAL; 2094 2095 count = 0; 2096 while (count < size) { 2097 status = dspio_write(codec, *buffer++); 2098 if (status != 0) 2099 break; 2100 count++; 2101 } 2102 2103 return status; 2104 } 2105 2106 static int dspio_read(struct hda_codec *codec, unsigned int *data) 2107 { 2108 int status; 2109 2110 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 2111 if (status == -EIO) 2112 return status; 2113 2114 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 2115 if (status == -EIO || 2116 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 2117 return -EIO; 2118 2119 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 2120 VENDOR_DSPIO_SCP_READ_DATA, 0); 2121 2122 return 0; 2123 } 2124 2125 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 2126 unsigned int *buf_size, unsigned int size_count) 2127 { 2128 int status = 0; 2129 unsigned int size = *buf_size; 2130 unsigned int count; 2131 unsigned int skip_count; 2132 unsigned int dummy; 2133 2134 if (buffer == NULL) 2135 return -1; 2136 2137 count = 0; 2138 while (count < size && count < size_count) { 2139 status = dspio_read(codec, buffer++); 2140 if (status != 0) 2141 break; 2142 count++; 2143 } 2144 2145 skip_count = count; 2146 if (status == 0) { 2147 while (skip_count < size) { 2148 status = dspio_read(codec, &dummy); 2149 if (status != 0) 2150 break; 2151 skip_count++; 2152 } 2153 } 2154 *buf_size = count; 2155 2156 return status; 2157 } 2158 2159 /* 2160 * Construct the SCP header using corresponding fields 2161 */ 2162 static inline unsigned int 2163 make_scp_header(unsigned int target_id, unsigned int source_id, 2164 unsigned int get_flag, unsigned int req, 2165 unsigned int device_flag, unsigned int resp_flag, 2166 unsigned int error_flag, unsigned int data_size) 2167 { 2168 unsigned int header = 0; 2169 2170 header = (data_size & 0x1f) << 27; 2171 header |= (error_flag & 0x01) << 26; 2172 header |= (resp_flag & 0x01) << 25; 2173 header |= (device_flag & 0x01) << 24; 2174 header |= (req & 0x7f) << 17; 2175 header |= (get_flag & 0x01) << 16; 2176 header |= (source_id & 0xff) << 8; 2177 header |= target_id & 0xff; 2178 2179 return header; 2180 } 2181 2182 /* 2183 * Extract corresponding fields from SCP header 2184 */ 2185 static inline void 2186 extract_scp_header(unsigned int header, 2187 unsigned int *target_id, unsigned int *source_id, 2188 unsigned int *get_flag, unsigned int *req, 2189 unsigned int *device_flag, unsigned int *resp_flag, 2190 unsigned int *error_flag, unsigned int *data_size) 2191 { 2192 if (data_size) 2193 *data_size = (header >> 27) & 0x1f; 2194 if (error_flag) 2195 *error_flag = (header >> 26) & 0x01; 2196 if (resp_flag) 2197 *resp_flag = (header >> 25) & 0x01; 2198 if (device_flag) 2199 *device_flag = (header >> 24) & 0x01; 2200 if (req) 2201 *req = (header >> 17) & 0x7f; 2202 if (get_flag) 2203 *get_flag = (header >> 16) & 0x01; 2204 if (source_id) 2205 *source_id = (header >> 8) & 0xff; 2206 if (target_id) 2207 *target_id = header & 0xff; 2208 } 2209 2210 #define SCP_MAX_DATA_WORDS (16) 2211 2212 /* Structure to contain any SCP message */ 2213 struct scp_msg { 2214 unsigned int hdr; 2215 unsigned int data[SCP_MAX_DATA_WORDS]; 2216 }; 2217 2218 static void dspio_clear_response_queue(struct hda_codec *codec) 2219 { 2220 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2221 unsigned int dummy = 0; 2222 int status; 2223 2224 /* clear all from the response queue */ 2225 do { 2226 status = dspio_read(codec, &dummy); 2227 } while (status == 0 && time_before(jiffies, timeout)); 2228 } 2229 2230 static int dspio_get_response_data(struct hda_codec *codec) 2231 { 2232 struct ca0132_spec *spec = codec->spec; 2233 unsigned int data = 0; 2234 unsigned int count; 2235 2236 if (dspio_read(codec, &data) < 0) 2237 return -EIO; 2238 2239 if ((data & 0x00ffffff) == spec->wait_scp_header) { 2240 spec->scp_resp_header = data; 2241 spec->scp_resp_count = data >> 27; 2242 count = spec->wait_num_data; 2243 dspio_read_multiple(codec, spec->scp_resp_data, 2244 &spec->scp_resp_count, count); 2245 return 0; 2246 } 2247 2248 return -EIO; 2249 } 2250 2251 /* 2252 * Send SCP message to DSP 2253 */ 2254 static int dspio_send_scp_message(struct hda_codec *codec, 2255 unsigned char *send_buf, 2256 unsigned int send_buf_size, 2257 unsigned char *return_buf, 2258 unsigned int return_buf_size, 2259 unsigned int *bytes_returned) 2260 { 2261 struct ca0132_spec *spec = codec->spec; 2262 int status; 2263 unsigned int scp_send_size = 0; 2264 unsigned int total_size; 2265 bool waiting_for_resp = false; 2266 unsigned int header; 2267 struct scp_msg *ret_msg; 2268 unsigned int resp_src_id, resp_target_id; 2269 unsigned int data_size, src_id, target_id, get_flag, device_flag; 2270 2271 if (bytes_returned) 2272 *bytes_returned = 0; 2273 2274 /* get scp header from buffer */ 2275 header = *((unsigned int *)send_buf); 2276 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 2277 &device_flag, NULL, NULL, &data_size); 2278 scp_send_size = data_size + 1; 2279 total_size = (scp_send_size * 4); 2280 2281 if (send_buf_size < total_size) 2282 return -EINVAL; 2283 2284 if (get_flag || device_flag) { 2285 if (!return_buf || return_buf_size < 4 || !bytes_returned) 2286 return -EINVAL; 2287 2288 spec->wait_scp_header = *((unsigned int *)send_buf); 2289 2290 /* swap source id with target id */ 2291 resp_target_id = src_id; 2292 resp_src_id = target_id; 2293 spec->wait_scp_header &= 0xffff0000; 2294 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 2295 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 2296 spec->wait_scp = 1; 2297 waiting_for_resp = true; 2298 } 2299 2300 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 2301 scp_send_size); 2302 if (status < 0) { 2303 spec->wait_scp = 0; 2304 return status; 2305 } 2306 2307 if (waiting_for_resp) { 2308 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 2309 memset(return_buf, 0, return_buf_size); 2310 do { 2311 msleep(20); 2312 } while (spec->wait_scp && time_before(jiffies, timeout)); 2313 waiting_for_resp = false; 2314 if (!spec->wait_scp) { 2315 ret_msg = (struct scp_msg *)return_buf; 2316 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 2317 memcpy(&ret_msg->data, spec->scp_resp_data, 2318 spec->wait_num_data); 2319 *bytes_returned = (spec->scp_resp_count + 1) * 4; 2320 status = 0; 2321 } else { 2322 status = -EIO; 2323 } 2324 spec->wait_scp = 0; 2325 } 2326 2327 return status; 2328 } 2329 2330 /** 2331 * dspio_scp - Prepare and send the SCP message to DSP 2332 * @codec: the HDA codec 2333 * @mod_id: ID of the DSP module to send the command 2334 * @src_id: ID of the source 2335 * @req: ID of request to send to the DSP module 2336 * @dir: SET or GET 2337 * @data: pointer to the data to send with the request, request specific 2338 * @len: length of the data, in bytes 2339 * @reply: point to the buffer to hold data returned for a reply 2340 * @reply_len: length of the reply buffer returned from GET 2341 * 2342 * Returns zero or a negative error code. 2343 */ 2344 static int dspio_scp(struct hda_codec *codec, 2345 int mod_id, int src_id, int req, int dir, const void *data, 2346 unsigned int len, void *reply, unsigned int *reply_len) 2347 { 2348 int status = 0; 2349 struct scp_msg scp_send, scp_reply; 2350 unsigned int ret_bytes, send_size, ret_size; 2351 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 2352 unsigned int reply_data_size; 2353 2354 memset(&scp_send, 0, sizeof(scp_send)); 2355 memset(&scp_reply, 0, sizeof(scp_reply)); 2356 2357 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 2358 return -EINVAL; 2359 2360 if (dir == SCP_GET && reply == NULL) { 2361 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 2362 return -EINVAL; 2363 } 2364 2365 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 2366 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 2367 return -EINVAL; 2368 } 2369 2370 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 2371 0, 0, 0, len/sizeof(unsigned int)); 2372 if (data != NULL && len > 0) { 2373 len = min((unsigned int)(sizeof(scp_send.data)), len); 2374 memcpy(scp_send.data, data, len); 2375 } 2376 2377 ret_bytes = 0; 2378 send_size = sizeof(unsigned int) + len; 2379 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 2380 send_size, (unsigned char *)&scp_reply, 2381 sizeof(scp_reply), &ret_bytes); 2382 2383 if (status < 0) { 2384 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 2385 return status; 2386 } 2387 2388 /* extract send and reply headers members */ 2389 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 2390 NULL, NULL, NULL, NULL, NULL); 2391 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 2392 &reply_resp_flag, &reply_error_flag, 2393 &reply_data_size); 2394 2395 if (!send_get_flag) 2396 return 0; 2397 2398 if (reply_resp_flag && !reply_error_flag) { 2399 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 2400 / sizeof(unsigned int); 2401 2402 if (*reply_len < ret_size*sizeof(unsigned int)) { 2403 codec_dbg(codec, "reply too long for buf\n"); 2404 return -EINVAL; 2405 } else if (ret_size != reply_data_size) { 2406 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 2407 return -EINVAL; 2408 } else if (!reply) { 2409 codec_dbg(codec, "NULL reply\n"); 2410 return -EINVAL; 2411 } else { 2412 *reply_len = ret_size*sizeof(unsigned int); 2413 memcpy(reply, scp_reply.data, *reply_len); 2414 } 2415 } else { 2416 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2417 return -EIO; 2418 } 2419 2420 return status; 2421 } 2422 2423 /* 2424 * Set DSP parameters 2425 */ 2426 static int dspio_set_param(struct hda_codec *codec, int mod_id, 2427 int src_id, int req, const void *data, unsigned int len) 2428 { 2429 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2430 NULL); 2431 } 2432 2433 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2434 int req, const unsigned int data) 2435 { 2436 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2437 sizeof(unsigned int)); 2438 } 2439 2440 /* 2441 * Allocate a DSP DMA channel via an SCP message 2442 */ 2443 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2444 { 2445 int status = 0; 2446 unsigned int size = sizeof(*dma_chan); 2447 2448 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2449 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2450 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2451 dma_chan, &size); 2452 2453 if (status < 0) { 2454 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2455 return status; 2456 } 2457 2458 if ((*dma_chan + 1) == 0) { 2459 codec_dbg(codec, "no free dma channels to allocate\n"); 2460 return -EBUSY; 2461 } 2462 2463 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2464 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2465 2466 return status; 2467 } 2468 2469 /* 2470 * Free a DSP DMA via an SCP message 2471 */ 2472 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2473 { 2474 int status = 0; 2475 unsigned int dummy = 0; 2476 2477 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2478 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2479 2480 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2481 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2482 sizeof(dma_chan), NULL, &dummy); 2483 2484 if (status < 0) { 2485 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2486 return status; 2487 } 2488 2489 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2490 2491 return status; 2492 } 2493 2494 /* 2495 * (Re)start the DSP 2496 */ 2497 static int dsp_set_run_state(struct hda_codec *codec) 2498 { 2499 unsigned int dbg_ctrl_reg; 2500 unsigned int halt_state; 2501 int err; 2502 2503 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2504 if (err < 0) 2505 return err; 2506 2507 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2508 DSP_DBGCNTL_STATE_LOBIT; 2509 2510 if (halt_state != 0) { 2511 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2512 DSP_DBGCNTL_SS_MASK); 2513 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2514 dbg_ctrl_reg); 2515 if (err < 0) 2516 return err; 2517 2518 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2519 DSP_DBGCNTL_EXEC_MASK; 2520 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2521 dbg_ctrl_reg); 2522 if (err < 0) 2523 return err; 2524 } 2525 2526 return 0; 2527 } 2528 2529 /* 2530 * Reset the DSP 2531 */ 2532 static int dsp_reset(struct hda_codec *codec) 2533 { 2534 unsigned int res; 2535 int retry = 20; 2536 2537 codec_dbg(codec, "dsp_reset\n"); 2538 do { 2539 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2540 retry--; 2541 } while (res == -EIO && retry); 2542 2543 if (!retry) { 2544 codec_dbg(codec, "dsp_reset timeout\n"); 2545 return -EIO; 2546 } 2547 2548 return 0; 2549 } 2550 2551 /* 2552 * Convert chip address to DSP address 2553 */ 2554 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2555 bool *code, bool *yram) 2556 { 2557 *code = *yram = false; 2558 2559 if (UC_RANGE(chip_addx, 1)) { 2560 *code = true; 2561 return UC_OFF(chip_addx); 2562 } else if (X_RANGE_ALL(chip_addx, 1)) { 2563 return X_OFF(chip_addx); 2564 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2565 *yram = true; 2566 return Y_OFF(chip_addx); 2567 } 2568 2569 return INVALID_CHIP_ADDRESS; 2570 } 2571 2572 /* 2573 * Check if the DSP DMA is active 2574 */ 2575 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2576 { 2577 unsigned int dma_chnlstart_reg; 2578 2579 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2580 2581 return ((dma_chnlstart_reg & (1 << 2582 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2583 } 2584 2585 static int dsp_dma_setup_common(struct hda_codec *codec, 2586 unsigned int chip_addx, 2587 unsigned int dma_chan, 2588 unsigned int port_map_mask, 2589 bool ovly) 2590 { 2591 int status = 0; 2592 unsigned int chnl_prop; 2593 unsigned int dsp_addx; 2594 unsigned int active; 2595 bool code, yram; 2596 2597 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2598 2599 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2600 codec_dbg(codec, "dma chan num invalid\n"); 2601 return -EINVAL; 2602 } 2603 2604 if (dsp_is_dma_active(codec, dma_chan)) { 2605 codec_dbg(codec, "dma already active\n"); 2606 return -EBUSY; 2607 } 2608 2609 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2610 2611 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2612 codec_dbg(codec, "invalid chip addr\n"); 2613 return -ENXIO; 2614 } 2615 2616 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2617 active = 0; 2618 2619 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2620 2621 if (ovly) { 2622 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2623 &chnl_prop); 2624 2625 if (status < 0) { 2626 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2627 return status; 2628 } 2629 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2630 } 2631 2632 if (!code) 2633 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2634 else 2635 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2636 2637 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2638 2639 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2640 if (status < 0) { 2641 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2642 return status; 2643 } 2644 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2645 2646 if (ovly) { 2647 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2648 &active); 2649 2650 if (status < 0) { 2651 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2652 return status; 2653 } 2654 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2655 } 2656 2657 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2658 DSPDMAC_ACTIVE_AAR_MASK; 2659 2660 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2661 if (status < 0) { 2662 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2663 return status; 2664 } 2665 2666 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2667 2668 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2669 port_map_mask); 2670 if (status < 0) { 2671 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2672 return status; 2673 } 2674 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2675 2676 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2677 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2678 if (status < 0) { 2679 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2680 return status; 2681 } 2682 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2683 2684 codec_dbg(codec, 2685 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2686 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2687 chip_addx, dsp_addx, dma_chan, 2688 port_map_mask, chnl_prop, active); 2689 2690 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2691 2692 return 0; 2693 } 2694 2695 /* 2696 * Setup the DSP DMA per-transfer-specific registers 2697 */ 2698 static int dsp_dma_setup(struct hda_codec *codec, 2699 unsigned int chip_addx, 2700 unsigned int count, 2701 unsigned int dma_chan) 2702 { 2703 int status = 0; 2704 bool code, yram; 2705 unsigned int dsp_addx; 2706 unsigned int addr_field; 2707 unsigned int incr_field; 2708 unsigned int base_cnt; 2709 unsigned int cur_cnt; 2710 unsigned int dma_cfg = 0; 2711 unsigned int adr_ofs = 0; 2712 unsigned int xfr_cnt = 0; 2713 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2714 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2715 2716 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2717 2718 if (count > max_dma_count) { 2719 codec_dbg(codec, "count too big\n"); 2720 return -EINVAL; 2721 } 2722 2723 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2724 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2725 codec_dbg(codec, "invalid chip addr\n"); 2726 return -ENXIO; 2727 } 2728 2729 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2730 2731 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2732 incr_field = 0; 2733 2734 if (!code) { 2735 addr_field <<= 1; 2736 if (yram) 2737 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2738 2739 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2740 } 2741 2742 dma_cfg = addr_field + incr_field; 2743 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2744 dma_cfg); 2745 if (status < 0) { 2746 codec_dbg(codec, "write DMACFG Reg fail\n"); 2747 return status; 2748 } 2749 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2750 2751 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2752 (code ? 0 : 1)); 2753 2754 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2755 adr_ofs); 2756 if (status < 0) { 2757 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2758 return status; 2759 } 2760 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2761 2762 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2763 2764 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2765 2766 xfr_cnt = base_cnt | cur_cnt; 2767 2768 status = chipio_write(codec, 2769 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2770 if (status < 0) { 2771 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2772 return status; 2773 } 2774 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2775 2776 codec_dbg(codec, 2777 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2778 "ADROFS=0x%x, XFRCNT=0x%x\n", 2779 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2780 2781 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2782 2783 return 0; 2784 } 2785 2786 /* 2787 * Start the DSP DMA 2788 */ 2789 static int dsp_dma_start(struct hda_codec *codec, 2790 unsigned int dma_chan, bool ovly) 2791 { 2792 unsigned int reg = 0; 2793 int status = 0; 2794 2795 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2796 2797 if (ovly) { 2798 status = chipio_read(codec, 2799 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2800 2801 if (status < 0) { 2802 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2803 return status; 2804 } 2805 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2806 2807 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2808 DSPDMAC_CHNLSTART_DIS_MASK); 2809 } 2810 2811 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2812 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2813 if (status < 0) { 2814 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2815 return status; 2816 } 2817 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2818 2819 return status; 2820 } 2821 2822 /* 2823 * Stop the DSP DMA 2824 */ 2825 static int dsp_dma_stop(struct hda_codec *codec, 2826 unsigned int dma_chan, bool ovly) 2827 { 2828 unsigned int reg = 0; 2829 int status = 0; 2830 2831 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2832 2833 if (ovly) { 2834 status = chipio_read(codec, 2835 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2836 2837 if (status < 0) { 2838 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2839 return status; 2840 } 2841 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2842 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2843 DSPDMAC_CHNLSTART_DIS_MASK); 2844 } 2845 2846 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2847 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2848 if (status < 0) { 2849 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2850 return status; 2851 } 2852 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2853 2854 return status; 2855 } 2856 2857 /** 2858 * dsp_allocate_router_ports - Allocate router ports 2859 * 2860 * @codec: the HDA codec 2861 * @num_chans: number of channels in the stream 2862 * @ports_per_channel: number of ports per channel 2863 * @start_device: start device 2864 * @port_map: pointer to the port list to hold the allocated ports 2865 * 2866 * Returns zero or a negative error code. 2867 */ 2868 static int dsp_allocate_router_ports(struct hda_codec *codec, 2869 unsigned int num_chans, 2870 unsigned int ports_per_channel, 2871 unsigned int start_device, 2872 unsigned int *port_map) 2873 { 2874 int status = 0; 2875 int res; 2876 u8 val; 2877 2878 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2879 if (status < 0) 2880 return status; 2881 2882 val = start_device << 6; 2883 val |= (ports_per_channel - 1) << 4; 2884 val |= num_chans - 1; 2885 2886 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2887 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2888 val); 2889 2890 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2891 VENDOR_CHIPIO_PORT_ALLOC_SET, 2892 MEM_CONNID_DSP); 2893 2894 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2895 if (status < 0) 2896 return status; 2897 2898 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2899 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2900 2901 *port_map = res; 2902 2903 return (res < 0) ? res : 0; 2904 } 2905 2906 /* 2907 * Free router ports 2908 */ 2909 static int dsp_free_router_ports(struct hda_codec *codec) 2910 { 2911 int status = 0; 2912 2913 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2914 if (status < 0) 2915 return status; 2916 2917 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2918 VENDOR_CHIPIO_PORT_FREE_SET, 2919 MEM_CONNID_DSP); 2920 2921 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2922 2923 return status; 2924 } 2925 2926 /* 2927 * Allocate DSP ports for the download stream 2928 */ 2929 static int dsp_allocate_ports(struct hda_codec *codec, 2930 unsigned int num_chans, 2931 unsigned int rate_multi, unsigned int *port_map) 2932 { 2933 int status; 2934 2935 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2936 2937 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2938 codec_dbg(codec, "bad rate multiple\n"); 2939 return -EINVAL; 2940 } 2941 2942 status = dsp_allocate_router_ports(codec, num_chans, 2943 rate_multi, 0, port_map); 2944 2945 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2946 2947 return status; 2948 } 2949 2950 static int dsp_allocate_ports_format(struct hda_codec *codec, 2951 const unsigned short fmt, 2952 unsigned int *port_map) 2953 { 2954 unsigned int num_chans; 2955 2956 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2957 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2958 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2959 2960 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2961 codec_dbg(codec, "bad rate multiple\n"); 2962 return -EINVAL; 2963 } 2964 2965 num_chans = get_hdafmt_chs(fmt) + 1; 2966 2967 return dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2968 } 2969 2970 /* 2971 * free DSP ports 2972 */ 2973 static int dsp_free_ports(struct hda_codec *codec) 2974 { 2975 int status; 2976 2977 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 2978 2979 status = dsp_free_router_ports(codec); 2980 if (status < 0) { 2981 codec_dbg(codec, "free router ports fail\n"); 2982 return status; 2983 } 2984 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 2985 2986 return status; 2987 } 2988 2989 /* 2990 * HDA DMA engine stuffs for DSP code download 2991 */ 2992 struct dma_engine { 2993 struct hda_codec *codec; 2994 unsigned short m_converter_format; 2995 struct snd_dma_buffer *dmab; 2996 unsigned int buf_size; 2997 }; 2998 2999 3000 enum dma_state { 3001 DMA_STATE_STOP = 0, 3002 DMA_STATE_RUN = 1 3003 }; 3004 3005 static int dma_convert_to_hda_format(struct hda_codec *codec, 3006 unsigned int sample_rate, 3007 unsigned short channels, 3008 unsigned short *hda_format) 3009 { 3010 unsigned int format_val; 3011 3012 format_val = snd_hdac_stream_format(channels, 32, sample_rate); 3013 3014 if (hda_format) 3015 *hda_format = (unsigned short)format_val; 3016 3017 return 0; 3018 } 3019 3020 /* 3021 * Reset DMA for DSP download 3022 */ 3023 static int dma_reset(struct dma_engine *dma) 3024 { 3025 struct hda_codec *codec = dma->codec; 3026 struct ca0132_spec *spec = codec->spec; 3027 int status; 3028 3029 if (dma->dmab->area) 3030 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 3031 3032 status = snd_hda_codec_load_dsp_prepare(codec, 3033 dma->m_converter_format, 3034 dma->buf_size, 3035 dma->dmab); 3036 if (status < 0) 3037 return status; 3038 spec->dsp_stream_id = status; 3039 return 0; 3040 } 3041 3042 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 3043 { 3044 bool cmd; 3045 3046 switch (state) { 3047 case DMA_STATE_STOP: 3048 cmd = false; 3049 break; 3050 case DMA_STATE_RUN: 3051 cmd = true; 3052 break; 3053 default: 3054 return 0; 3055 } 3056 3057 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 3058 return 0; 3059 } 3060 3061 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 3062 { 3063 return dma->dmab->bytes; 3064 } 3065 3066 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 3067 { 3068 return dma->dmab->area; 3069 } 3070 3071 static int dma_xfer(struct dma_engine *dma, 3072 const unsigned int *data, 3073 unsigned int count) 3074 { 3075 memcpy(dma->dmab->area, data, count); 3076 return 0; 3077 } 3078 3079 static void dma_get_converter_format( 3080 struct dma_engine *dma, 3081 unsigned short *format) 3082 { 3083 if (format) 3084 *format = dma->m_converter_format; 3085 } 3086 3087 static unsigned int dma_get_stream_id(struct dma_engine *dma) 3088 { 3089 struct ca0132_spec *spec = dma->codec->spec; 3090 3091 return spec->dsp_stream_id; 3092 } 3093 3094 struct dsp_image_seg { 3095 u32 magic; 3096 u32 chip_addr; 3097 u32 count; 3098 u32 data[]; 3099 }; 3100 3101 static const u32 g_magic_value = 0x4c46584d; 3102 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 3103 3104 static bool is_valid(const struct dsp_image_seg *p) 3105 { 3106 return p->magic == g_magic_value; 3107 } 3108 3109 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 3110 { 3111 return g_chip_addr_magic_value == p->chip_addr; 3112 } 3113 3114 static bool is_last(const struct dsp_image_seg *p) 3115 { 3116 return p->count == 0; 3117 } 3118 3119 static size_t dsp_sizeof(const struct dsp_image_seg *p) 3120 { 3121 return struct_size(p, data, p->count); 3122 } 3123 3124 static const struct dsp_image_seg *get_next_seg_ptr( 3125 const struct dsp_image_seg *p) 3126 { 3127 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 3128 } 3129 3130 /* 3131 * CA0132 chip DSP transfer stuffs. For DSP download. 3132 */ 3133 #define INVALID_DMA_CHANNEL (~0U) 3134 3135 /* 3136 * Program a list of address/data pairs via the ChipIO widget. 3137 * The segment data is in the format of successive pairs of words. 3138 * These are repeated as indicated by the segment's count field. 3139 */ 3140 static int dspxfr_hci_write(struct hda_codec *codec, 3141 const struct dsp_image_seg *fls) 3142 { 3143 int status; 3144 const u32 *data; 3145 unsigned int count; 3146 3147 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 3148 codec_dbg(codec, "hci_write invalid params\n"); 3149 return -EINVAL; 3150 } 3151 3152 count = fls->count; 3153 data = (u32 *)(fls->data); 3154 while (count >= 2) { 3155 status = chipio_write(codec, data[0], data[1]); 3156 if (status < 0) { 3157 codec_dbg(codec, "hci_write chipio failed\n"); 3158 return status; 3159 } 3160 count -= 2; 3161 data += 2; 3162 } 3163 return 0; 3164 } 3165 3166 /** 3167 * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine. 3168 * 3169 * @codec: the HDA codec 3170 * @fls: pointer to a fast load image 3171 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3172 * no relocation 3173 * @dma_engine: pointer to DMA engine to be used for DSP download 3174 * @dma_chan: The number of DMA channels used for DSP download 3175 * @port_map_mask: port mapping 3176 * @ovly: TRUE if overlay format is required 3177 * 3178 * Returns zero or a negative error code. 3179 */ 3180 static int dspxfr_one_seg(struct hda_codec *codec, 3181 const struct dsp_image_seg *fls, 3182 unsigned int reloc, 3183 struct dma_engine *dma_engine, 3184 unsigned int dma_chan, 3185 unsigned int port_map_mask, 3186 bool ovly) 3187 { 3188 int status = 0; 3189 bool comm_dma_setup_done = false; 3190 const unsigned int *data; 3191 unsigned int chip_addx; 3192 unsigned int words_to_write; 3193 unsigned int buffer_size_words; 3194 unsigned char *buffer_addx; 3195 unsigned short hda_format; 3196 unsigned int sample_rate_div; 3197 unsigned int sample_rate_mul; 3198 unsigned int num_chans; 3199 unsigned int hda_frame_size_words; 3200 unsigned int remainder_words; 3201 const u32 *data_remainder; 3202 u32 chip_addx_remainder; 3203 unsigned int run_size_words; 3204 const struct dsp_image_seg *hci_write = NULL; 3205 unsigned long timeout; 3206 bool dma_active; 3207 3208 if (fls == NULL) 3209 return -EINVAL; 3210 if (is_hci_prog_list_seg(fls)) { 3211 hci_write = fls; 3212 fls = get_next_seg_ptr(fls); 3213 } 3214 3215 if (hci_write && (!fls || is_last(fls))) { 3216 codec_dbg(codec, "hci_write\n"); 3217 return dspxfr_hci_write(codec, hci_write); 3218 } 3219 3220 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 3221 codec_dbg(codec, "Invalid Params\n"); 3222 return -EINVAL; 3223 } 3224 3225 data = fls->data; 3226 chip_addx = fls->chip_addr; 3227 words_to_write = fls->count; 3228 3229 if (!words_to_write) 3230 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 3231 if (reloc) 3232 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 3233 3234 if (!UC_RANGE(chip_addx, words_to_write) && 3235 !X_RANGE_ALL(chip_addx, words_to_write) && 3236 !Y_RANGE_ALL(chip_addx, words_to_write)) { 3237 codec_dbg(codec, "Invalid chip_addx Params\n"); 3238 return -EINVAL; 3239 } 3240 3241 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 3242 sizeof(u32); 3243 3244 buffer_addx = dma_get_buffer_addr(dma_engine); 3245 3246 if (buffer_addx == NULL) { 3247 codec_dbg(codec, "dma_engine buffer NULL\n"); 3248 return -EINVAL; 3249 } 3250 3251 dma_get_converter_format(dma_engine, &hda_format); 3252 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 3253 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 3254 num_chans = get_hdafmt_chs(hda_format) + 1; 3255 3256 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 3257 (num_chans * sample_rate_mul / sample_rate_div)); 3258 3259 if (hda_frame_size_words == 0) { 3260 codec_dbg(codec, "frmsz zero\n"); 3261 return -EINVAL; 3262 } 3263 3264 buffer_size_words = min(buffer_size_words, 3265 (unsigned int)(UC_RANGE(chip_addx, 1) ? 3266 65536 : 32768)); 3267 buffer_size_words -= buffer_size_words % hda_frame_size_words; 3268 codec_dbg(codec, 3269 "chpadr=0x%08x frmsz=%u nchan=%u " 3270 "rate_mul=%u div=%u bufsz=%u\n", 3271 chip_addx, hda_frame_size_words, num_chans, 3272 sample_rate_mul, sample_rate_div, buffer_size_words); 3273 3274 if (buffer_size_words < hda_frame_size_words) { 3275 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 3276 return -EINVAL; 3277 } 3278 3279 remainder_words = words_to_write % hda_frame_size_words; 3280 data_remainder = data; 3281 chip_addx_remainder = chip_addx; 3282 3283 data += remainder_words; 3284 chip_addx += remainder_words*sizeof(u32); 3285 words_to_write -= remainder_words; 3286 3287 while (words_to_write != 0) { 3288 run_size_words = min(buffer_size_words, words_to_write); 3289 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 3290 words_to_write, run_size_words, remainder_words); 3291 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 3292 if (!comm_dma_setup_done) { 3293 status = dsp_dma_stop(codec, dma_chan, ovly); 3294 if (status < 0) 3295 return status; 3296 status = dsp_dma_setup_common(codec, chip_addx, 3297 dma_chan, port_map_mask, ovly); 3298 if (status < 0) 3299 return status; 3300 comm_dma_setup_done = true; 3301 } 3302 3303 status = dsp_dma_setup(codec, chip_addx, 3304 run_size_words, dma_chan); 3305 if (status < 0) 3306 return status; 3307 status = dsp_dma_start(codec, dma_chan, ovly); 3308 if (status < 0) 3309 return status; 3310 if (!dsp_is_dma_active(codec, dma_chan)) { 3311 codec_dbg(codec, "dspxfr:DMA did not start\n"); 3312 return -EIO; 3313 } 3314 status = dma_set_state(dma_engine, DMA_STATE_RUN); 3315 if (status < 0) 3316 return status; 3317 if (remainder_words != 0) { 3318 status = chipio_write_multiple(codec, 3319 chip_addx_remainder, 3320 data_remainder, 3321 remainder_words); 3322 if (status < 0) 3323 return status; 3324 remainder_words = 0; 3325 } 3326 if (hci_write) { 3327 status = dspxfr_hci_write(codec, hci_write); 3328 if (status < 0) 3329 return status; 3330 hci_write = NULL; 3331 } 3332 3333 timeout = jiffies + msecs_to_jiffies(2000); 3334 do { 3335 dma_active = dsp_is_dma_active(codec, dma_chan); 3336 if (!dma_active) 3337 break; 3338 msleep(20); 3339 } while (time_before(jiffies, timeout)); 3340 if (dma_active) 3341 break; 3342 3343 codec_dbg(codec, "+++++ DMA complete\n"); 3344 dma_set_state(dma_engine, DMA_STATE_STOP); 3345 status = dma_reset(dma_engine); 3346 3347 if (status < 0) 3348 return status; 3349 3350 data += run_size_words; 3351 chip_addx += run_size_words*sizeof(u32); 3352 words_to_write -= run_size_words; 3353 } 3354 3355 if (remainder_words != 0) { 3356 status = chipio_write_multiple(codec, chip_addx_remainder, 3357 data_remainder, remainder_words); 3358 } 3359 3360 return status; 3361 } 3362 3363 /** 3364 * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories 3365 * 3366 * @codec: the HDA codec 3367 * @fls_data: pointer to a fast load image 3368 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3369 * no relocation 3370 * @sample_rate: sampling rate of the stream used for DSP download 3371 * @channels: channels of the stream used for DSP download 3372 * @ovly: TRUE if overlay format is required 3373 * 3374 * Returns zero or a negative error code. 3375 */ 3376 static int dspxfr_image(struct hda_codec *codec, 3377 const struct dsp_image_seg *fls_data, 3378 unsigned int reloc, 3379 unsigned int sample_rate, 3380 unsigned short channels, 3381 bool ovly) 3382 { 3383 struct ca0132_spec *spec = codec->spec; 3384 int status; 3385 unsigned short hda_format = 0; 3386 unsigned int response; 3387 unsigned char stream_id = 0; 3388 struct dma_engine *dma_engine; 3389 unsigned int dma_chan; 3390 unsigned int port_map_mask; 3391 3392 if (fls_data == NULL) 3393 return -EINVAL; 3394 3395 dma_engine = kzalloc_obj(*dma_engine); 3396 if (!dma_engine) 3397 return -ENOMEM; 3398 3399 dma_engine->dmab = kzalloc_obj(*dma_engine->dmab); 3400 if (!dma_engine->dmab) { 3401 kfree(dma_engine); 3402 return -ENOMEM; 3403 } 3404 3405 dma_engine->codec = codec; 3406 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3407 dma_engine->m_converter_format = hda_format; 3408 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3409 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3410 3411 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3412 3413 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3414 hda_format, &response); 3415 3416 if (status < 0) { 3417 codec_dbg(codec, "set converter format fail\n"); 3418 goto exit; 3419 } 3420 3421 status = snd_hda_codec_load_dsp_prepare(codec, 3422 dma_engine->m_converter_format, 3423 dma_engine->buf_size, 3424 dma_engine->dmab); 3425 if (status < 0) 3426 goto exit; 3427 spec->dsp_stream_id = status; 3428 3429 if (ovly) { 3430 status = dspio_alloc_dma_chan(codec, &dma_chan); 3431 if (status < 0) { 3432 codec_dbg(codec, "alloc dmachan fail\n"); 3433 dma_chan = INVALID_DMA_CHANNEL; 3434 goto exit; 3435 } 3436 } 3437 3438 port_map_mask = 0; 3439 status = dsp_allocate_ports_format(codec, hda_format, 3440 &port_map_mask); 3441 if (status < 0) { 3442 codec_dbg(codec, "alloc ports fail\n"); 3443 goto exit; 3444 } 3445 3446 stream_id = dma_get_stream_id(dma_engine); 3447 status = codec_set_converter_stream_channel(codec, 3448 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3449 if (status < 0) { 3450 codec_dbg(codec, "set stream chan fail\n"); 3451 goto exit; 3452 } 3453 3454 while ((fls_data != NULL) && !is_last(fls_data)) { 3455 if (!is_valid(fls_data)) { 3456 codec_dbg(codec, "FLS check fail\n"); 3457 status = -EINVAL; 3458 goto exit; 3459 } 3460 status = dspxfr_one_seg(codec, fls_data, reloc, 3461 dma_engine, dma_chan, 3462 port_map_mask, ovly); 3463 if (status < 0) 3464 break; 3465 3466 if (is_hci_prog_list_seg(fls_data)) 3467 fls_data = get_next_seg_ptr(fls_data); 3468 3469 if ((fls_data != NULL) && !is_last(fls_data)) 3470 fls_data = get_next_seg_ptr(fls_data); 3471 } 3472 3473 if (port_map_mask != 0) 3474 status = dsp_free_ports(codec); 3475 3476 if (status < 0) 3477 goto exit; 3478 3479 status = codec_set_converter_stream_channel(codec, 3480 WIDGET_CHIP_CTRL, 0, 0, &response); 3481 3482 exit: 3483 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3484 dspio_free_dma_chan(codec, dma_chan); 3485 3486 if (dma_engine->dmab->area) 3487 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3488 kfree(dma_engine->dmab); 3489 kfree(dma_engine); 3490 3491 return status; 3492 } 3493 3494 /* 3495 * CA0132 DSP download stuffs. 3496 */ 3497 static void dspload_post_setup(struct hda_codec *codec) 3498 { 3499 struct ca0132_spec *spec = codec->spec; 3500 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3501 if (!ca0132_use_alt_functions(spec)) { 3502 /*set DSP speaker to 2.0 configuration*/ 3503 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3504 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3505 3506 /*update write pointer*/ 3507 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3508 } 3509 } 3510 3511 /** 3512 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3513 * 3514 * @codec: the HDA codec 3515 * @fls: pointer to a fast load image 3516 * @ovly: TRUE if overlay format is required 3517 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3518 * no relocation 3519 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3520 * @router_chans: number of audio router channels to be allocated (0 means use 3521 * internal defaults; max is 32) 3522 * 3523 * Download DSP from a DSP Image Fast Load structure. This structure is a 3524 * linear, non-constant sized element array of structures, each of which 3525 * contain the count of the data to be loaded, the data itself, and the 3526 * corresponding starting chip address of the starting data location. 3527 * Returns zero or a negative error code. 3528 */ 3529 static int dspload_image(struct hda_codec *codec, 3530 const struct dsp_image_seg *fls, 3531 bool ovly, 3532 unsigned int reloc, 3533 bool autostart, 3534 int router_chans) 3535 { 3536 int status = 0; 3537 unsigned int sample_rate; 3538 unsigned short channels; 3539 3540 codec_dbg(codec, "---- dspload_image begin ------\n"); 3541 if (router_chans == 0) { 3542 if (!ovly) 3543 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3544 else 3545 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3546 } 3547 3548 sample_rate = 48000; 3549 channels = (unsigned short)router_chans; 3550 3551 while (channels > 16) { 3552 sample_rate *= 2; 3553 channels /= 2; 3554 } 3555 3556 do { 3557 codec_dbg(codec, "Ready to program DMA\n"); 3558 if (!ovly) 3559 status = dsp_reset(codec); 3560 3561 if (status < 0) 3562 break; 3563 3564 codec_dbg(codec, "dsp_reset() complete\n"); 3565 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3566 ovly); 3567 3568 if (status < 0) 3569 break; 3570 3571 codec_dbg(codec, "dspxfr_image() complete\n"); 3572 if (autostart && !ovly) { 3573 dspload_post_setup(codec); 3574 status = dsp_set_run_state(codec); 3575 } 3576 3577 codec_dbg(codec, "LOAD FINISHED\n"); 3578 } while (0); 3579 3580 return status; 3581 } 3582 3583 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3584 static bool dspload_is_loaded(struct hda_codec *codec) 3585 { 3586 unsigned int data = 0; 3587 int status = 0; 3588 3589 status = chipio_read(codec, 0x40004, &data); 3590 if ((status < 0) || (data != 1)) 3591 return false; 3592 3593 return true; 3594 } 3595 #else 3596 #define dspload_is_loaded(codec) false 3597 #endif 3598 3599 static bool dspload_wait_loaded(struct hda_codec *codec) 3600 { 3601 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3602 3603 do { 3604 if (dspload_is_loaded(codec)) { 3605 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3606 return true; 3607 } 3608 msleep(20); 3609 } while (time_before(jiffies, timeout)); 3610 3611 codec_err(codec, "ca0132 failed to download DSP\n"); 3612 return false; 3613 } 3614 3615 /* 3616 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3617 * based cards, and has a second mmio region, region2, that's used for special 3618 * commands. 3619 */ 3620 3621 /* 3622 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3623 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3624 * The first eight bits are just the number of the pin. So far, I've only seen 3625 * this number go to 7. 3626 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3627 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3628 * then off to send that bit. 3629 */ 3630 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3631 bool enable) 3632 { 3633 struct ca0132_spec *spec = codec->spec; 3634 unsigned short gpio_data; 3635 3636 gpio_data = gpio_pin & 0xF; 3637 gpio_data |= ((enable << 8) & 0x100); 3638 3639 writew(gpio_data, spec->mem_base + 0x320); 3640 } 3641 3642 /* 3643 * Special pci region2 commands that are only used by the AE-5. They follow 3644 * a set format, and require reads at certain points to seemingly 'clear' 3645 * the response data. My first tests didn't do these reads, and would cause 3646 * the card to get locked up until the memory was read. These commands 3647 * seem to work with three distinct values that I've taken to calling group, 3648 * target-id, and value. 3649 */ 3650 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3651 unsigned int target, unsigned int value) 3652 { 3653 struct ca0132_spec *spec = codec->spec; 3654 unsigned int write_val; 3655 3656 writel(0x0000007e, spec->mem_base + 0x210); 3657 readl(spec->mem_base + 0x210); 3658 writel(0x0000005a, spec->mem_base + 0x210); 3659 readl(spec->mem_base + 0x210); 3660 readl(spec->mem_base + 0x210); 3661 3662 writel(0x00800005, spec->mem_base + 0x20c); 3663 writel(group, spec->mem_base + 0x804); 3664 3665 writel(0x00800005, spec->mem_base + 0x20c); 3666 write_val = (target & 0xff); 3667 write_val |= (value << 8); 3668 3669 3670 writel(write_val, spec->mem_base + 0x204); 3671 /* 3672 * Need delay here or else it goes too fast and works inconsistently. 3673 */ 3674 msleep(20); 3675 3676 readl(spec->mem_base + 0x860); 3677 readl(spec->mem_base + 0x854); 3678 readl(spec->mem_base + 0x840); 3679 3680 writel(0x00800004, spec->mem_base + 0x20c); 3681 writel(0x00000000, spec->mem_base + 0x210); 3682 readl(spec->mem_base + 0x210); 3683 readl(spec->mem_base + 0x210); 3684 } 3685 3686 /* 3687 * This second type of command is used for setting the sound filter type. 3688 */ 3689 static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3690 unsigned int group, unsigned int target, unsigned int value) 3691 { 3692 struct ca0132_spec *spec = codec->spec; 3693 unsigned int write_val; 3694 3695 writel(0x0000007e, spec->mem_base + 0x210); 3696 readl(spec->mem_base + 0x210); 3697 writel(0x0000005a, spec->mem_base + 0x210); 3698 readl(spec->mem_base + 0x210); 3699 readl(spec->mem_base + 0x210); 3700 3701 writel(0x00800003, spec->mem_base + 0x20c); 3702 writel(group, spec->mem_base + 0x804); 3703 3704 writel(0x00800005, spec->mem_base + 0x20c); 3705 write_val = (target & 0xff); 3706 write_val |= (value << 8); 3707 3708 3709 writel(write_val, spec->mem_base + 0x204); 3710 msleep(20); 3711 readl(spec->mem_base + 0x860); 3712 readl(spec->mem_base + 0x854); 3713 readl(spec->mem_base + 0x840); 3714 3715 writel(0x00800004, spec->mem_base + 0x20c); 3716 writel(0x00000000, spec->mem_base + 0x210); 3717 readl(spec->mem_base + 0x210); 3718 readl(spec->mem_base + 0x210); 3719 } 3720 3721 /* 3722 * Setup GPIO for the other variants of Core3D. 3723 */ 3724 3725 /* 3726 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3727 * the card shows as having no GPIO pins. 3728 */ 3729 static void ca0132_gpio_init(struct hda_codec *codec) 3730 { 3731 struct ca0132_spec *spec = codec->spec; 3732 3733 switch (ca0132_quirk(spec)) { 3734 case QUIRK_SBZ: 3735 case QUIRK_AE5: 3736 case QUIRK_AE7: 3737 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3738 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3739 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3740 break; 3741 case QUIRK_R3DI: 3742 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3743 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3744 break; 3745 default: 3746 break; 3747 } 3748 3749 } 3750 3751 /* Sets the GPIO for audio output. */ 3752 static void ca0132_gpio_setup(struct hda_codec *codec) 3753 { 3754 struct ca0132_spec *spec = codec->spec; 3755 3756 switch (ca0132_quirk(spec)) { 3757 case QUIRK_SBZ: 3758 snd_hda_codec_set_gpio(codec, 0x07, 0x07, 0x04, 0); 3759 snd_hda_codec_write(codec, 0x01, 0, 3760 AC_VERB_SET_GPIO_DATA, 0x06); 3761 break; 3762 case QUIRK_R3DI: 3763 snd_hda_codec_set_gpio(codec, 0x1F, 0x1E, 0x0C, 0); 3764 break; 3765 default: 3766 break; 3767 } 3768 } 3769 3770 /* 3771 * GPIO control functions for the Recon3D integrated. 3772 */ 3773 3774 enum r3di_gpio_bit { 3775 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3776 R3DI_MIC_SELECT_BIT = 1, 3777 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3778 R3DI_OUT_SELECT_BIT = 2, 3779 /* 3780 * I dunno what this actually does, but it stays on until the dsp 3781 * is downloaded. 3782 */ 3783 R3DI_GPIO_DSP_DOWNLOADING = 3, 3784 /* 3785 * Same as above, no clue what it does, but it comes on after the dsp 3786 * is downloaded. 3787 */ 3788 R3DI_GPIO_DSP_DOWNLOADED = 4 3789 }; 3790 3791 enum r3di_mic_select { 3792 /* Set GPIO bit 1 to 0 for rear mic */ 3793 R3DI_REAR_MIC = 0, 3794 /* Set GPIO bit 1 to 1 for front microphone*/ 3795 R3DI_FRONT_MIC = 1 3796 }; 3797 3798 enum r3di_out_select { 3799 /* Set GPIO bit 2 to 0 for headphone */ 3800 R3DI_HEADPHONE_OUT = 0, 3801 /* Set GPIO bit 2 to 1 for speaker */ 3802 R3DI_LINE_OUT = 1 3803 }; 3804 enum r3di_dsp_status { 3805 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3806 R3DI_DSP_DOWNLOADING = 0, 3807 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3808 R3DI_DSP_DOWNLOADED = 1 3809 }; 3810 3811 3812 static void r3di_gpio_mic_set(struct hda_codec *codec, 3813 enum r3di_mic_select cur_mic) 3814 { 3815 unsigned int cur_gpio; 3816 3817 /* Get the current GPIO Data setup */ 3818 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3819 3820 switch (cur_mic) { 3821 case R3DI_REAR_MIC: 3822 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3823 break; 3824 case R3DI_FRONT_MIC: 3825 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3826 break; 3827 } 3828 snd_hda_codec_write(codec, codec->core.afg, 0, 3829 AC_VERB_SET_GPIO_DATA, cur_gpio); 3830 } 3831 3832 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3833 enum r3di_dsp_status dsp_status) 3834 { 3835 unsigned int cur_gpio; 3836 3837 /* Get the current GPIO Data setup */ 3838 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3839 3840 switch (dsp_status) { 3841 case R3DI_DSP_DOWNLOADING: 3842 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3843 snd_hda_codec_write(codec, codec->core.afg, 0, 3844 AC_VERB_SET_GPIO_DATA, cur_gpio); 3845 break; 3846 case R3DI_DSP_DOWNLOADED: 3847 /* Set DOWNLOADING bit to 0. */ 3848 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3849 3850 snd_hda_codec_write(codec, codec->core.afg, 0, 3851 AC_VERB_SET_GPIO_DATA, cur_gpio); 3852 3853 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3854 break; 3855 } 3856 3857 snd_hda_codec_write(codec, codec->core.afg, 0, 3858 AC_VERB_SET_GPIO_DATA, cur_gpio); 3859 } 3860 3861 /* 3862 * PCM callbacks 3863 */ 3864 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3865 struct hda_codec *codec, 3866 unsigned int stream_tag, 3867 unsigned int format, 3868 struct snd_pcm_substream *substream) 3869 { 3870 struct ca0132_spec *spec = codec->spec; 3871 3872 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3873 3874 return 0; 3875 } 3876 3877 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3878 struct hda_codec *codec, 3879 struct snd_pcm_substream *substream) 3880 { 3881 struct ca0132_spec *spec = codec->spec; 3882 3883 if (spec->dsp_state == DSP_DOWNLOADING) 3884 return 0; 3885 3886 /*If Playback effects are on, allow stream some time to flush 3887 *effects tail*/ 3888 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3889 msleep(50); 3890 3891 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3892 3893 return 0; 3894 } 3895 3896 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3897 struct hda_codec *codec, 3898 struct snd_pcm_substream *substream) 3899 { 3900 struct ca0132_spec *spec = codec->spec; 3901 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3902 struct snd_pcm_runtime *runtime = substream->runtime; 3903 3904 if (spec->dsp_state != DSP_DOWNLOADED) 3905 return 0; 3906 3907 /* Add latency if playback enhancement and either effect is enabled. */ 3908 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3909 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3910 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3911 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3912 } 3913 3914 /* Applying Speaker EQ adds latency as well. */ 3915 if (spec->cur_out_type == SPEAKER_OUT) 3916 latency += DSP_SPEAKER_OUT_LATENCY; 3917 3918 return (latency * runtime->rate) / 1000; 3919 } 3920 3921 /* 3922 * Digital out 3923 */ 3924 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3925 struct hda_codec *codec, 3926 struct snd_pcm_substream *substream) 3927 { 3928 struct ca0132_spec *spec = codec->spec; 3929 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3930 } 3931 3932 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3933 struct hda_codec *codec, 3934 unsigned int stream_tag, 3935 unsigned int format, 3936 struct snd_pcm_substream *substream) 3937 { 3938 struct ca0132_spec *spec = codec->spec; 3939 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3940 stream_tag, format, substream); 3941 } 3942 3943 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3944 struct hda_codec *codec, 3945 struct snd_pcm_substream *substream) 3946 { 3947 struct ca0132_spec *spec = codec->spec; 3948 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3949 } 3950 3951 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3952 struct hda_codec *codec, 3953 struct snd_pcm_substream *substream) 3954 { 3955 struct ca0132_spec *spec = codec->spec; 3956 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3957 } 3958 3959 /* 3960 * Analog capture 3961 */ 3962 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3963 struct hda_codec *codec, 3964 unsigned int stream_tag, 3965 unsigned int format, 3966 struct snd_pcm_substream *substream) 3967 { 3968 snd_hda_codec_setup_stream(codec, hinfo->nid, 3969 stream_tag, 0, format); 3970 3971 return 0; 3972 } 3973 3974 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 3975 struct hda_codec *codec, 3976 struct snd_pcm_substream *substream) 3977 { 3978 struct ca0132_spec *spec = codec->spec; 3979 3980 if (spec->dsp_state == DSP_DOWNLOADING) 3981 return 0; 3982 3983 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 3984 return 0; 3985 } 3986 3987 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 3988 struct hda_codec *codec, 3989 struct snd_pcm_substream *substream) 3990 { 3991 struct ca0132_spec *spec = codec->spec; 3992 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 3993 struct snd_pcm_runtime *runtime = substream->runtime; 3994 3995 if (spec->dsp_state != DSP_DOWNLOADED) 3996 return 0; 3997 3998 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 3999 latency += DSP_CRYSTAL_VOICE_LATENCY; 4000 4001 return (latency * runtime->rate) / 1000; 4002 } 4003 4004 /* 4005 * Controls stuffs. 4006 */ 4007 4008 /* 4009 * Mixer controls helpers. 4010 */ 4011 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4012 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4013 .name = xname, \ 4014 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4015 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4016 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4017 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4018 .info = ca0132_volume_info, \ 4019 .get = ca0132_volume_get, \ 4020 .put = ca0132_volume_put, \ 4021 .tlv = { .c = ca0132_volume_tlv }, \ 4022 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4023 4024 /* 4025 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 4026 * volume put, which is used for setting the DSP volume. This was done because 4027 * the ca0132 functions were taking too much time and causing lag. 4028 */ 4029 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 4030 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4031 .name = xname, \ 4032 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4033 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 4034 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 4035 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 4036 .info = snd_hda_mixer_amp_volume_info, \ 4037 .get = snd_hda_mixer_amp_volume_get, \ 4038 .put = ca0132_alt_volume_put, \ 4039 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 4040 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4041 4042 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 4043 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4044 .name = xname, \ 4045 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 4046 .info = snd_hda_mixer_amp_switch_info, \ 4047 .get = ca0132_switch_get, \ 4048 .put = ca0132_switch_put, \ 4049 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 4050 4051 /* stereo */ 4052 #define CA0132_CODEC_VOL(xname, nid, dir) \ 4053 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 4054 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 4055 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 4056 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 4057 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 4058 4059 /* lookup tables */ 4060 /* 4061 * Lookup table with decibel values for the DSP. When volume is changed in 4062 * Windows, the DSP is also sent the dB value in floating point. In Windows, 4063 * these values have decimal points, probably because the Windows driver 4064 * actually uses floating point. We can't here, so I made a lookup table of 4065 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 4066 * DAC's, and 9 is the maximum. 4067 */ 4068 static const unsigned int float_vol_db_lookup[] = { 4069 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 4070 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 4071 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 4072 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 4073 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 4074 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 4075 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 4076 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 4077 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 4078 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 4079 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 4080 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4081 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4082 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4083 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4084 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4085 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 4086 }; 4087 4088 /* 4089 * This table counts from float 0 to 1 in increments of .01, which is 4090 * useful for a few different sliders. 4091 */ 4092 static const unsigned int float_zero_to_one_lookup[] = { 4093 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4094 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4095 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4096 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4097 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4098 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4099 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4100 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4101 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4102 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4103 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4104 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4105 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4106 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4107 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4108 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4109 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4110 }; 4111 4112 /* 4113 * This table counts from float 10 to 1000, which is the range of the x-bass 4114 * crossover slider in Windows. 4115 */ 4116 static const unsigned int float_xbass_xover_lookup[] = { 4117 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 4118 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 4119 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 4120 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 4121 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 4122 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 4123 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 4124 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 4125 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 4126 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 4127 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 4128 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 4129 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 4130 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 4131 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 4132 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 4133 0x44728000, 0x44750000, 0x44778000, 0x447A0000 4134 }; 4135 4136 /* The following are for tuning of products */ 4137 #ifdef ENABLE_TUNING_CONTROLS 4138 4139 static const unsigned int voice_focus_vals_lookup[] = { 4140 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 4141 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 4142 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 4143 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 4144 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 4145 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 4146 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 4147 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 4148 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 4149 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 4150 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 4151 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 4152 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 4153 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 4154 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 4155 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 4156 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 4157 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 4158 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 4159 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 4160 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 4161 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 4162 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 4163 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 4164 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 4165 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 4166 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 4167 }; 4168 4169 static const unsigned int mic_svm_vals_lookup[] = { 4170 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 4171 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 4172 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 4173 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 4174 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 4175 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 4176 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 4177 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 4178 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 4179 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 4180 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 4181 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 4182 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 4183 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 4184 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 4185 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 4186 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 4187 }; 4188 4189 static const unsigned int equalizer_vals_lookup[] = { 4190 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 4191 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 4192 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 4193 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 4194 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 4195 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 4196 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 4197 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 4198 0x41C00000 4199 }; 4200 4201 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 4202 const unsigned int *lookup, int idx) 4203 { 4204 int i; 4205 4206 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4207 if (nid == ca0132_tuning_ctls[i].nid) { 4208 CLASS(snd_hda_power, pm)(codec); 4209 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 4210 ca0132_tuning_ctls[i].req, 4211 &(lookup[idx]), sizeof(unsigned int)); 4212 return 1; 4213 } 4214 } 4215 4216 return -EINVAL; 4217 } 4218 4219 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 4220 struct snd_ctl_elem_value *ucontrol) 4221 { 4222 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4223 struct ca0132_spec *spec = codec->spec; 4224 hda_nid_t nid = get_amp_nid(kcontrol); 4225 long *valp = ucontrol->value.integer.value; 4226 int idx = nid - TUNING_CTL_START_NID; 4227 4228 *valp = spec->cur_ctl_vals[idx]; 4229 return 0; 4230 } 4231 4232 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 4233 struct snd_ctl_elem_info *uinfo) 4234 { 4235 int chs = get_amp_channels(kcontrol); 4236 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4237 uinfo->count = chs == 3 ? 2 : 1; 4238 uinfo->value.integer.min = 20; 4239 uinfo->value.integer.max = 180; 4240 uinfo->value.integer.step = 1; 4241 4242 return 0; 4243 } 4244 4245 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 4246 struct snd_ctl_elem_value *ucontrol) 4247 { 4248 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4249 struct ca0132_spec *spec = codec->spec; 4250 hda_nid_t nid = get_amp_nid(kcontrol); 4251 long *valp = ucontrol->value.integer.value; 4252 int idx; 4253 4254 idx = nid - TUNING_CTL_START_NID; 4255 /* any change? */ 4256 if (spec->cur_ctl_vals[idx] == *valp) 4257 return 0; 4258 4259 spec->cur_ctl_vals[idx] = *valp; 4260 4261 idx = *valp - 20; 4262 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 4263 4264 return 1; 4265 } 4266 4267 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 4268 struct snd_ctl_elem_info *uinfo) 4269 { 4270 int chs = get_amp_channels(kcontrol); 4271 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4272 uinfo->count = chs == 3 ? 2 : 1; 4273 uinfo->value.integer.min = 0; 4274 uinfo->value.integer.max = 100; 4275 uinfo->value.integer.step = 1; 4276 4277 return 0; 4278 } 4279 4280 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 4281 struct snd_ctl_elem_value *ucontrol) 4282 { 4283 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4284 struct ca0132_spec *spec = codec->spec; 4285 hda_nid_t nid = get_amp_nid(kcontrol); 4286 long *valp = ucontrol->value.integer.value; 4287 int idx; 4288 4289 idx = nid - TUNING_CTL_START_NID; 4290 /* any change? */ 4291 if (spec->cur_ctl_vals[idx] == *valp) 4292 return 0; 4293 4294 spec->cur_ctl_vals[idx] = *valp; 4295 4296 idx = *valp; 4297 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 4298 4299 return 0; 4300 } 4301 4302 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 4303 struct snd_ctl_elem_info *uinfo) 4304 { 4305 int chs = get_amp_channels(kcontrol); 4306 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 4307 uinfo->count = chs == 3 ? 2 : 1; 4308 uinfo->value.integer.min = 0; 4309 uinfo->value.integer.max = 48; 4310 uinfo->value.integer.step = 1; 4311 4312 return 0; 4313 } 4314 4315 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 4316 struct snd_ctl_elem_value *ucontrol) 4317 { 4318 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 4319 struct ca0132_spec *spec = codec->spec; 4320 hda_nid_t nid = get_amp_nid(kcontrol); 4321 long *valp = ucontrol->value.integer.value; 4322 int idx; 4323 4324 idx = nid - TUNING_CTL_START_NID; 4325 /* any change? */ 4326 if (spec->cur_ctl_vals[idx] == *valp) 4327 return 0; 4328 4329 spec->cur_ctl_vals[idx] = *valp; 4330 4331 idx = *valp; 4332 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 4333 4334 return 1; 4335 } 4336 4337 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 4338 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 4339 4340 static int add_tuning_control(struct hda_codec *codec, 4341 hda_nid_t pnid, hda_nid_t nid, 4342 const char *name, int dir) 4343 { 4344 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 4345 int type = dir ? HDA_INPUT : HDA_OUTPUT; 4346 struct snd_kcontrol_new knew = 4347 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 4348 4349 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 4350 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 4351 knew.tlv.c = NULL; 4352 knew.tlv.p = NULL; 4353 switch (pnid) { 4354 case VOICE_FOCUS: 4355 knew.info = voice_focus_ctl_info; 4356 knew.get = tuning_ctl_get; 4357 knew.put = voice_focus_ctl_put; 4358 knew.tlv.p = voice_focus_db_scale; 4359 break; 4360 case MIC_SVM: 4361 knew.info = mic_svm_ctl_info; 4362 knew.get = tuning_ctl_get; 4363 knew.put = mic_svm_ctl_put; 4364 break; 4365 case EQUALIZER: 4366 knew.info = equalizer_ctl_info; 4367 knew.get = tuning_ctl_get; 4368 knew.put = equalizer_ctl_put; 4369 knew.tlv.p = eq_db_scale; 4370 break; 4371 default: 4372 return 0; 4373 } 4374 knew.private_value = 4375 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4376 snprintf(namestr, sizeof(namestr), "%s %s Volume", name, dirstr[dir]); 4377 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4378 } 4379 4380 static int add_tuning_ctls(struct hda_codec *codec) 4381 { 4382 int i; 4383 int err; 4384 4385 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4386 err = add_tuning_control(codec, 4387 ca0132_tuning_ctls[i].parent_nid, 4388 ca0132_tuning_ctls[i].nid, 4389 ca0132_tuning_ctls[i].name, 4390 ca0132_tuning_ctls[i].direct); 4391 if (err < 0) 4392 return err; 4393 } 4394 4395 return 0; 4396 } 4397 4398 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4399 { 4400 struct ca0132_spec *spec = codec->spec; 4401 int i; 4402 4403 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4404 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4405 /* SVM level defaults to 0.74. */ 4406 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4407 4408 /* EQ defaults to 0dB. */ 4409 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4410 spec->cur_ctl_vals[i] = 24; 4411 } 4412 #endif /*ENABLE_TUNING_CONTROLS*/ 4413 4414 /* 4415 * Select the active output. 4416 * If autodetect is enabled, output will be selected based on jack detection. 4417 * If jack inserted, headphone will be selected, else built-in speakers 4418 * If autodetect is disabled, output will be selected based on selection. 4419 */ 4420 static int ca0132_select_out(struct hda_codec *codec) 4421 { 4422 struct ca0132_spec *spec = codec->spec; 4423 unsigned int pin_ctl; 4424 int jack_present; 4425 int auto_jack; 4426 unsigned int tmp; 4427 int err; 4428 4429 codec_dbg(codec, "ca0132_select_out\n"); 4430 4431 CLASS(snd_hda_power_pm, pm)(codec); 4432 4433 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4434 4435 if (auto_jack) 4436 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4437 else 4438 jack_present = 4439 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4440 4441 if (jack_present) 4442 spec->cur_out_type = HEADPHONE_OUT; 4443 else 4444 spec->cur_out_type = SPEAKER_OUT; 4445 4446 if (spec->cur_out_type == SPEAKER_OUT) { 4447 codec_dbg(codec, "ca0132_select_out speaker\n"); 4448 /*speaker out config*/ 4449 tmp = FLOAT_ONE; 4450 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4451 if (err < 0) 4452 return err; 4453 /*enable speaker EQ*/ 4454 tmp = FLOAT_ONE; 4455 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4456 if (err < 0) 4457 return err; 4458 4459 /* Setup EAPD */ 4460 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4461 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4462 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4463 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4464 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4465 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4466 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4467 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4468 4469 /* disable headphone node */ 4470 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4471 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4472 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4473 pin_ctl & ~PIN_HP); 4474 /* enable speaker node */ 4475 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4476 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4477 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4478 pin_ctl | PIN_OUT); 4479 } else { 4480 codec_dbg(codec, "ca0132_select_out hp\n"); 4481 /*headphone out config*/ 4482 tmp = FLOAT_ZERO; 4483 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4484 if (err < 0) 4485 return err; 4486 /*disable speaker EQ*/ 4487 tmp = FLOAT_ZERO; 4488 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4489 if (err < 0) 4490 return err; 4491 4492 /* Setup EAPD */ 4493 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4494 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4495 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4496 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4497 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4498 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4499 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4500 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4501 4502 /* disable speaker*/ 4503 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4504 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4505 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4506 pin_ctl & ~PIN_HP); 4507 /* enable headphone*/ 4508 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4509 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4510 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4511 pin_ctl | PIN_HP); 4512 } 4513 4514 return 0; 4515 } 4516 4517 static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4518 static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4519 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4520 4521 static void ae5_mmio_select_out(struct hda_codec *codec) 4522 { 4523 struct ca0132_spec *spec = codec->spec; 4524 const struct ae_ca0113_output_set *out_cmds; 4525 unsigned int i; 4526 4527 if (ca0132_quirk(spec) == QUIRK_AE5) 4528 out_cmds = &ae5_ca0113_output_presets; 4529 else 4530 out_cmds = &ae7_ca0113_output_presets; 4531 4532 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++) 4533 ca0113_mmio_command_set(codec, out_cmds->group[i], 4534 out_cmds->target[i], 4535 out_cmds->vals[spec->cur_out_type][i]); 4536 } 4537 4538 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec) 4539 { 4540 struct ca0132_spec *spec = codec->spec; 4541 int quirk = ca0132_quirk(spec); 4542 unsigned int tmp; 4543 int err; 4544 4545 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */ 4546 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0 4547 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4548 return 0; 4549 4550 /* Set front L/R full range. Zero for full-range, one for redirection. */ 4551 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE; 4552 err = dspio_set_uint_param(codec, 0x96, 4553 SPEAKER_FULL_RANGE_FRONT_L_R, tmp); 4554 if (err < 0) 4555 return err; 4556 4557 /* When setting full-range rear, both rear and center/lfe are set. */ 4558 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE; 4559 err = dspio_set_uint_param(codec, 0x96, 4560 SPEAKER_FULL_RANGE_CENTER_LFE, tmp); 4561 if (err < 0) 4562 return err; 4563 4564 err = dspio_set_uint_param(codec, 0x96, 4565 SPEAKER_FULL_RANGE_REAR_L_R, tmp); 4566 if (err < 0) 4567 return err; 4568 4569 /* 4570 * Only the AE series cards set this value when setting full-range, 4571 * and it's always 1.0f. 4572 */ 4573 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) { 4574 err = dspio_set_uint_param(codec, 0x96, 4575 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE); 4576 if (err < 0) 4577 return err; 4578 } 4579 4580 return 0; 4581 } 4582 4583 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec, 4584 bool val) 4585 { 4586 struct ca0132_spec *spec = codec->spec; 4587 unsigned int tmp; 4588 int err; 4589 4590 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 && 4591 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0) 4592 tmp = FLOAT_ONE; 4593 else 4594 tmp = FLOAT_ZERO; 4595 4596 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp); 4597 if (err < 0) 4598 return err; 4599 4600 /* If it is enabled, make sure to set the crossover frequency. */ 4601 if (tmp) { 4602 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq]; 4603 err = dspio_set_uint_param(codec, 0x96, 4604 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp); 4605 if (err < 0) 4606 return err; 4607 } 4608 4609 return 0; 4610 } 4611 4612 /* 4613 * These are the commands needed to setup output on each of the different card 4614 * types. 4615 */ 4616 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec, 4617 const struct ca0132_alt_out_set_quirk_data **quirk_data) 4618 { 4619 struct ca0132_spec *spec = codec->spec; 4620 int quirk = ca0132_quirk(spec); 4621 unsigned int i; 4622 4623 *quirk_data = NULL; 4624 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) { 4625 if (quirk_out_set_data[i].quirk_id == quirk) { 4626 *quirk_data = &quirk_out_set_data[i]; 4627 return; 4628 } 4629 } 4630 } 4631 4632 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec) 4633 { 4634 const struct ca0132_alt_out_set_quirk_data *quirk_data; 4635 const struct ca0132_alt_out_set_info *out_info; 4636 struct ca0132_spec *spec = codec->spec; 4637 unsigned int i, gpio_data; 4638 int err; 4639 4640 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data); 4641 if (!quirk_data) 4642 return 0; 4643 4644 out_info = &quirk_data->out_set_info[spec->cur_out_type]; 4645 if (quirk_data->is_ae_series) 4646 ae5_mmio_select_out(codec); 4647 4648 if (out_info->has_hda_gpio) { 4649 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0, 4650 AC_VERB_GET_GPIO_DATA, 0); 4651 4652 if (out_info->hda_gpio_set) 4653 gpio_data |= (1 << out_info->hda_gpio_pin); 4654 else 4655 gpio_data &= ~(1 << out_info->hda_gpio_pin); 4656 4657 snd_hda_codec_write(codec, codec->core.afg, 0, 4658 AC_VERB_SET_GPIO_DATA, gpio_data); 4659 } 4660 4661 if (out_info->mmio_gpio_count) { 4662 for (i = 0; i < out_info->mmio_gpio_count; i++) { 4663 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i], 4664 out_info->mmio_gpio_set[i]); 4665 } 4666 } 4667 4668 if (out_info->scp_cmds_count) { 4669 for (i = 0; i < out_info->scp_cmds_count; i++) { 4670 err = dspio_set_uint_param(codec, 4671 out_info->scp_cmd_mid[i], 4672 out_info->scp_cmd_req[i], 4673 out_info->scp_cmd_val[i]); 4674 if (err < 0) 4675 return err; 4676 } 4677 } 4678 4679 chipio_set_control_param(codec, 0x0d, out_info->dac2port); 4680 4681 if (out_info->has_chipio_write) { 4682 chipio_write(codec, out_info->chipio_write_addr, 4683 out_info->chipio_write_data); 4684 } 4685 4686 if (quirk_data->has_headphone_gain) { 4687 if (spec->cur_out_type != HEADPHONE_OUT) { 4688 if (quirk_data->is_ae_series) 4689 ae5_headphone_gain_set(codec, 2); 4690 else 4691 zxr_headphone_gain_set(codec, 0); 4692 } else { 4693 if (quirk_data->is_ae_series) 4694 ae5_headphone_gain_set(codec, 4695 spec->ae5_headphone_gain_val); 4696 else 4697 zxr_headphone_gain_set(codec, 4698 spec->zxr_gain_set); 4699 } 4700 } 4701 4702 return 0; 4703 } 4704 4705 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid, 4706 bool out_enable, bool hp_enable) 4707 { 4708 unsigned int pin_ctl; 4709 4710 pin_ctl = snd_hda_codec_read(codec, nid, 0, 4711 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4712 4713 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP; 4714 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT; 4715 snd_hda_set_pin_ctl(codec, nid, pin_ctl); 4716 } 4717 4718 /* 4719 * This function behaves similarly to the ca0132_select_out funciton above, 4720 * except with a few differences. It adds the ability to select the current 4721 * output with an enumerated control "output source" if the auto detect 4722 * mute switch is set to off. If the auto detect mute switch is enabled, it 4723 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4724 * It also adds the ability to auto-detect the front headphone port. 4725 */ 4726 static int ca0132_alt_select_out(struct hda_codec *codec) 4727 { 4728 struct ca0132_spec *spec = codec->spec; 4729 unsigned int tmp, outfx_set; 4730 int jack_present; 4731 int auto_jack; 4732 int err; 4733 /* Default Headphone is rear headphone */ 4734 hda_nid_t headphone_nid = spec->out_pins[1]; 4735 4736 codec_dbg(codec, "%s\n", __func__); 4737 4738 CLASS(snd_hda_power_pm, pm)(codec); 4739 4740 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4741 4742 /* 4743 * If headphone rear or front is plugged in, set to headphone. 4744 * If neither is plugged in, set to rear line out. Only if 4745 * hp/speaker auto detect is enabled. 4746 */ 4747 if (auto_jack) { 4748 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4749 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4750 4751 if (jack_present) 4752 spec->cur_out_type = HEADPHONE_OUT; 4753 else 4754 spec->cur_out_type = SPEAKER_OUT; 4755 } else 4756 spec->cur_out_type = spec->out_enum_val; 4757 4758 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]; 4759 4760 /* Begin DSP output switch, mute DSP volume. */ 4761 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE); 4762 if (err < 0) 4763 return err; 4764 4765 err = ca0132_alt_select_out_quirk_set(codec); 4766 if (err < 0) 4767 return err; 4768 4769 switch (spec->cur_out_type) { 4770 case SPEAKER_OUT: 4771 codec_dbg(codec, "%s speaker\n", __func__); 4772 4773 /* Enable EAPD */ 4774 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4775 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4776 4777 /* Disable headphone node. */ 4778 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0); 4779 /* Set front L-R to output. */ 4780 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0); 4781 /* Set Center/LFE to output. */ 4782 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0); 4783 /* Set rear surround to output. */ 4784 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0); 4785 4786 /* 4787 * Without PlayEnhancement being enabled, if we've got a 2.0 4788 * setup, set it to floating point eight to disable any DSP 4789 * processing effects. 4790 */ 4791 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0) 4792 tmp = FLOAT_EIGHT; 4793 else 4794 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val; 4795 4796 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4797 if (err < 0) 4798 return err; 4799 4800 break; 4801 case HEADPHONE_OUT: 4802 codec_dbg(codec, "%s hp\n", __func__); 4803 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4804 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4805 4806 /* Disable all speaker nodes. */ 4807 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0); 4808 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0); 4809 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0); 4810 4811 /* enable headphone, either front or rear */ 4812 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4813 headphone_nid = spec->out_pins[2]; 4814 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4815 headphone_nid = spec->out_pins[1]; 4816 4817 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1); 4818 4819 if (outfx_set) 4820 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4821 else 4822 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4823 4824 if (err < 0) 4825 return err; 4826 break; 4827 } 4828 /* 4829 * If output effects are enabled, set the X-Bass effect value again to 4830 * make sure that it's properly enabled/disabled for speaker 4831 * configurations with an LFE channel. 4832 */ 4833 if (outfx_set) 4834 ca0132_effects_set(codec, X_BASS, 4835 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4836 4837 /* Set speaker EQ bypass attenuation to 0. */ 4838 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO); 4839 if (err < 0) 4840 return err; 4841 4842 /* 4843 * Although unused on all cards but the AE series, this is always set 4844 * to zero when setting the output. 4845 */ 4846 err = dspio_set_uint_param(codec, 0x96, 4847 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO); 4848 if (err < 0) 4849 return err; 4850 4851 if (spec->cur_out_type == SPEAKER_OUT) 4852 err = ca0132_alt_surround_set_bass_redirection(codec, 4853 spec->bass_redirection_val); 4854 else 4855 err = ca0132_alt_surround_set_bass_redirection(codec, 0); 4856 if (err < 0) 4857 return err; 4858 4859 /* Unmute DSP now that we're done with output selection. */ 4860 err = dspio_set_uint_param(codec, 0x96, 4861 SPEAKER_TUNING_MUTE, FLOAT_ZERO); 4862 if (err < 0) 4863 return err; 4864 4865 if (spec->cur_out_type == SPEAKER_OUT) { 4866 err = ca0132_alt_set_full_range_speaker(codec); 4867 if (err < 0) 4868 return err; 4869 } 4870 4871 return 0; 4872 } 4873 4874 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4875 { 4876 struct ca0132_spec *spec = container_of( 4877 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4878 struct hda_jack_tbl *jack; 4879 4880 if (ca0132_use_alt_functions(spec)) 4881 ca0132_alt_select_out(spec->codec); 4882 else 4883 ca0132_select_out(spec->codec); 4884 4885 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4886 if (jack) { 4887 jack->block_report = 0; 4888 snd_hda_jack_report_sync(spec->codec); 4889 } 4890 } 4891 4892 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4893 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4894 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4895 static int stop_mic1(struct hda_codec *codec); 4896 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4897 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4898 4899 /* 4900 * Select the active VIP source 4901 */ 4902 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4903 { 4904 struct ca0132_spec *spec = codec->spec; 4905 unsigned int tmp; 4906 4907 if (spec->dsp_state != DSP_DOWNLOADED) 4908 return 0; 4909 4910 /* if CrystalVoice if off, vipsource should be 0 */ 4911 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4912 (val == 0)) { 4913 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4914 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4915 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4916 if (spec->cur_mic_type == DIGITAL_MIC) 4917 tmp = FLOAT_TWO; 4918 else 4919 tmp = FLOAT_ONE; 4920 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4921 tmp = FLOAT_ZERO; 4922 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4923 } else { 4924 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4925 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4926 if (spec->cur_mic_type == DIGITAL_MIC) 4927 tmp = FLOAT_TWO; 4928 else 4929 tmp = FLOAT_ONE; 4930 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4931 tmp = FLOAT_ONE; 4932 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4933 msleep(20); 4934 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4935 } 4936 4937 return 1; 4938 } 4939 4940 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4941 { 4942 struct ca0132_spec *spec = codec->spec; 4943 unsigned int tmp; 4944 4945 if (spec->dsp_state != DSP_DOWNLOADED) 4946 return 0; 4947 4948 codec_dbg(codec, "%s\n", __func__); 4949 4950 chipio_set_stream_control(codec, 0x03, 0); 4951 chipio_set_stream_control(codec, 0x04, 0); 4952 4953 /* if CrystalVoice is off, vipsource should be 0 */ 4954 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4955 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4956 codec_dbg(codec, "%s: off.", __func__); 4957 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4958 4959 tmp = FLOAT_ZERO; 4960 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4961 4962 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4963 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4964 if (ca0132_quirk(spec) == QUIRK_R3DI) 4965 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4966 4967 4968 if (spec->in_enum_val == REAR_LINE_IN) 4969 tmp = FLOAT_ZERO; 4970 else { 4971 if (ca0132_quirk(spec) == QUIRK_SBZ) 4972 tmp = FLOAT_THREE; 4973 else 4974 tmp = FLOAT_ONE; 4975 } 4976 4977 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4978 4979 } else { 4980 codec_dbg(codec, "%s: on.", __func__); 4981 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4982 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4983 if (ca0132_quirk(spec) == QUIRK_R3DI) 4984 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 4985 4986 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 4987 tmp = FLOAT_TWO; 4988 else 4989 tmp = FLOAT_ONE; 4990 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4991 4992 tmp = FLOAT_ONE; 4993 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4994 4995 msleep(20); 4996 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4997 } 4998 4999 chipio_set_stream_control(codec, 0x03, 1); 5000 chipio_set_stream_control(codec, 0x04, 1); 5001 5002 return 1; 5003 } 5004 5005 /* 5006 * Select the active microphone. 5007 * If autodetect is enabled, mic will be selected based on jack detection. 5008 * If jack inserted, ext.mic will be selected, else built-in mic 5009 * If autodetect is disabled, mic will be selected based on selection. 5010 */ 5011 static int ca0132_select_mic(struct hda_codec *codec) 5012 { 5013 struct ca0132_spec *spec = codec->spec; 5014 int jack_present; 5015 int auto_jack; 5016 5017 codec_dbg(codec, "ca0132_select_mic\n"); 5018 5019 CLASS(snd_hda_power_pm, pm)(codec); 5020 5021 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5022 5023 if (auto_jack) 5024 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 5025 else 5026 jack_present = 5027 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 5028 5029 if (jack_present) 5030 spec->cur_mic_type = LINE_MIC_IN; 5031 else 5032 spec->cur_mic_type = DIGITAL_MIC; 5033 5034 if (spec->cur_mic_type == DIGITAL_MIC) { 5035 /* enable digital Mic */ 5036 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 5037 ca0132_set_dmic(codec, 1); 5038 ca0132_mic_boost_set(codec, 0); 5039 /* set voice focus */ 5040 ca0132_effects_set(codec, VOICE_FOCUS, 5041 spec->effects_switch 5042 [VOICE_FOCUS - EFFECT_START_NID]); 5043 } else { 5044 /* disable digital Mic */ 5045 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 5046 ca0132_set_dmic(codec, 0); 5047 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 5048 /* disable voice focus */ 5049 ca0132_effects_set(codec, VOICE_FOCUS, 0); 5050 } 5051 5052 return 0; 5053 } 5054 5055 /* 5056 * Select the active input. 5057 * Mic detection isn't used, because it's kind of pointless on the SBZ. 5058 * The front mic has no jack-detection, so the only way to switch to it 5059 * is to do it manually in alsamixer. 5060 */ 5061 static int ca0132_alt_select_in(struct hda_codec *codec) 5062 { 5063 struct ca0132_spec *spec = codec->spec; 5064 unsigned int tmp; 5065 5066 codec_dbg(codec, "%s\n", __func__); 5067 5068 CLASS(snd_hda_power_pm, pm)(codec); 5069 5070 chipio_set_stream_control(codec, 0x03, 0); 5071 chipio_set_stream_control(codec, 0x04, 0); 5072 5073 spec->cur_mic_type = spec->in_enum_val; 5074 5075 switch (spec->cur_mic_type) { 5076 case REAR_MIC: 5077 switch (ca0132_quirk(spec)) { 5078 case QUIRK_SBZ: 5079 case QUIRK_R3D: 5080 ca0113_mmio_gpio_set(codec, 0, false); 5081 tmp = FLOAT_THREE; 5082 break; 5083 case QUIRK_ZXR: 5084 tmp = FLOAT_THREE; 5085 break; 5086 case QUIRK_R3DI: 5087 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5088 tmp = FLOAT_ONE; 5089 break; 5090 case QUIRK_AE5: 5091 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5092 tmp = FLOAT_THREE; 5093 break; 5094 case QUIRK_AE7: 5095 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5096 tmp = FLOAT_THREE; 5097 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5098 SR_96_000); 5099 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5100 SR_96_000); 5101 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5102 break; 5103 default: 5104 tmp = FLOAT_ONE; 5105 break; 5106 } 5107 5108 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5109 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5110 if (ca0132_quirk(spec) == QUIRK_R3DI) 5111 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5112 5113 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5114 5115 chipio_set_stream_control(codec, 0x03, 1); 5116 chipio_set_stream_control(codec, 0x04, 1); 5117 switch (ca0132_quirk(spec)) { 5118 case QUIRK_SBZ: 5119 chipio_write(codec, 0x18B098, 0x0000000C); 5120 chipio_write(codec, 0x18B09C, 0x0000000C); 5121 break; 5122 case QUIRK_ZXR: 5123 chipio_write(codec, 0x18B098, 0x0000000C); 5124 chipio_write(codec, 0x18B09C, 0x000000CC); 5125 break; 5126 case QUIRK_AE5: 5127 chipio_write(codec, 0x18B098, 0x0000000C); 5128 chipio_write(codec, 0x18B09C, 0x0000004C); 5129 break; 5130 default: 5131 break; 5132 } 5133 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5134 break; 5135 case REAR_LINE_IN: 5136 ca0132_mic_boost_set(codec, 0); 5137 switch (ca0132_quirk(spec)) { 5138 case QUIRK_SBZ: 5139 case QUIRK_R3D: 5140 ca0113_mmio_gpio_set(codec, 0, false); 5141 break; 5142 case QUIRK_R3DI: 5143 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 5144 break; 5145 case QUIRK_AE5: 5146 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 5147 break; 5148 case QUIRK_AE7: 5149 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5150 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, 5151 SR_96_000); 5152 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, 5153 SR_96_000); 5154 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO); 5155 break; 5156 default: 5157 break; 5158 } 5159 5160 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5161 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5162 if (ca0132_quirk(spec) == QUIRK_R3DI) 5163 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5164 5165 if (ca0132_quirk(spec) == QUIRK_AE7) 5166 tmp = FLOAT_THREE; 5167 else 5168 tmp = FLOAT_ZERO; 5169 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5170 5171 switch (ca0132_quirk(spec)) { 5172 case QUIRK_SBZ: 5173 case QUIRK_AE5: 5174 chipio_write(codec, 0x18B098, 0x00000000); 5175 chipio_write(codec, 0x18B09C, 0x00000000); 5176 break; 5177 default: 5178 break; 5179 } 5180 chipio_set_stream_control(codec, 0x03, 1); 5181 chipio_set_stream_control(codec, 0x04, 1); 5182 break; 5183 case FRONT_MIC: 5184 switch (ca0132_quirk(spec)) { 5185 case QUIRK_SBZ: 5186 case QUIRK_R3D: 5187 ca0113_mmio_gpio_set(codec, 0, true); 5188 ca0113_mmio_gpio_set(codec, 5, false); 5189 tmp = FLOAT_THREE; 5190 break; 5191 case QUIRK_R3DI: 5192 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 5193 tmp = FLOAT_ONE; 5194 break; 5195 case QUIRK_AE5: 5196 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f); 5197 tmp = FLOAT_THREE; 5198 break; 5199 default: 5200 tmp = FLOAT_ONE; 5201 break; 5202 } 5203 5204 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 5205 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 5206 if (ca0132_quirk(spec) == QUIRK_R3DI) 5207 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 5208 5209 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5210 5211 chipio_set_stream_control(codec, 0x03, 1); 5212 chipio_set_stream_control(codec, 0x04, 1); 5213 5214 switch (ca0132_quirk(spec)) { 5215 case QUIRK_SBZ: 5216 chipio_write(codec, 0x18B098, 0x0000000C); 5217 chipio_write(codec, 0x18B09C, 0x000000CC); 5218 break; 5219 case QUIRK_AE5: 5220 chipio_write(codec, 0x18B098, 0x0000000C); 5221 chipio_write(codec, 0x18B09C, 0x0000004C); 5222 break; 5223 default: 5224 break; 5225 } 5226 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5227 break; 5228 } 5229 ca0132_cvoice_switch_set(codec); 5230 5231 return 0; 5232 } 5233 5234 /* 5235 * Check if VNODE settings take effect immediately. 5236 */ 5237 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 5238 hda_nid_t vnid, 5239 hda_nid_t *shared_nid) 5240 { 5241 struct ca0132_spec *spec = codec->spec; 5242 hda_nid_t nid; 5243 5244 switch (vnid) { 5245 case VNID_SPK: 5246 nid = spec->shared_out_nid; 5247 break; 5248 case VNID_MIC: 5249 nid = spec->shared_mic_nid; 5250 break; 5251 default: 5252 return false; 5253 } 5254 5255 if (shared_nid) 5256 *shared_nid = nid; 5257 5258 return true; 5259 } 5260 5261 /* 5262 * The following functions are control change helpers. 5263 * They return 0 if no changed. Return 1 if changed. 5264 */ 5265 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 5266 { 5267 struct ca0132_spec *spec = codec->spec; 5268 unsigned int tmp; 5269 5270 /* based on CrystalVoice state to enable VoiceFX. */ 5271 if (enable) { 5272 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 5273 FLOAT_ONE : FLOAT_ZERO; 5274 } else { 5275 tmp = FLOAT_ZERO; 5276 } 5277 5278 dspio_set_uint_param(codec, ca0132_voicefx.mid, 5279 ca0132_voicefx.reqs[0], tmp); 5280 5281 return 1; 5282 } 5283 5284 /* 5285 * Set the effects parameters 5286 */ 5287 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 5288 { 5289 struct ca0132_spec *spec = codec->spec; 5290 unsigned int on, tmp, channel_cfg; 5291 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 5292 int err = 0; 5293 int idx = nid - EFFECT_START_NID; 5294 5295 if ((idx < 0) || (idx >= num_fx)) 5296 return 0; /* no changed */ 5297 5298 /* for out effect, qualify with PE */ 5299 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 5300 /* if PE if off, turn off out effects. */ 5301 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 5302 val = 0; 5303 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) { 5304 channel_cfg = spec->channel_cfg_val; 5305 if (channel_cfg != SPEAKER_CHANNELS_2_0 && 5306 channel_cfg != SPEAKER_CHANNELS_4_0) 5307 val = 0; 5308 } 5309 } 5310 5311 /* for in effect, qualify with CrystalVoice */ 5312 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 5313 /* if CrystalVoice if off, turn off in effects. */ 5314 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 5315 val = 0; 5316 5317 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 5318 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 5319 val = 0; 5320 5321 /* If Voice Focus on SBZ, set to two channel. */ 5322 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) 5323 && (spec->cur_mic_type != REAR_LINE_IN)) { 5324 if (spec->effects_switch[CRYSTAL_VOICE - 5325 EFFECT_START_NID]) { 5326 5327 if (spec->effects_switch[VOICE_FOCUS - 5328 EFFECT_START_NID]) { 5329 tmp = FLOAT_TWO; 5330 val = 1; 5331 } else 5332 tmp = FLOAT_ONE; 5333 5334 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 5335 } 5336 } 5337 /* 5338 * For SBZ noise reduction, there's an extra command 5339 * to module ID 0x47. No clue why. 5340 */ 5341 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) 5342 && (spec->cur_mic_type != REAR_LINE_IN)) { 5343 if (spec->effects_switch[CRYSTAL_VOICE - 5344 EFFECT_START_NID]) { 5345 if (spec->effects_switch[NOISE_REDUCTION - 5346 EFFECT_START_NID]) 5347 tmp = FLOAT_ONE; 5348 else 5349 tmp = FLOAT_ZERO; 5350 } else 5351 tmp = FLOAT_ZERO; 5352 5353 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 5354 } 5355 5356 /* If rear line in disable effects. */ 5357 if (ca0132_use_alt_functions(spec) && 5358 spec->in_enum_val == REAR_LINE_IN) 5359 val = 0; 5360 } 5361 5362 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 5363 nid, val); 5364 5365 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 5366 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5367 ca0132_effects[idx].reqs[0], on); 5368 5369 if (err < 0) 5370 return 0; /* no changed */ 5371 5372 return 1; 5373 } 5374 5375 /* 5376 * Turn on/off Playback Enhancements 5377 */ 5378 static int ca0132_pe_switch_set(struct hda_codec *codec) 5379 { 5380 struct ca0132_spec *spec = codec->spec; 5381 hda_nid_t nid; 5382 int i, ret = 0; 5383 5384 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 5385 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 5386 5387 if (ca0132_use_alt_functions(spec)) 5388 ca0132_alt_select_out(codec); 5389 5390 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 5391 nid = OUT_EFFECT_START_NID; 5392 /* PE affects all out effects */ 5393 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 5394 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5395 5396 return ret; 5397 } 5398 5399 /* Check if Mic1 is streaming, if so, stop streaming */ 5400 static int stop_mic1(struct hda_codec *codec) 5401 { 5402 struct ca0132_spec *spec = codec->spec; 5403 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 5404 AC_VERB_GET_CONV, 0); 5405 if (oldval != 0) 5406 snd_hda_codec_write(codec, spec->adcs[0], 0, 5407 AC_VERB_SET_CHANNEL_STREAMID, 5408 0); 5409 return oldval; 5410 } 5411 5412 /* Resume Mic1 streaming if it was stopped. */ 5413 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 5414 { 5415 struct ca0132_spec *spec = codec->spec; 5416 /* Restore the previous stream and channel */ 5417 if (oldval != 0) 5418 snd_hda_codec_write(codec, spec->adcs[0], 0, 5419 AC_VERB_SET_CHANNEL_STREAMID, 5420 oldval); 5421 } 5422 5423 /* 5424 * Turn on/off CrystalVoice 5425 */ 5426 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 5427 { 5428 struct ca0132_spec *spec = codec->spec; 5429 hda_nid_t nid; 5430 int i, ret = 0; 5431 unsigned int oldval; 5432 5433 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 5434 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 5435 5436 i = IN_EFFECT_START_NID - EFFECT_START_NID; 5437 nid = IN_EFFECT_START_NID; 5438 /* CrystalVoice affects all in effects */ 5439 for (; nid < IN_EFFECT_END_NID; nid++, i++) 5440 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5441 5442 /* including VoiceFX */ 5443 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 5444 5445 /* set correct vipsource */ 5446 oldval = stop_mic1(codec); 5447 if (ca0132_use_alt_functions(spec)) 5448 ret |= ca0132_alt_set_vipsource(codec, 1); 5449 else 5450 ret |= ca0132_set_vipsource(codec, 1); 5451 resume_mic1(codec, oldval); 5452 return ret; 5453 } 5454 5455 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 5456 { 5457 struct ca0132_spec *spec = codec->spec; 5458 int ret = 0; 5459 5460 if (val) /* on */ 5461 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5462 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5463 else /* off */ 5464 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5465 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5466 5467 return ret; 5468 } 5469 5470 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5471 { 5472 struct ca0132_spec *spec = codec->spec; 5473 int ret = 0; 5474 5475 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5476 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5477 return ret; 5478 } 5479 5480 static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5481 { 5482 unsigned int i; 5483 5484 for (i = 0; i < 4; i++) 5485 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5486 ae5_headphone_gain_presets[val].vals[i]); 5487 return 0; 5488 } 5489 5490 /* 5491 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5492 * amplifier to handle a 600 ohm load. 5493 */ 5494 static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5495 { 5496 ca0113_mmio_gpio_set(codec, 1, val); 5497 5498 return 0; 5499 } 5500 5501 /* 5502 * Manual output selection (HP/Speaker Playback Switch or alt Output Select) 5503 * is meaningful only when HP/Speaker auto-detect is disabled, since the 5504 * select_out path always prefers jack presence when auto-detect is on. When 5505 * the user explicitly chooses an output, turn auto-detect off so the manual 5506 * choice actually takes effect, and notify userspace so the auto-detect 5507 * control reflects the new state. 5508 */ 5509 static void ca0132_disable_hp_auto_detect(struct hda_codec *codec) 5510 { 5511 struct ca0132_spec *spec = codec->spec; 5512 struct snd_kcontrol *kctl; 5513 5514 if (!spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]) 5515 return; 5516 5517 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID] = 0; 5518 kctl = snd_hda_find_mixer_ctl(codec, 5519 "HP/Speaker Auto Detect Playback Switch"); 5520 if (kctl) 5521 snd_ctl_notify(codec->card, SNDRV_CTL_EVENT_MASK_VALUE, 5522 &kctl->id); 5523 } 5524 5525 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5526 struct snd_ctl_elem_value *ucontrol) 5527 { 5528 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5529 hda_nid_t nid = get_amp_nid(kcontrol); 5530 hda_nid_t shared_nid = 0; 5531 bool effective; 5532 int ret = 0; 5533 struct ca0132_spec *spec = codec->spec; 5534 int auto_jack; 5535 5536 if (nid == VNID_HP_SEL) { 5537 ca0132_disable_hp_auto_detect(codec); 5538 if (ca0132_use_alt_functions(spec)) 5539 ca0132_alt_select_out(codec); 5540 else 5541 ca0132_select_out(codec); 5542 return 1; 5543 } 5544 5545 if (nid == VNID_AMIC1_SEL) { 5546 auto_jack = 5547 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5548 if (!auto_jack) 5549 ca0132_select_mic(codec); 5550 return 1; 5551 } 5552 5553 if (nid == VNID_HP_ASEL) { 5554 if (ca0132_use_alt_functions(spec)) 5555 ca0132_alt_select_out(codec); 5556 else 5557 ca0132_select_out(codec); 5558 return 1; 5559 } 5560 5561 if (nid == VNID_AMIC1_ASEL) { 5562 ca0132_select_mic(codec); 5563 return 1; 5564 } 5565 5566 /* if effective conditions, then update hw immediately. */ 5567 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5568 if (effective) { 5569 int dir = get_amp_direction(kcontrol); 5570 int ch = get_amp_channels(kcontrol); 5571 unsigned long pval; 5572 5573 guard(mutex)(&codec->control_mutex); 5574 pval = kcontrol->private_value; 5575 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5576 0, dir); 5577 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5578 kcontrol->private_value = pval; 5579 } 5580 5581 return ret; 5582 } 5583 /* End of control change helpers. */ 5584 5585 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec, 5586 long idx) 5587 { 5588 CLASS(snd_hda_power, pm)(codec); 5589 5590 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ, 5591 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int)); 5592 } 5593 5594 /* 5595 * Below I've added controls to mess with the effect levels, I've only enabled 5596 * them on the Sound Blaster Z, but they would probably also work on the 5597 * Chromebook. I figured they were probably tuned specifically for it, and left 5598 * out for a reason. 5599 */ 5600 5601 /* Sets DSP effect level from the sliders above the controls */ 5602 5603 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5604 const unsigned int *lookup, int idx) 5605 { 5606 int i = 0; 5607 unsigned int y; 5608 /* 5609 * For X_BASS, req 2 is actually crossover freq instead of 5610 * effect level 5611 */ 5612 if (nid == X_BASS) 5613 y = 2; 5614 else 5615 y = 1; 5616 5617 CLASS(snd_hda_power, pm)(codec); 5618 if (nid == XBASS_XOVER) { 5619 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5620 if (ca0132_effects[i].nid == X_BASS) 5621 break; 5622 5623 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5624 ca0132_effects[i].reqs[1], 5625 &(lookup[idx - 1]), sizeof(unsigned int)); 5626 } else { 5627 /* Find the actual effect structure */ 5628 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5629 if (nid == ca0132_effects[i].nid) 5630 break; 5631 5632 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5633 ca0132_effects[i].reqs[y], 5634 &(lookup[idx]), sizeof(unsigned int)); 5635 } 5636 5637 return 0; 5638 } 5639 5640 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5641 struct snd_ctl_elem_value *ucontrol) 5642 { 5643 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5644 struct ca0132_spec *spec = codec->spec; 5645 long *valp = ucontrol->value.integer.value; 5646 hda_nid_t nid = get_amp_nid(kcontrol); 5647 5648 if (nid == BASS_REDIRECTION_XOVER) 5649 *valp = spec->bass_redirect_xover_freq; 5650 else 5651 *valp = spec->xbass_xover_freq; 5652 5653 return 0; 5654 } 5655 5656 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5657 struct snd_ctl_elem_value *ucontrol) 5658 { 5659 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5660 struct ca0132_spec *spec = codec->spec; 5661 hda_nid_t nid = get_amp_nid(kcontrol); 5662 long *valp = ucontrol->value.integer.value; 5663 int idx = nid - OUT_EFFECT_START_NID; 5664 5665 *valp = spec->fx_ctl_val[idx]; 5666 return 0; 5667 } 5668 5669 /* 5670 * The X-bass crossover starts at 10hz, so the min is 1. The 5671 * frequency is set in multiples of 10. 5672 */ 5673 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5674 struct snd_ctl_elem_info *uinfo) 5675 { 5676 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5677 uinfo->count = 1; 5678 uinfo->value.integer.min = 1; 5679 uinfo->value.integer.max = 100; 5680 uinfo->value.integer.step = 1; 5681 5682 return 0; 5683 } 5684 5685 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5686 struct snd_ctl_elem_info *uinfo) 5687 { 5688 int chs = get_amp_channels(kcontrol); 5689 5690 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5691 uinfo->count = chs == 3 ? 2 : 1; 5692 uinfo->value.integer.min = 0; 5693 uinfo->value.integer.max = 100; 5694 uinfo->value.integer.step = 1; 5695 5696 return 0; 5697 } 5698 5699 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5700 struct snd_ctl_elem_value *ucontrol) 5701 { 5702 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5703 struct ca0132_spec *spec = codec->spec; 5704 hda_nid_t nid = get_amp_nid(kcontrol); 5705 long *valp = ucontrol->value.integer.value; 5706 long *cur_val; 5707 int idx; 5708 5709 if (nid == BASS_REDIRECTION_XOVER) 5710 cur_val = &spec->bass_redirect_xover_freq; 5711 else 5712 cur_val = &spec->xbass_xover_freq; 5713 5714 /* any change? */ 5715 if (*cur_val == *valp) 5716 return 0; 5717 5718 *cur_val = *valp; 5719 5720 idx = *valp; 5721 if (nid == BASS_REDIRECTION_XOVER) 5722 ca0132_alt_bass_redirection_xover_set(codec, *cur_val); 5723 else 5724 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5725 5726 return 0; 5727 } 5728 5729 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5730 struct snd_ctl_elem_value *ucontrol) 5731 { 5732 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5733 struct ca0132_spec *spec = codec->spec; 5734 hda_nid_t nid = get_amp_nid(kcontrol); 5735 long *valp = ucontrol->value.integer.value; 5736 int idx; 5737 5738 idx = nid - EFFECT_START_NID; 5739 /* any change? */ 5740 if (spec->fx_ctl_val[idx] == *valp) 5741 return 0; 5742 5743 spec->fx_ctl_val[idx] = *valp; 5744 5745 idx = *valp; 5746 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5747 5748 return 0; 5749 } 5750 5751 5752 /* 5753 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5754 * only has off or full 30 dB, and didn't like making a volume slider that has 5755 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5756 */ 5757 #define MIC_BOOST_NUM_OF_STEPS 4 5758 #define MIC_BOOST_ENUM_MAX_STRLEN 10 5759 5760 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5761 struct snd_ctl_elem_info *uinfo) 5762 { 5763 const char *sfx = "dB"; 5764 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5765 5766 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5767 uinfo->count = 1; 5768 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5769 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5770 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5771 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 5772 strscpy(uinfo->value.enumerated.name, namestr); 5773 return 0; 5774 } 5775 5776 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5777 struct snd_ctl_elem_value *ucontrol) 5778 { 5779 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5780 struct ca0132_spec *spec = codec->spec; 5781 5782 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5783 return 0; 5784 } 5785 5786 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5787 struct snd_ctl_elem_value *ucontrol) 5788 { 5789 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5790 struct ca0132_spec *spec = codec->spec; 5791 int sel = ucontrol->value.enumerated.item[0]; 5792 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5793 5794 if (sel >= items) 5795 return 0; 5796 5797 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5798 sel); 5799 5800 spec->mic_boost_enum_val = sel; 5801 5802 if (spec->in_enum_val != REAR_LINE_IN) 5803 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5804 5805 return 1; 5806 } 5807 5808 /* 5809 * Sound BlasterX AE-5 Headphone Gain Controls. 5810 */ 5811 #define AE5_HEADPHONE_GAIN_MAX 3 5812 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5813 struct snd_ctl_elem_info *uinfo) 5814 { 5815 const char *sfx = " Ohms)"; 5816 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5817 5818 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5819 uinfo->count = 1; 5820 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5821 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5822 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5823 sprintf(namestr, "%s %s", 5824 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5825 sfx); 5826 strscpy(uinfo->value.enumerated.name, namestr); 5827 return 0; 5828 } 5829 5830 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5831 struct snd_ctl_elem_value *ucontrol) 5832 { 5833 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5834 struct ca0132_spec *spec = codec->spec; 5835 5836 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5837 return 0; 5838 } 5839 5840 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5841 struct snd_ctl_elem_value *ucontrol) 5842 { 5843 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5844 struct ca0132_spec *spec = codec->spec; 5845 int sel = ucontrol->value.enumerated.item[0]; 5846 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5847 5848 if (sel >= items) 5849 return 0; 5850 5851 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5852 sel); 5853 5854 spec->ae5_headphone_gain_val = sel; 5855 5856 if (spec->out_enum_val == HEADPHONE_OUT) 5857 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5858 5859 return 1; 5860 } 5861 5862 /* 5863 * Sound BlasterX AE-5 sound filter enumerated control. 5864 */ 5865 #define AE5_SOUND_FILTER_MAX 3 5866 5867 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5868 struct snd_ctl_elem_info *uinfo) 5869 { 5870 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5871 5872 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5873 uinfo->count = 1; 5874 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5875 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5876 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5877 sprintf(namestr, "%s", 5878 ae5_filter_presets[uinfo->value.enumerated.item].name); 5879 strscpy(uinfo->value.enumerated.name, namestr); 5880 return 0; 5881 } 5882 5883 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5884 struct snd_ctl_elem_value *ucontrol) 5885 { 5886 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5887 struct ca0132_spec *spec = codec->spec; 5888 5889 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5890 return 0; 5891 } 5892 5893 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5894 struct snd_ctl_elem_value *ucontrol) 5895 { 5896 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5897 struct ca0132_spec *spec = codec->spec; 5898 int sel = ucontrol->value.enumerated.item[0]; 5899 unsigned int items = AE5_SOUND_FILTER_MAX; 5900 5901 if (sel >= items) 5902 return 0; 5903 5904 codec_dbg(codec, "ae5_sound_filter: %s\n", 5905 ae5_filter_presets[sel].name); 5906 5907 spec->ae5_filter_val = sel; 5908 5909 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5910 ae5_filter_presets[sel].val); 5911 5912 return 1; 5913 } 5914 5915 /* 5916 * Input Select Control for alternative ca0132 codecs. This exists because 5917 * front microphone has no auto-detect, and we need a way to set the rear 5918 * as line-in 5919 */ 5920 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5921 struct snd_ctl_elem_info *uinfo) 5922 { 5923 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5924 uinfo->count = 1; 5925 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5926 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5927 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5928 strscpy(uinfo->value.enumerated.name, 5929 in_src_str[uinfo->value.enumerated.item]); 5930 return 0; 5931 } 5932 5933 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5934 struct snd_ctl_elem_value *ucontrol) 5935 { 5936 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5937 struct ca0132_spec *spec = codec->spec; 5938 5939 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5940 return 0; 5941 } 5942 5943 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5944 struct snd_ctl_elem_value *ucontrol) 5945 { 5946 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5947 struct ca0132_spec *spec = codec->spec; 5948 int sel = ucontrol->value.enumerated.item[0]; 5949 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5950 5951 /* 5952 * The AE-7 has no front microphone, so limit items to 2: rear mic and 5953 * line-in. 5954 */ 5955 if (ca0132_quirk(spec) == QUIRK_AE7) 5956 items = 2; 5957 5958 if (sel >= items) 5959 return 0; 5960 5961 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5962 sel, in_src_str[sel]); 5963 5964 spec->in_enum_val = sel; 5965 5966 ca0132_alt_select_in(codec); 5967 5968 return 1; 5969 } 5970 5971 /* Sound Blaster Z Output Select Control */ 5972 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 5973 struct snd_ctl_elem_info *uinfo) 5974 { 5975 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5976 uinfo->count = 1; 5977 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 5978 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 5979 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 5980 strscpy(uinfo->value.enumerated.name, 5981 out_type_str[uinfo->value.enumerated.item]); 5982 return 0; 5983 } 5984 5985 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 5986 struct snd_ctl_elem_value *ucontrol) 5987 { 5988 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5989 struct ca0132_spec *spec = codec->spec; 5990 5991 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 5992 return 0; 5993 } 5994 5995 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 5996 struct snd_ctl_elem_value *ucontrol) 5997 { 5998 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5999 struct ca0132_spec *spec = codec->spec; 6000 int sel = ucontrol->value.enumerated.item[0]; 6001 unsigned int items = NUM_OF_OUTPUTS; 6002 6003 if (sel >= items) 6004 return 0; 6005 6006 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 6007 sel, out_type_str[sel]); 6008 6009 spec->out_enum_val = sel; 6010 6011 ca0132_disable_hp_auto_detect(codec); 6012 ca0132_alt_select_out(codec); 6013 6014 return 1; 6015 } 6016 6017 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */ 6018 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol, 6019 struct snd_ctl_elem_info *uinfo) 6020 { 6021 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6022 6023 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6024 uinfo->count = 1; 6025 uinfo->value.enumerated.items = items; 6026 if (uinfo->value.enumerated.item >= items) 6027 uinfo->value.enumerated.item = items - 1; 6028 strscpy(uinfo->value.enumerated.name, 6029 speaker_channel_cfgs[uinfo->value.enumerated.item].name); 6030 return 0; 6031 } 6032 6033 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol, 6034 struct snd_ctl_elem_value *ucontrol) 6035 { 6036 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6037 struct ca0132_spec *spec = codec->spec; 6038 6039 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val; 6040 return 0; 6041 } 6042 6043 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol, 6044 struct snd_ctl_elem_value *ucontrol) 6045 { 6046 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6047 struct ca0132_spec *spec = codec->spec; 6048 int sel = ucontrol->value.enumerated.item[0]; 6049 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT; 6050 6051 if (sel >= items) 6052 return 0; 6053 6054 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n", 6055 sel, speaker_channel_cfgs[sel].name); 6056 6057 spec->channel_cfg_val = sel; 6058 6059 if (spec->out_enum_val == SPEAKER_OUT) 6060 ca0132_alt_select_out(codec); 6061 6062 return 1; 6063 } 6064 6065 /* 6066 * Smart Volume output setting control. Three different settings, Normal, 6067 * which takes the value from the smart volume slider. The two others, loud 6068 * and night, disregard the slider value and have uneditable values. 6069 */ 6070 #define NUM_OF_SVM_SETTINGS 3 6071 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 6072 6073 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 6074 struct snd_ctl_elem_info *uinfo) 6075 { 6076 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6077 uinfo->count = 1; 6078 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 6079 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 6080 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 6081 strscpy(uinfo->value.enumerated.name, 6082 out_svm_set_enum_str[uinfo->value.enumerated.item]); 6083 return 0; 6084 } 6085 6086 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 6087 struct snd_ctl_elem_value *ucontrol) 6088 { 6089 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6090 struct ca0132_spec *spec = codec->spec; 6091 6092 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 6093 return 0; 6094 } 6095 6096 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 6097 struct snd_ctl_elem_value *ucontrol) 6098 { 6099 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6100 struct ca0132_spec *spec = codec->spec; 6101 int sel = ucontrol->value.enumerated.item[0]; 6102 unsigned int items = NUM_OF_SVM_SETTINGS; 6103 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 6104 unsigned int tmp; 6105 6106 if (sel >= items) 6107 return 0; 6108 6109 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 6110 sel, out_svm_set_enum_str[sel]); 6111 6112 spec->smart_volume_setting = sel; 6113 6114 switch (sel) { 6115 case 0: 6116 tmp = FLOAT_ZERO; 6117 break; 6118 case 1: 6119 tmp = FLOAT_ONE; 6120 break; 6121 case 2: 6122 tmp = FLOAT_TWO; 6123 break; 6124 default: 6125 tmp = FLOAT_ZERO; 6126 break; 6127 } 6128 /* Req 2 is the Smart Volume Setting req. */ 6129 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 6130 ca0132_effects[idx].reqs[2], tmp); 6131 return 1; 6132 } 6133 6134 /* Sound Blaster Z EQ preset controls */ 6135 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 6136 struct snd_ctl_elem_info *uinfo) 6137 { 6138 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6139 6140 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6141 uinfo->count = 1; 6142 uinfo->value.enumerated.items = items; 6143 if (uinfo->value.enumerated.item >= items) 6144 uinfo->value.enumerated.item = items - 1; 6145 strscpy(uinfo->value.enumerated.name, 6146 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 6147 return 0; 6148 } 6149 6150 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 6151 struct snd_ctl_elem_value *ucontrol) 6152 { 6153 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6154 struct ca0132_spec *spec = codec->spec; 6155 6156 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 6157 return 0; 6158 } 6159 6160 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 6161 struct snd_ctl_elem_value *ucontrol) 6162 { 6163 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6164 struct ca0132_spec *spec = codec->spec; 6165 int i, err = 0; 6166 int sel = ucontrol->value.enumerated.item[0]; 6167 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 6168 6169 if (sel >= items) 6170 return 0; 6171 6172 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 6173 ca0132_alt_eq_presets[sel].name); 6174 /* 6175 * Idx 0 is default. 6176 * Default needs to qualify with CrystalVoice state. 6177 */ 6178 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 6179 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 6180 ca0132_alt_eq_enum.reqs[i], 6181 ca0132_alt_eq_presets[sel].vals[i]); 6182 if (err < 0) 6183 break; 6184 } 6185 6186 if (err >= 0) 6187 spec->eq_preset_val = sel; 6188 6189 return 1; 6190 } 6191 6192 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 6193 struct snd_ctl_elem_info *uinfo) 6194 { 6195 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 6196 6197 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 6198 uinfo->count = 1; 6199 uinfo->value.enumerated.items = items; 6200 if (uinfo->value.enumerated.item >= items) 6201 uinfo->value.enumerated.item = items - 1; 6202 strscpy(uinfo->value.enumerated.name, 6203 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 6204 return 0; 6205 } 6206 6207 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 6208 struct snd_ctl_elem_value *ucontrol) 6209 { 6210 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6211 struct ca0132_spec *spec = codec->spec; 6212 6213 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 6214 return 0; 6215 } 6216 6217 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 6218 struct snd_ctl_elem_value *ucontrol) 6219 { 6220 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6221 struct ca0132_spec *spec = codec->spec; 6222 int i, err = 0; 6223 int sel = ucontrol->value.enumerated.item[0]; 6224 6225 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 6226 return 0; 6227 6228 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 6229 sel, ca0132_voicefx_presets[sel].name); 6230 6231 /* 6232 * Idx 0 is default. 6233 * Default needs to qualify with CrystalVoice state. 6234 */ 6235 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 6236 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 6237 ca0132_voicefx.reqs[i], 6238 ca0132_voicefx_presets[sel].vals[i]); 6239 if (err < 0) 6240 break; 6241 } 6242 6243 if (err >= 0) { 6244 spec->voicefx_val = sel; 6245 /* enable voice fx */ 6246 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 6247 } 6248 6249 return 1; 6250 } 6251 6252 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 6253 struct snd_ctl_elem_value *ucontrol) 6254 { 6255 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6256 struct ca0132_spec *spec = codec->spec; 6257 hda_nid_t nid = get_amp_nid(kcontrol); 6258 int ch = get_amp_channels(kcontrol); 6259 long *valp = ucontrol->value.integer.value; 6260 6261 /* vnode */ 6262 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6263 if (ch & 1) { 6264 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 6265 valp++; 6266 } 6267 if (ch & 2) { 6268 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 6269 valp++; 6270 } 6271 return 0; 6272 } 6273 6274 /* effects, include PE and CrystalVoice */ 6275 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 6276 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 6277 return 0; 6278 } 6279 6280 /* mic boost */ 6281 if (nid == spec->input_pins[0]) { 6282 *valp = spec->cur_mic_boost; 6283 return 0; 6284 } 6285 6286 if (nid == ZXR_HEADPHONE_GAIN) { 6287 *valp = spec->zxr_gain_set; 6288 return 0; 6289 } 6290 6291 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6292 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT]; 6293 return 0; 6294 } 6295 6296 if (nid == BASS_REDIRECTION) { 6297 *valp = spec->bass_redirection_val; 6298 return 0; 6299 } 6300 6301 return 0; 6302 } 6303 6304 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 6305 struct snd_ctl_elem_value *ucontrol) 6306 { 6307 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6308 struct ca0132_spec *spec = codec->spec; 6309 hda_nid_t nid = get_amp_nid(kcontrol); 6310 int ch = get_amp_channels(kcontrol); 6311 long *valp = ucontrol->value.integer.value; 6312 6313 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 6314 nid, *valp); 6315 6316 CLASS(snd_hda_power, pm)(codec); 6317 /* vnode */ 6318 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 6319 if (ch & 1) { 6320 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 6321 valp++; 6322 } 6323 if (ch & 2) { 6324 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 6325 valp++; 6326 } 6327 return ca0132_vnode_switch_set(kcontrol, ucontrol); 6328 } 6329 6330 /* PE */ 6331 if (nid == PLAY_ENHANCEMENT) { 6332 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6333 return ca0132_pe_switch_set(codec); 6334 } 6335 6336 /* CrystalVoice */ 6337 if (nid == CRYSTAL_VOICE) { 6338 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6339 return ca0132_cvoice_switch_set(codec); 6340 } 6341 6342 /* out and in effects */ 6343 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 6344 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 6345 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 6346 return ca0132_effects_set(codec, nid, *valp); 6347 } 6348 6349 /* mic boost */ 6350 if (nid == spec->input_pins[0]) { 6351 spec->cur_mic_boost = *valp; 6352 if (ca0132_use_alt_functions(spec)) { 6353 if (spec->in_enum_val != REAR_LINE_IN) 6354 return ca0132_mic_boost_set(codec, *valp); 6355 } else { 6356 /* Mic boost does not apply to Digital Mic */ 6357 if (spec->cur_mic_type != DIGITAL_MIC) 6358 return ca0132_mic_boost_set(codec, *valp); 6359 } 6360 6361 return 1; 6362 } 6363 6364 if (nid == ZXR_HEADPHONE_GAIN) { 6365 spec->zxr_gain_set = *valp; 6366 if (spec->cur_out_type == HEADPHONE_OUT) 6367 return zxr_headphone_gain_set(codec, *valp); 6368 else 6369 return 0; 6370 } 6371 6372 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) { 6373 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp; 6374 if (spec->cur_out_type == SPEAKER_OUT) 6375 ca0132_alt_set_full_range_speaker(codec); 6376 6377 return 0; 6378 } 6379 6380 if (nid == BASS_REDIRECTION) { 6381 spec->bass_redirection_val = *valp; 6382 if (spec->cur_out_type == SPEAKER_OUT) 6383 ca0132_alt_surround_set_bass_redirection(codec, *valp); 6384 6385 return 0; 6386 } 6387 6388 return 1; 6389 } 6390 6391 /* 6392 * Volume related 6393 */ 6394 /* 6395 * Sets the internal DSP decibel level to match the DAC for output, and the 6396 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 6397 * all alternative codecs set DSP playback volume. 6398 */ 6399 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 6400 { 6401 struct ca0132_spec *spec = codec->spec; 6402 unsigned int dsp_dir; 6403 unsigned int lookup_val; 6404 6405 if (nid == VNID_SPK) 6406 dsp_dir = DSP_VOL_OUT; 6407 else 6408 dsp_dir = DSP_VOL_IN; 6409 6410 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 6411 6412 dspio_set_uint_param(codec, 6413 ca0132_alt_vol_ctls[dsp_dir].mid, 6414 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 6415 float_vol_db_lookup[lookup_val]); 6416 6417 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 6418 6419 dspio_set_uint_param(codec, 6420 ca0132_alt_vol_ctls[dsp_dir].mid, 6421 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 6422 float_vol_db_lookup[lookup_val]); 6423 6424 dspio_set_uint_param(codec, 6425 ca0132_alt_vol_ctls[dsp_dir].mid, 6426 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 6427 } 6428 6429 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 6430 struct snd_ctl_elem_info *uinfo) 6431 { 6432 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6433 struct ca0132_spec *spec = codec->spec; 6434 hda_nid_t nid = get_amp_nid(kcontrol); 6435 int ch = get_amp_channels(kcontrol); 6436 int dir = get_amp_direction(kcontrol); 6437 unsigned long pval; 6438 int err; 6439 6440 switch (nid) { 6441 case VNID_SPK: 6442 /* follow shared_out info */ 6443 nid = spec->shared_out_nid; 6444 scoped_guard(mutex, &codec->control_mutex) { 6445 pval = kcontrol->private_value; 6446 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6447 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6448 kcontrol->private_value = pval; 6449 } 6450 break; 6451 case VNID_MIC: 6452 /* follow shared_mic info */ 6453 nid = spec->shared_mic_nid; 6454 scoped_guard(mutex, &codec->control_mutex) { 6455 pval = kcontrol->private_value; 6456 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6457 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6458 kcontrol->private_value = pval; 6459 } 6460 break; 6461 default: 6462 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 6463 } 6464 return err; 6465 } 6466 6467 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 6468 struct snd_ctl_elem_value *ucontrol) 6469 { 6470 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6471 struct ca0132_spec *spec = codec->spec; 6472 hda_nid_t nid = get_amp_nid(kcontrol); 6473 int ch = get_amp_channels(kcontrol); 6474 long *valp = ucontrol->value.integer.value; 6475 6476 /* store the left and right volume */ 6477 if (ch & 1) { 6478 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 6479 valp++; 6480 } 6481 if (ch & 2) { 6482 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 6483 valp++; 6484 } 6485 return 0; 6486 } 6487 6488 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 6489 struct snd_ctl_elem_value *ucontrol) 6490 { 6491 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6492 struct ca0132_spec *spec = codec->spec; 6493 hda_nid_t nid = get_amp_nid(kcontrol); 6494 int ch = get_amp_channels(kcontrol); 6495 long *valp = ucontrol->value.integer.value; 6496 hda_nid_t shared_nid = 0; 6497 bool effective; 6498 int changed = 1; 6499 6500 /* store the left and right volume */ 6501 if (ch & 1) { 6502 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 6503 valp++; 6504 } 6505 if (ch & 2) { 6506 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 6507 valp++; 6508 } 6509 6510 /* if effective conditions, then update hw immediately. */ 6511 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 6512 if (effective) { 6513 int dir = get_amp_direction(kcontrol); 6514 unsigned long pval; 6515 6516 CLASS(snd_hda_power, pm)(codec); 6517 guard(mutex)(&codec->control_mutex); 6518 pval = kcontrol->private_value; 6519 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 6520 0, dir); 6521 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6522 kcontrol->private_value = pval; 6523 } 6524 6525 return changed; 6526 } 6527 6528 /* 6529 * This function is the same as the one above, because using an if statement 6530 * inside of the above volume control for the DSP volume would cause too much 6531 * lag. This is a lot more smooth. 6532 */ 6533 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 6534 struct snd_ctl_elem_value *ucontrol) 6535 { 6536 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6537 struct ca0132_spec *spec = codec->spec; 6538 hda_nid_t nid = get_amp_nid(kcontrol); 6539 int ch = get_amp_channels(kcontrol); 6540 long *valp = ucontrol->value.integer.value; 6541 hda_nid_t vnid = 0; 6542 6543 switch (nid) { 6544 case 0x02: 6545 vnid = VNID_SPK; 6546 break; 6547 case 0x07: 6548 vnid = VNID_MIC; 6549 break; 6550 } 6551 6552 /* store the left and right volume */ 6553 if (ch & 1) { 6554 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 6555 valp++; 6556 } 6557 if (ch & 2) { 6558 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 6559 valp++; 6560 } 6561 6562 CLASS(snd_hda_power, pm)(codec); 6563 ca0132_alt_dsp_volume_put(codec, vnid); 6564 guard(mutex)(&codec->control_mutex); 6565 return snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6566 } 6567 6568 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 6569 unsigned int size, unsigned int __user *tlv) 6570 { 6571 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6572 struct ca0132_spec *spec = codec->spec; 6573 hda_nid_t nid = get_amp_nid(kcontrol); 6574 int ch = get_amp_channels(kcontrol); 6575 int dir = get_amp_direction(kcontrol); 6576 unsigned long pval; 6577 int err; 6578 6579 switch (nid) { 6580 case VNID_SPK: 6581 /* follow shared_out tlv */ 6582 nid = spec->shared_out_nid; 6583 scoped_guard(mutex, &codec->control_mutex) { 6584 pval = kcontrol->private_value; 6585 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6586 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6587 kcontrol->private_value = pval; 6588 } 6589 break; 6590 case VNID_MIC: 6591 /* follow shared_mic tlv */ 6592 nid = spec->shared_mic_nid; 6593 scoped_guard(mutex, &codec->control_mutex) { 6594 pval = kcontrol->private_value; 6595 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6596 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6597 kcontrol->private_value = pval; 6598 } 6599 break; 6600 default: 6601 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6602 } 6603 return err; 6604 } 6605 6606 /* Add volume slider control for effect level */ 6607 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6608 const char *pfx, int dir) 6609 { 6610 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6611 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6612 struct snd_kcontrol_new knew = 6613 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6614 6615 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 6616 6617 knew.tlv.c = NULL; 6618 6619 switch (nid) { 6620 case XBASS_XOVER: 6621 knew.info = ca0132_alt_xbass_xover_slider_info; 6622 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6623 knew.put = ca0132_alt_xbass_xover_slider_put; 6624 break; 6625 default: 6626 knew.info = ca0132_alt_effect_slider_info; 6627 knew.get = ca0132_alt_slider_ctl_get; 6628 knew.put = ca0132_alt_effect_slider_put; 6629 knew.private_value = 6630 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6631 break; 6632 } 6633 6634 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6635 } 6636 6637 /* 6638 * Added FX: prefix for the alternative codecs, because otherwise the surround 6639 * effect would conflict with the Surround sound volume control. Also seems more 6640 * clear as to what the switches do. Left alone for others. 6641 */ 6642 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6643 const char *pfx, int dir) 6644 { 6645 struct ca0132_spec *spec = codec->spec; 6646 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6647 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6648 struct snd_kcontrol_new knew = 6649 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6650 /* If using alt_controls, add FX: prefix. But, don't add FX: 6651 * prefix to OutFX or InFX enable controls. 6652 */ 6653 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) 6654 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 6655 else 6656 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 6657 6658 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6659 } 6660 6661 static int add_voicefx(struct hda_codec *codec) 6662 { 6663 struct snd_kcontrol_new knew = 6664 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6665 VOICEFX, 1, 0, HDA_INPUT); 6666 knew.info = ca0132_voicefx_info; 6667 knew.get = ca0132_voicefx_get; 6668 knew.put = ca0132_voicefx_put; 6669 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6670 } 6671 6672 /* Create the EQ Preset control */ 6673 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6674 { 6675 struct snd_kcontrol_new knew = 6676 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6677 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6678 knew.info = ca0132_alt_eq_preset_info; 6679 knew.get = ca0132_alt_eq_preset_get; 6680 knew.put = ca0132_alt_eq_preset_put; 6681 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6682 snd_ctl_new1(&knew, codec)); 6683 } 6684 6685 /* 6686 * Add enumerated control for the three different settings of the smart volume 6687 * output effect. Normal just uses the slider value, and loud and night are 6688 * their own things that ignore that value. 6689 */ 6690 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6691 { 6692 struct snd_kcontrol_new knew = 6693 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6694 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6695 knew.info = ca0132_alt_svm_setting_info; 6696 knew.get = ca0132_alt_svm_setting_get; 6697 knew.put = ca0132_alt_svm_setting_put; 6698 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6699 snd_ctl_new1(&knew, codec)); 6700 6701 } 6702 6703 /* 6704 * Create an Output Select enumerated control for codecs with surround 6705 * out capabilities. 6706 */ 6707 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6708 { 6709 struct snd_kcontrol_new knew = 6710 HDA_CODEC_MUTE_MONO("Output Select", 6711 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6712 knew.info = ca0132_alt_output_select_get_info; 6713 knew.get = ca0132_alt_output_select_get; 6714 knew.put = ca0132_alt_output_select_put; 6715 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6716 snd_ctl_new1(&knew, codec)); 6717 } 6718 6719 /* 6720 * Add a control for selecting channel count on speaker output. Setting this 6721 * allows the DSP to do bass redirection and channel upmixing on surround 6722 * configurations. 6723 */ 6724 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec) 6725 { 6726 struct snd_kcontrol_new knew = 6727 HDA_CODEC_MUTE_MONO("Surround Channel Config", 6728 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT); 6729 knew.info = ca0132_alt_speaker_channel_cfg_get_info; 6730 knew.get = ca0132_alt_speaker_channel_cfg_get; 6731 knew.put = ca0132_alt_speaker_channel_cfg_put; 6732 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM, 6733 snd_ctl_new1(&knew, codec)); 6734 } 6735 6736 /* 6737 * Full range front stereo and rear surround switches. When these are set to 6738 * full range, the lower frequencies from these channels are no longer 6739 * redirected to the LFE channel. 6740 */ 6741 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec) 6742 { 6743 struct snd_kcontrol_new knew = 6744 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers", 6745 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT); 6746 6747 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT, 6748 snd_ctl_new1(&knew, codec)); 6749 } 6750 6751 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec) 6752 { 6753 struct snd_kcontrol_new knew = 6754 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers", 6755 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT); 6756 6757 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR, 6758 snd_ctl_new1(&knew, codec)); 6759 } 6760 6761 /* 6762 * Bass redirection redirects audio below the crossover frequency to the LFE 6763 * channel on speakers that are set as not being full-range. On configurations 6764 * without an LFE channel, it does nothing. Bass redirection seems to be the 6765 * replacement for X-Bass on configurations with an LFE channel. 6766 */ 6767 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec) 6768 { 6769 const char *namestr = "Bass Redirection Crossover"; 6770 struct snd_kcontrol_new knew = 6771 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0, 6772 HDA_OUTPUT); 6773 6774 knew.tlv.c = NULL; 6775 knew.info = ca0132_alt_xbass_xover_slider_info; 6776 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6777 knew.put = ca0132_alt_xbass_xover_slider_put; 6778 6779 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER, 6780 snd_ctl_new1(&knew, codec)); 6781 } 6782 6783 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec) 6784 { 6785 const char *namestr = "Bass Redirection"; 6786 struct snd_kcontrol_new knew = 6787 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1, 6788 HDA_OUTPUT); 6789 6790 return snd_hda_ctl_add(codec, BASS_REDIRECTION, 6791 snd_ctl_new1(&knew, codec)); 6792 } 6793 6794 /* 6795 * Create an Input Source enumerated control for the alternate ca0132 codecs 6796 * because the front microphone has no auto-detect, and Line-in has to be set 6797 * somehow. 6798 */ 6799 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6800 { 6801 struct snd_kcontrol_new knew = 6802 HDA_CODEC_MUTE_MONO("Input Source", 6803 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6804 knew.info = ca0132_alt_input_source_info; 6805 knew.get = ca0132_alt_input_source_get; 6806 knew.put = ca0132_alt_input_source_put; 6807 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6808 snd_ctl_new1(&knew, codec)); 6809 } 6810 6811 /* 6812 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6813 * more control than the original mic boost, which is either full 30dB or off. 6814 */ 6815 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6816 { 6817 struct snd_kcontrol_new knew = 6818 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6819 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6820 knew.info = ca0132_alt_mic_boost_info; 6821 knew.get = ca0132_alt_mic_boost_get; 6822 knew.put = ca0132_alt_mic_boost_put; 6823 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6824 snd_ctl_new1(&knew, codec)); 6825 6826 } 6827 6828 /* 6829 * Add headphone gain enumerated control for the AE-5. This switches between 6830 * three modes, low, medium, and high. When non-headphone outputs are selected, 6831 * it is automatically set to high. This is the same behavior as Windows. 6832 */ 6833 static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6834 { 6835 struct snd_kcontrol_new knew = 6836 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6837 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6838 knew.info = ae5_headphone_gain_info; 6839 knew.get = ae5_headphone_gain_get; 6840 knew.put = ae5_headphone_gain_put; 6841 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6842 snd_ctl_new1(&knew, codec)); 6843 } 6844 6845 /* 6846 * Add sound filter enumerated control for the AE-5. This adds three different 6847 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6848 * read into it, it changes the DAC's interpolation filter. 6849 */ 6850 static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6851 { 6852 struct snd_kcontrol_new knew = 6853 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6854 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6855 knew.info = ae5_sound_filter_info; 6856 knew.get = ae5_sound_filter_get; 6857 knew.put = ae5_sound_filter_put; 6858 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6859 snd_ctl_new1(&knew, codec)); 6860 } 6861 6862 static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6863 { 6864 struct snd_kcontrol_new knew = 6865 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6866 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6867 6868 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6869 snd_ctl_new1(&knew, codec)); 6870 } 6871 6872 /* 6873 * Need to create follower controls for the alternate codecs that have surround 6874 * capabilities. 6875 */ 6876 static const char * const ca0132_alt_follower_pfxs[] = { 6877 "Front", "Surround", "Center", "LFE", NULL, 6878 }; 6879 6880 /* 6881 * Also need special channel map, because the default one is incorrect. 6882 * I think this has to do with the pin for rear surround being 0x11, 6883 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6884 */ 6885 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6886 { .channels = 2, 6887 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6888 { .channels = 4, 6889 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6890 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6891 { .channels = 6, 6892 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6893 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6894 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6895 { } 6896 }; 6897 6898 /* Add the correct chmap for streams with 6 channels. */ 6899 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6900 { 6901 int err = 0; 6902 struct hda_pcm *pcm; 6903 6904 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6905 struct hda_pcm_stream *hinfo = 6906 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6907 struct snd_pcm_chmap *chmap; 6908 const struct snd_pcm_chmap_elem *elem; 6909 6910 elem = ca0132_alt_chmaps; 6911 if (hinfo->channels_max == 6) { 6912 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6913 SNDRV_PCM_STREAM_PLAYBACK, 6914 elem, hinfo->channels_max, 0, &chmap); 6915 if (err < 0) 6916 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6917 } 6918 } 6919 } 6920 6921 /* 6922 * When changing Node IDs for Mixer Controls below, make sure to update 6923 * Node IDs in ca0132_config() as well. 6924 */ 6925 static const struct snd_kcontrol_new ca0132_mixer[] = { 6926 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6927 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6928 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6929 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6930 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6931 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6932 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6933 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6934 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6935 0x12, 1, HDA_INPUT), 6936 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6937 VNID_HP_SEL, 1, HDA_OUTPUT), 6938 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6939 VNID_AMIC1_SEL, 1, HDA_INPUT), 6940 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6941 VNID_HP_ASEL, 1, HDA_OUTPUT), 6942 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6943 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6944 { } /* end */ 6945 }; 6946 6947 /* 6948 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6949 * surround controls. Also sets both the Front Playback and Capture Volume 6950 * controls to alt so they set the DSP's decibel level. 6951 */ 6952 static const struct snd_kcontrol_new desktop_mixer[] = { 6953 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6954 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6955 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6956 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6957 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6958 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6959 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6960 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6961 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 6962 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6963 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6964 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6965 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6966 VNID_HP_ASEL, 1, HDA_OUTPUT), 6967 { } /* end */ 6968 }; 6969 6970 /* 6971 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 6972 * because it doesn't set decibel levels for the DSP for capture. 6973 */ 6974 static const struct snd_kcontrol_new r3di_mixer[] = { 6975 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6976 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6977 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6978 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6979 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6980 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6981 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6982 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6983 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6984 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6985 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6986 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6987 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6988 VNID_HP_ASEL, 1, HDA_OUTPUT), 6989 { } /* end */ 6990 }; 6991 6992 static int ca0132_build_controls(struct hda_codec *codec) 6993 { 6994 struct ca0132_spec *spec = codec->spec; 6995 int i, num_fx, num_sliders; 6996 int err = 0; 6997 6998 /* Add Mixer controls */ 6999 for (i = 0; i < spec->num_mixers; i++) { 7000 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 7001 if (err < 0) 7002 return err; 7003 } 7004 /* Setup vmaster with surround followers for desktop ca0132 devices */ 7005 if (ca0132_use_alt_functions(spec)) { 7006 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 7007 spec->tlv); 7008 snd_hda_add_vmaster(codec, "Master Playback Volume", 7009 spec->tlv, ca0132_alt_follower_pfxs, 7010 "Playback Volume", 0); 7011 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 7012 NULL, ca0132_alt_follower_pfxs, 7013 "Playback Switch", 7014 true, 0, &spec->vmaster_mute.sw_kctl); 7015 if (err < 0) 7016 return err; 7017 } 7018 7019 /* Add in and out effects controls. 7020 * VoiceFX, PE and CrystalVoice are added separately. 7021 */ 7022 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 7023 for (i = 0; i < num_fx; i++) { 7024 /* Desktop cards break if Echo Cancellation is used. */ 7025 if (ca0132_use_pci_mmio(spec)) { 7026 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 7027 OUT_EFFECTS_COUNT)) 7028 continue; 7029 } 7030 7031 err = add_fx_switch(codec, ca0132_effects[i].nid, 7032 ca0132_effects[i].name, 7033 ca0132_effects[i].direct); 7034 if (err < 0) 7035 return err; 7036 } 7037 /* 7038 * If codec has use_alt_controls set to true, add effect level sliders, 7039 * EQ presets, and Smart Volume presets. Also, change names to add FX 7040 * prefix, and change PlayEnhancement and CrystalVoice to match. 7041 */ 7042 if (ca0132_use_alt_controls(spec)) { 7043 err = ca0132_alt_add_svm_enum(codec); 7044 if (err < 0) 7045 return err; 7046 7047 err = add_ca0132_alt_eq_presets(codec); 7048 if (err < 0) 7049 return err; 7050 7051 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7052 "Enable OutFX", 0); 7053 if (err < 0) 7054 return err; 7055 7056 err = add_fx_switch(codec, CRYSTAL_VOICE, 7057 "Enable InFX", 1); 7058 if (err < 0) 7059 return err; 7060 7061 num_sliders = OUT_EFFECTS_COUNT - 1; 7062 for (i = 0; i < num_sliders; i++) { 7063 err = ca0132_alt_add_effect_slider(codec, 7064 ca0132_effects[i].nid, 7065 ca0132_effects[i].name, 7066 ca0132_effects[i].direct); 7067 if (err < 0) 7068 return err; 7069 } 7070 7071 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 7072 "X-Bass Crossover", EFX_DIR_OUT); 7073 7074 if (err < 0) 7075 return err; 7076 } else { 7077 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 7078 "PlayEnhancement", 0); 7079 if (err < 0) 7080 return err; 7081 7082 err = add_fx_switch(codec, CRYSTAL_VOICE, 7083 "CrystalVoice", 1); 7084 if (err < 0) 7085 return err; 7086 } 7087 err = add_voicefx(codec); 7088 if (err < 0) 7089 return err; 7090 7091 /* 7092 * If the codec uses alt_functions, you need the enumerated controls 7093 * to select the new outputs and inputs, plus add the new mic boost 7094 * setting control. 7095 */ 7096 if (ca0132_use_alt_functions(spec)) { 7097 err = ca0132_alt_add_output_enum(codec); 7098 if (err < 0) 7099 return err; 7100 err = ca0132_alt_add_speaker_channel_cfg_enum(codec); 7101 if (err < 0) 7102 return err; 7103 err = ca0132_alt_add_front_full_range_switch(codec); 7104 if (err < 0) 7105 return err; 7106 err = ca0132_alt_add_rear_full_range_switch(codec); 7107 if (err < 0) 7108 return err; 7109 err = ca0132_alt_add_bass_redirection_crossover(codec); 7110 if (err < 0) 7111 return err; 7112 err = ca0132_alt_add_bass_redirection_switch(codec); 7113 if (err < 0) 7114 return err; 7115 err = ca0132_alt_add_mic_boost_enum(codec); 7116 if (err < 0) 7117 return err; 7118 /* 7119 * ZxR only has microphone input, there is no front panel 7120 * header on the card, and aux-in is handled by the DBPro board. 7121 */ 7122 if (ca0132_quirk(spec) != QUIRK_ZXR) { 7123 err = ca0132_alt_add_input_enum(codec); 7124 if (err < 0) 7125 return err; 7126 } 7127 } 7128 7129 switch (ca0132_quirk(spec)) { 7130 case QUIRK_AE5: 7131 case QUIRK_AE7: 7132 err = ae5_add_headphone_gain_enum(codec); 7133 if (err < 0) 7134 return err; 7135 err = ae5_add_sound_filter_enum(codec); 7136 if (err < 0) 7137 return err; 7138 break; 7139 case QUIRK_ZXR: 7140 err = zxr_add_headphone_gain_switch(codec); 7141 if (err < 0) 7142 return err; 7143 break; 7144 default: 7145 break; 7146 } 7147 7148 #ifdef ENABLE_TUNING_CONTROLS 7149 add_tuning_ctls(codec); 7150 #endif 7151 7152 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 7153 if (err < 0) 7154 return err; 7155 7156 if (spec->dig_out) { 7157 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7158 spec->dig_out); 7159 if (err < 0) 7160 return err; 7161 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 7162 if (err < 0) 7163 return err; 7164 /* spec->multiout.share_spdif = 1; */ 7165 } 7166 7167 if (spec->dig_in) { 7168 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7169 if (err < 0) 7170 return err; 7171 } 7172 7173 if (ca0132_use_alt_functions(spec)) 7174 ca0132_alt_add_chmap_ctls(codec); 7175 7176 return 0; 7177 } 7178 7179 static int dbpro_build_controls(struct hda_codec *codec) 7180 { 7181 struct ca0132_spec *spec = codec->spec; 7182 int err = 0; 7183 7184 if (spec->dig_out) { 7185 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 7186 spec->dig_out); 7187 if (err < 0) 7188 return err; 7189 } 7190 7191 if (spec->dig_in) { 7192 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 7193 if (err < 0) 7194 return err; 7195 } 7196 7197 return 0; 7198 } 7199 7200 /* 7201 * PCM 7202 */ 7203 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 7204 .substreams = 1, 7205 .channels_min = 2, 7206 .channels_max = 6, 7207 .ops = { 7208 .prepare = ca0132_playback_pcm_prepare, 7209 .cleanup = ca0132_playback_pcm_cleanup, 7210 .get_delay = ca0132_playback_pcm_delay, 7211 }, 7212 }; 7213 7214 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 7215 .substreams = 1, 7216 .channels_min = 2, 7217 .channels_max = 2, 7218 .ops = { 7219 .prepare = ca0132_capture_pcm_prepare, 7220 .cleanup = ca0132_capture_pcm_cleanup, 7221 .get_delay = ca0132_capture_pcm_delay, 7222 }, 7223 }; 7224 7225 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 7226 .substreams = 1, 7227 .channels_min = 2, 7228 .channels_max = 2, 7229 .ops = { 7230 .open = ca0132_dig_playback_pcm_open, 7231 .close = ca0132_dig_playback_pcm_close, 7232 .prepare = ca0132_dig_playback_pcm_prepare, 7233 .cleanup = ca0132_dig_playback_pcm_cleanup 7234 }, 7235 }; 7236 7237 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 7238 .substreams = 1, 7239 .channels_min = 2, 7240 .channels_max = 2, 7241 }; 7242 7243 static int ca0132_build_pcms(struct hda_codec *codec) 7244 { 7245 struct ca0132_spec *spec = codec->spec; 7246 struct hda_pcm *info; 7247 7248 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 7249 if (!info) 7250 return -ENOMEM; 7251 if (ca0132_use_alt_functions(spec)) { 7252 info->own_chmap = true; 7253 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 7254 = ca0132_alt_chmaps; 7255 } 7256 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 7257 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 7258 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 7259 spec->multiout.max_channels; 7260 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7261 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7262 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7263 7264 /* With the DSP enabled, desktops don't use this ADC. */ 7265 if (!ca0132_use_alt_functions(spec)) { 7266 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 7267 if (!info) 7268 return -ENOMEM; 7269 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7270 ca0132_pcm_analog_capture; 7271 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7272 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 7273 } 7274 7275 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 7276 if (!info) 7277 return -ENOMEM; 7278 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7279 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7280 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 7281 7282 if (!spec->dig_out && !spec->dig_in) 7283 return 0; 7284 7285 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7286 if (!info) 7287 return -ENOMEM; 7288 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7289 if (spec->dig_out) { 7290 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7291 ca0132_pcm_digital_playback; 7292 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7293 } 7294 if (spec->dig_in) { 7295 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7296 ca0132_pcm_digital_capture; 7297 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7298 } 7299 7300 return 0; 7301 } 7302 7303 static int dbpro_build_pcms(struct hda_codec *codec) 7304 { 7305 struct ca0132_spec *spec = codec->spec; 7306 struct hda_pcm *info; 7307 7308 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 7309 if (!info) 7310 return -ENOMEM; 7311 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 7312 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 7313 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 7314 7315 7316 if (!spec->dig_out && !spec->dig_in) 7317 return 0; 7318 7319 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 7320 if (!info) 7321 return -ENOMEM; 7322 info->pcm_type = HDA_PCM_TYPE_SPDIF; 7323 if (spec->dig_out) { 7324 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 7325 ca0132_pcm_digital_playback; 7326 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 7327 } 7328 if (spec->dig_in) { 7329 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 7330 ca0132_pcm_digital_capture; 7331 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 7332 } 7333 7334 return 0; 7335 } 7336 7337 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 7338 { 7339 if (pin) { 7340 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 7341 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 7342 snd_hda_codec_write(codec, pin, 0, 7343 AC_VERB_SET_AMP_GAIN_MUTE, 7344 AMP_OUT_UNMUTE); 7345 } 7346 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 7347 snd_hda_codec_write(codec, dac, 0, 7348 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 7349 } 7350 7351 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 7352 { 7353 if (pin) { 7354 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 7355 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 7356 snd_hda_codec_write(codec, pin, 0, 7357 AC_VERB_SET_AMP_GAIN_MUTE, 7358 AMP_IN_UNMUTE(0)); 7359 } 7360 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 7361 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 7362 AMP_IN_UNMUTE(0)); 7363 7364 /* init to 0 dB and unmute. */ 7365 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7366 HDA_AMP_VOLMASK, 0x5a); 7367 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 7368 HDA_AMP_MUTE, 0); 7369 } 7370 } 7371 7372 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 7373 { 7374 unsigned int caps; 7375 7376 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 7377 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 7378 snd_hda_override_amp_caps(codec, nid, dir, caps); 7379 } 7380 7381 /* 7382 * Switch between Digital built-in mic and analog mic. 7383 */ 7384 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 7385 { 7386 struct ca0132_spec *spec = codec->spec; 7387 unsigned int tmp; 7388 u8 val; 7389 unsigned int oldval; 7390 7391 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 7392 7393 oldval = stop_mic1(codec); 7394 ca0132_set_vipsource(codec, 0); 7395 if (enable) { 7396 /* set DMic input as 2-ch */ 7397 tmp = FLOAT_TWO; 7398 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7399 7400 val = spec->dmic_ctl; 7401 val |= 0x80; 7402 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7403 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7404 7405 if (!(spec->dmic_ctl & 0x20)) 7406 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 7407 } else { 7408 /* set AMic input as mono */ 7409 tmp = FLOAT_ONE; 7410 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7411 7412 val = spec->dmic_ctl; 7413 /* clear bit7 and bit5 to disable dmic */ 7414 val &= 0x5f; 7415 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7416 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7417 7418 if (!(spec->dmic_ctl & 0x20)) 7419 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 7420 } 7421 ca0132_set_vipsource(codec, 1); 7422 resume_mic1(codec, oldval); 7423 } 7424 7425 /* 7426 * Initialization for Digital Mic. 7427 */ 7428 static void ca0132_init_dmic(struct hda_codec *codec) 7429 { 7430 struct ca0132_spec *spec = codec->spec; 7431 u8 val; 7432 7433 /* Setup Digital Mic here, but don't enable. 7434 * Enable based on jack detect. 7435 */ 7436 7437 /* MCLK uses MPIO1, set to enable. 7438 * Bit 2-0: MPIO select 7439 * Bit 3: set to disable 7440 * Bit 7-4: reserved 7441 */ 7442 val = 0x01; 7443 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7444 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 7445 7446 /* Data1 uses MPIO3. Data2 not use 7447 * Bit 2-0: Data1 MPIO select 7448 * Bit 3: set disable Data1 7449 * Bit 6-4: Data2 MPIO select 7450 * Bit 7: set disable Data2 7451 */ 7452 val = 0x83; 7453 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7454 VENDOR_CHIPIO_DMIC_PIN_SET, val); 7455 7456 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 7457 * Bit 3-0: Channel mask 7458 * Bit 4: set for 48KHz, clear for 32KHz 7459 * Bit 5: mode 7460 * Bit 6: set to select Data2, clear for Data1 7461 * Bit 7: set to enable DMic, clear for AMic 7462 */ 7463 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) 7464 val = 0x33; 7465 else 7466 val = 0x23; 7467 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 7468 spec->dmic_ctl = val; 7469 snd_hda_codec_write(codec, spec->input_pins[0], 0, 7470 VENDOR_CHIPIO_DMIC_CTL_SET, val); 7471 } 7472 7473 /* 7474 * Initialization for Analog Mic 2 7475 */ 7476 static void ca0132_init_analog_mic2(struct hda_codec *codec) 7477 { 7478 struct ca0132_spec *spec = codec->spec; 7479 7480 guard(mutex)(&spec->chipio_mutex); 7481 7482 chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00); 7483 chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00); 7484 } 7485 7486 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 7487 { 7488 struct ca0132_spec *spec = codec->spec; 7489 int i; 7490 7491 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 7492 snd_hda_codec_update_widgets(codec); 7493 7494 for (i = 0; i < spec->multiout.num_dacs; i++) 7495 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 7496 7497 for (i = 0; i < spec->num_outputs; i++) 7498 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 7499 7500 for (i = 0; i < spec->num_inputs; i++) { 7501 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 7502 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 7503 } 7504 } 7505 7506 7507 /* If there is an active channel for some reason, find it and free it. */ 7508 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec) 7509 { 7510 unsigned int i, tmp; 7511 int status; 7512 7513 /* Read active DSPDMAC channel register. */ 7514 status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp); 7515 if (status >= 0) { 7516 /* AND against 0xfff to get the active channel bits. */ 7517 tmp = tmp & 0xfff; 7518 7519 /* If there are no active channels, nothing to free. */ 7520 if (!tmp) 7521 return; 7522 } else { 7523 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n", 7524 __func__); 7525 return; 7526 } 7527 7528 /* 7529 * Check each DSP DMA channel for activity, and if the channel is 7530 * active, free it. 7531 */ 7532 for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) { 7533 if (dsp_is_dma_active(codec, i)) { 7534 status = dspio_free_dma_chan(codec, i); 7535 if (status < 0) 7536 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n", 7537 __func__, i); 7538 } 7539 } 7540 } 7541 7542 /* 7543 * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in 7544 * use, audio is no longer routed directly to the DAC/ADC from the HDA stream. 7545 * Instead, audio is now routed through the DSP's DMA controllers, which 7546 * the DSP is tasked with setting up itself. Through debugging, it seems the 7547 * cause of most of the no-audio on startup issues were due to improperly 7548 * configured DSP DMA channels. 7549 * 7550 * Normally, the DSP configures these the first time an HDA audio stream is 7551 * started post DSP firmware download. That is why creating a 'dummy' stream 7552 * worked in fixing the audio in some cases. This works most of the time, but 7553 * sometimes if a stream is started/stopped before the DSP can setup the DMA 7554 * configuration registers, it ends up in a broken state. Issues can also 7555 * arise if streams are started in an unusual order, i.e the audio output dma 7556 * channel being sandwiched between the mic1 and mic2 dma channels. 7557 * 7558 * The solution to this is to make sure that the DSP has no DMA channels 7559 * in use post DSP firmware download, and then to manually start each default 7560 * DSP stream that uses the DMA channels. These are 0x0c, the audio output 7561 * stream, 0x03, analog mic 1, and 0x04, analog mic 2. 7562 */ 7563 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec) 7564 { 7565 static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 }; 7566 struct ca0132_spec *spec = codec->spec; 7567 unsigned int i, tmp; 7568 7569 /* 7570 * Check if any of the default streams are active, and if they are, 7571 * stop them. 7572 */ 7573 scoped_guard(mutex, &spec->chipio_mutex) { 7574 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7575 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp); 7576 7577 if (tmp) { 7578 chipio_set_stream_control(codec, 7579 dsp_dma_stream_ids[i], 0); 7580 } 7581 } 7582 } 7583 7584 /* 7585 * If all DSP streams are inactive, there should be no active DSP DMA 7586 * channels. Check and make sure this is the case, and if it isn't, 7587 * free any active channels. 7588 */ 7589 ca0132_alt_free_active_dma_channels(codec); 7590 7591 guard(mutex)(&spec->chipio_mutex); 7592 7593 /* Make sure stream 0x0c is six channels. */ 7594 chipio_set_stream_channels(codec, 0x0c, 6); 7595 7596 for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) { 7597 chipio_set_stream_control(codec, 7598 dsp_dma_stream_ids[i], 1); 7599 7600 /* Give the DSP some time to setup the DMA channel. */ 7601 msleep(75); 7602 } 7603 } 7604 7605 /* 7606 * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio 7607 * router', where each entry represents a 48khz audio channel, with a format 7608 * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number 7609 * value. The 2-bit number value is seemingly 0 if inactive, 1 if active, 7610 * and 3 if it's using Sample Rate Converter ports. 7611 * An example is: 7612 * 0x0001f8c0 7613 * In this case, f8 is the destination, and c0 is the source. The number value 7614 * is 1. 7615 * This region of memory is normally managed internally by the 8051, where 7616 * the region of exram memory from 0x1477-0x1575 has each byte represent an 7617 * entry within the 0x190000 range, and when a range of entries is in use, the 7618 * ending value is overwritten with 0xff. 7619 * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO 7620 * streamID's, where each entry is a starting 0x190000 port offset. 7621 * 0x159d in exram is the same as 0x1578, except it contains the ending port 7622 * offset for the corresponding streamID. 7623 * 7624 * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by 7625 * the 8051, then manually overwritten to remap the ports to work with the 7626 * new DACs. 7627 * 7628 * Currently known portID's: 7629 * 0x00-0x1f: HDA audio stream input/output ports. 7630 * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to 7631 * have the lower-nibble set to 0x1, 0x2, and 0x9. 7632 * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned. 7633 * 0xe0-0xff: DAC/ADC audio input/output ports. 7634 * 7635 * Currently known streamID's: 7636 * 0x03: Mic1 ADC to DSP. 7637 * 0x04: Mic2 ADC to DSP. 7638 * 0x05: HDA node 0x02 audio stream to DSP. 7639 * 0x0f: DSP Mic exit to HDA node 0x07. 7640 * 0x0c: DSP processed audio to DACs. 7641 * 0x14: DAC0, front L/R. 7642 * 7643 * It is possible to route the HDA audio streams directly to the DAC and 7644 * bypass the DSP entirely, with the only downside being that since the DSP 7645 * does volume control, the only volume control you'll get is through PCM on 7646 * the PC side, in the same way volume is handled for optical out. This may be 7647 * useful for debugging. 7648 */ 7649 static void chipio_remap_stream(struct hda_codec *codec, 7650 const struct chipio_stream_remap_data *remap_data) 7651 { 7652 unsigned int i, stream_offset; 7653 7654 /* Get the starting port for the stream to be remapped. */ 7655 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7656 &stream_offset); 7657 7658 /* 7659 * Check if the stream's port value is 0xff, because the 8051 may not 7660 * have gotten around to setting up the stream yet. Wait until it's 7661 * setup to remap it's ports. 7662 */ 7663 if (stream_offset == 0xff) { 7664 for (i = 0; i < 5; i++) { 7665 msleep(25); 7666 7667 chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id, 7668 &stream_offset); 7669 7670 if (stream_offset != 0xff) 7671 break; 7672 } 7673 } 7674 7675 if (stream_offset == 0xff) { 7676 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n", 7677 __func__, remap_data->stream_id); 7678 return; 7679 } 7680 7681 /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */ 7682 stream_offset *= 0x04; 7683 stream_offset += 0x190000; 7684 7685 for (i = 0; i < remap_data->count; i++) { 7686 chipio_write_no_mutex(codec, 7687 stream_offset + remap_data->offset[i], 7688 remap_data->value[i]); 7689 } 7690 7691 /* Update stream map configuration. */ 7692 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 7693 } 7694 7695 /* 7696 * Default speaker tuning values setup for alternative codecs. 7697 */ 7698 static const unsigned int sbz_default_delay_values[] = { 7699 /* Non-zero values are floating point 0.000198. */ 7700 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000 7701 }; 7702 7703 static const unsigned int zxr_default_delay_values[] = { 7704 /* Non-zero values are floating point 0.000220. */ 7705 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd 7706 }; 7707 7708 static const unsigned int ae5_default_delay_values[] = { 7709 /* Non-zero values are floating point 0.000100. */ 7710 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717 7711 }; 7712 7713 /* 7714 * If we never change these, probably only need them on initialization. 7715 */ 7716 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec) 7717 { 7718 struct ca0132_spec *spec = codec->spec; 7719 unsigned int i, tmp, start_req, end_req; 7720 const unsigned int *values; 7721 7722 switch (ca0132_quirk(spec)) { 7723 case QUIRK_SBZ: 7724 values = sbz_default_delay_values; 7725 break; 7726 case QUIRK_ZXR: 7727 values = zxr_default_delay_values; 7728 break; 7729 case QUIRK_AE5: 7730 case QUIRK_AE7: 7731 values = ae5_default_delay_values; 7732 break; 7733 default: 7734 values = sbz_default_delay_values; 7735 break; 7736 } 7737 7738 tmp = FLOAT_ZERO; 7739 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp); 7740 7741 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL; 7742 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL; 7743 for (i = start_req; i < end_req + 1; i++) 7744 dspio_set_uint_param(codec, 0x96, i, tmp); 7745 7746 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT; 7747 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT; 7748 for (i = start_req; i < end_req + 1; i++) 7749 dspio_set_uint_param(codec, 0x96, i, tmp); 7750 7751 7752 for (i = 0; i < 6; i++) 7753 dspio_set_uint_param(codec, 0x96, 7754 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]); 7755 } 7756 7757 /* 7758 * Initialize mic for non-chromebook ca0132 implementations. 7759 */ 7760 static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 7761 { 7762 struct ca0132_spec *spec = codec->spec; 7763 unsigned int tmp; 7764 7765 /* Mic 1 Setup */ 7766 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7767 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7768 if (ca0132_quirk(spec) == QUIRK_R3DI) { 7769 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7770 tmp = FLOAT_ONE; 7771 } else 7772 tmp = FLOAT_THREE; 7773 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7774 7775 /* Mic 2 setup (not present on desktop cards) */ 7776 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 7777 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 7778 if (ca0132_quirk(spec) == QUIRK_R3DI) 7779 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 7780 tmp = FLOAT_ZERO; 7781 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7782 } 7783 7784 /* 7785 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 7786 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 7787 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 7788 * having an updated DAC, which changes the destination to that DAC. 7789 */ 7790 static void sbz_connect_streams(struct hda_codec *codec) 7791 { 7792 struct ca0132_spec *spec = codec->spec; 7793 7794 guard(mutex)(&spec->chipio_mutex); 7795 7796 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 7797 7798 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 7799 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 7800 7801 /* Setup stream 0x14 with it's source and destination points */ 7802 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 7803 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 7804 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 7805 chipio_set_stream_channels(codec, 0x14, 2); 7806 chipio_set_stream_control(codec, 0x14, 1); 7807 7808 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 7809 } 7810 7811 /* 7812 * Write data through ChipIO to setup proper stream destinations. 7813 * Not sure how it exactly works, but it seems to direct data 7814 * to different destinations. Example is f8 to c0, e0 to c0. 7815 * All I know is, if you don't set these, you get no sound. 7816 */ 7817 static void sbz_chipio_startup_data(struct hda_codec *codec) 7818 { 7819 const struct chipio_stream_remap_data *dsp_out_remap_data; 7820 struct ca0132_spec *spec = codec->spec; 7821 7822 guard(mutex)(&spec->chipio_mutex); 7823 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 7824 7825 /* Remap DAC0's output ports. */ 7826 chipio_remap_stream(codec, &stream_remap_data[0]); 7827 7828 /* Remap DSP audio output stream ports. */ 7829 switch (ca0132_quirk(spec)) { 7830 case QUIRK_SBZ: 7831 dsp_out_remap_data = &stream_remap_data[1]; 7832 break; 7833 7834 case QUIRK_ZXR: 7835 dsp_out_remap_data = &stream_remap_data[2]; 7836 break; 7837 7838 default: 7839 dsp_out_remap_data = NULL; 7840 break; 7841 } 7842 7843 if (dsp_out_remap_data) 7844 chipio_remap_stream(codec, dsp_out_remap_data); 7845 7846 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 7847 } 7848 7849 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7850 { 7851 struct ca0132_spec *spec = codec->spec; 7852 unsigned int tmp; 7853 7854 chipio_set_stream_control(codec, 0x03, 0); 7855 chipio_set_stream_control(codec, 0x04, 0); 7856 7857 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7858 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7859 7860 tmp = FLOAT_THREE; 7861 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7862 7863 chipio_set_stream_control(codec, 0x03, 1); 7864 chipio_set_stream_control(codec, 0x04, 1); 7865 7866 switch (ca0132_quirk(spec)) { 7867 case QUIRK_SBZ: 7868 chipio_write(codec, 0x18b098, 0x0000000c); 7869 chipio_write(codec, 0x18b09C, 0x0000000c); 7870 break; 7871 case QUIRK_AE5: 7872 chipio_write(codec, 0x18b098, 0x0000000c); 7873 chipio_write(codec, 0x18b09c, 0x0000004c); 7874 break; 7875 default: 7876 break; 7877 } 7878 } 7879 7880 static void ae5_post_dsp_register_set(struct hda_codec *codec) 7881 { 7882 struct ca0132_spec *spec = codec->spec; 7883 7884 chipio_8051_write_direct(codec, 0x93, 0x10); 7885 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 7886 7887 writeb(0xff, spec->mem_base + 0x304); 7888 writeb(0xff, spec->mem_base + 0x304); 7889 writeb(0xff, spec->mem_base + 0x304); 7890 writeb(0xff, spec->mem_base + 0x304); 7891 writeb(0x00, spec->mem_base + 0x100); 7892 writeb(0xff, spec->mem_base + 0x304); 7893 writeb(0x00, spec->mem_base + 0x100); 7894 writeb(0xff, spec->mem_base + 0x304); 7895 writeb(0x00, spec->mem_base + 0x100); 7896 writeb(0xff, spec->mem_base + 0x304); 7897 writeb(0x00, spec->mem_base + 0x100); 7898 writeb(0xff, spec->mem_base + 0x304); 7899 7900 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7901 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7902 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7903 } 7904 7905 static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7906 { 7907 /* 7908 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7909 * which seems to be 'multichannel'. This is also mentioned in the 7910 * AE-5's registry values in Windows. 7911 */ 7912 chipio_set_control_param(codec, 3, 0); 7913 /* 7914 * I believe ASI is 'audio serial interface' and that it's used to 7915 * change colors on the external LED strip connected to the AE-5. 7916 */ 7917 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7918 7919 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7920 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7921 7922 chipio_8051_write_exram(codec, 0xfa92, 0x22); 7923 } 7924 7925 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7926 { 7927 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 7928 chipio_8051_write_pll_pmu(codec, 0x45, 0xcc); 7929 chipio_8051_write_pll_pmu(codec, 0x40, 0xcb); 7930 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 7931 chipio_8051_write_pll_pmu(codec, 0x51, 0x8d); 7932 } 7933 7934 static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7935 { 7936 struct ca0132_spec *spec = codec->spec; 7937 7938 guard(mutex)(&spec->chipio_mutex); 7939 7940 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7941 7942 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7943 7944 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 7945 7946 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 7947 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7948 chipio_set_stream_channels(codec, 0x18, 6); 7949 chipio_set_stream_control(codec, 0x18, 1); 7950 7951 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7952 7953 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 7954 7955 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 7956 } 7957 7958 static void ae5_post_dsp_startup_data(struct hda_codec *codec) 7959 { 7960 struct ca0132_spec *spec = codec->spec; 7961 7962 guard(mutex)(&spec->chipio_mutex); 7963 7964 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 7965 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 7966 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 7967 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 7968 7969 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7970 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 7971 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 7972 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 7973 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 7974 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7975 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7976 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7977 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7978 ca0113_mmio_gpio_set(codec, 0, true); 7979 ca0113_mmio_gpio_set(codec, 1, true); 7980 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 7981 7982 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 7983 7984 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7985 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7986 } 7987 7988 static void ae7_post_dsp_setup_ports(struct hda_codec *codec) 7989 { 7990 struct ca0132_spec *spec = codec->spec; 7991 7992 guard(mutex)(&spec->chipio_mutex); 7993 7994 /* Seems to share the same port remapping as the SBZ. */ 7995 chipio_remap_stream(codec, &stream_remap_data[1]); 7996 7997 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 7998 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40); 7999 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00); 8000 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00); 8001 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff); 8002 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff); 8003 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff); 8004 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f); 8005 } 8006 8007 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec) 8008 { 8009 struct ca0132_spec *spec = codec->spec; 8010 8011 guard(mutex)(&spec->chipio_mutex); 8012 8013 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 8014 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8015 8016 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 8017 8018 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8019 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8020 8021 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8022 chipio_set_stream_channels(codec, 0x18, 6); 8023 chipio_set_stream_control(codec, 0x18, 1); 8024 8025 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 8026 } 8027 8028 static void ae7_post_dsp_pll_setup(struct hda_codec *codec) 8029 { 8030 static const unsigned int addr[] = { 8031 0x41, 0x45, 0x40, 0x43, 0x51 8032 }; 8033 static const unsigned int data[] = { 8034 0xc8, 0xcc, 0xcb, 0xc7, 0x8d 8035 }; 8036 unsigned int i; 8037 8038 for (i = 0; i < ARRAY_SIZE(addr); i++) 8039 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]); 8040 } 8041 8042 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec) 8043 { 8044 struct ca0132_spec *spec = codec->spec; 8045 static const unsigned int target[] = { 8046 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14 8047 }; 8048 static const unsigned int data[] = { 8049 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f 8050 }; 8051 unsigned int i; 8052 8053 guard(mutex)(&spec->chipio_mutex); 8054 8055 chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7); 8056 8057 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 8058 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 8059 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 8060 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 8061 8062 ae7_post_dsp_pll_setup(codec); 8063 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8064 8065 for (i = 0; i < ARRAY_SIZE(target); i++) 8066 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]); 8067 8068 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8069 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8070 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8071 8072 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56); 8073 chipio_set_stream_channels(codec, 0x21, 2); 8074 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000); 8075 8076 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09); 8077 /* 8078 * In the 8051's memory, this param is referred to as 'n2sid', which I 8079 * believe is 'node to streamID'. It seems to be a way to assign a 8080 * stream to a given HDA node. 8081 */ 8082 chipio_set_control_param_no_mutex(codec, 0x20, 0x21); 8083 8084 chipio_write_no_mutex(codec, 0x18b038, 0x00000088); 8085 8086 /* 8087 * Now, at this point on Windows, an actual stream is setup and 8088 * seemingly sends data to the HDA node 0x09, which is the digital 8089 * audio input node. This is left out here, because obviously I don't 8090 * know what data is being sent. Interestingly, the AE-5 seems to go 8091 * through the motions of getting here and never actually takes this 8092 * step, but the AE-7 does. 8093 */ 8094 8095 ca0113_mmio_gpio_set(codec, 0, 1); 8096 ca0113_mmio_gpio_set(codec, 1, 1); 8097 8098 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8099 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000); 8100 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 8101 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 8102 8103 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00); 8104 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0); 8105 8106 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 8107 chipio_set_stream_channels(codec, 0x18, 6); 8108 8109 /* 8110 * Runs again, this has been repeated a few times, but I'm just 8111 * following what the Windows driver does. 8112 */ 8113 ae7_post_dsp_pll_setup(codec); 8114 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 8115 } 8116 8117 /* 8118 * The Windows driver has commands that seem to setup ASI, which I believe to 8119 * be some sort of audio serial interface. My current speculation is that it's 8120 * related to communicating with the new DAC. 8121 */ 8122 static void ae7_post_dsp_asi_setup(struct hda_codec *codec) 8123 { 8124 chipio_8051_write_direct(codec, 0x93, 0x10); 8125 8126 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 8127 8128 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8129 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8130 8131 chipio_set_control_param(codec, 3, 3); 8132 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 8133 8134 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 8135 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8136 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00); 8137 8138 chipio_8051_write_exram(codec, 0xfa92, 0x22); 8139 8140 ae7_post_dsp_pll_setup(codec); 8141 ae7_post_dsp_asi_stream_setup(codec); 8142 8143 chipio_8051_write_pll_pmu(codec, 0x43, 0xc7); 8144 8145 ae7_post_dsp_asi_setup_ports(codec); 8146 } 8147 8148 /* 8149 * Setup default parameters for DSP 8150 */ 8151 static void ca0132_setup_defaults(struct hda_codec *codec) 8152 { 8153 struct ca0132_spec *spec = codec->spec; 8154 unsigned int tmp; 8155 int num_fx; 8156 int idx, i; 8157 8158 if (spec->dsp_state != DSP_DOWNLOADED) 8159 return; 8160 8161 /* out, in effects + voicefx */ 8162 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8163 for (idx = 0; idx < num_fx; idx++) { 8164 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8165 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 8166 ca0132_effects[idx].reqs[i], 8167 ca0132_effects[idx].def_vals[i]); 8168 } 8169 } 8170 8171 /*remove DSP headroom*/ 8172 tmp = FLOAT_ZERO; 8173 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8174 8175 /*set speaker EQ bypass attenuation*/ 8176 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 8177 8178 /* set AMic1 and AMic2 as mono mic */ 8179 tmp = FLOAT_ONE; 8180 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 8181 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 8182 8183 /* set AMic1 as CrystalVoice input */ 8184 tmp = FLOAT_ONE; 8185 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 8186 8187 /* set WUH source */ 8188 tmp = FLOAT_TWO; 8189 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8190 } 8191 8192 /* 8193 * Setup default parameters for Recon3D/Recon3Di DSP. 8194 */ 8195 8196 static void r3d_setup_defaults(struct hda_codec *codec) 8197 { 8198 struct ca0132_spec *spec = codec->spec; 8199 unsigned int tmp; 8200 int num_fx; 8201 int idx, i; 8202 8203 if (spec->dsp_state != DSP_DOWNLOADED) 8204 return; 8205 8206 ca0132_alt_init_analog_mics(codec); 8207 ca0132_alt_start_dsp_audio_streams(codec); 8208 8209 /*remove DSP headroom*/ 8210 tmp = FLOAT_ZERO; 8211 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8212 8213 /* set WUH source */ 8214 tmp = FLOAT_TWO; 8215 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8216 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8217 8218 /* Set speaker source? */ 8219 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8220 8221 if (ca0132_quirk(spec) == QUIRK_R3DI) 8222 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 8223 8224 /* Disable mute on Center/LFE. */ 8225 if (ca0132_quirk(spec) == QUIRK_R3D) { 8226 ca0113_mmio_gpio_set(codec, 2, false); 8227 ca0113_mmio_gpio_set(codec, 4, true); 8228 } 8229 8230 /* Setup effect defaults */ 8231 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8232 for (idx = 0; idx < num_fx; idx++) { 8233 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8234 dspio_set_uint_param(codec, 8235 ca0132_effects[idx].mid, 8236 ca0132_effects[idx].reqs[i], 8237 ca0132_effects[idx].def_vals[i]); 8238 } 8239 } 8240 } 8241 8242 /* 8243 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 8244 * than the Chromebook setup. 8245 */ 8246 static void sbz_setup_defaults(struct hda_codec *codec) 8247 { 8248 struct ca0132_spec *spec = codec->spec; 8249 unsigned int tmp; 8250 int num_fx; 8251 int idx, i; 8252 8253 if (spec->dsp_state != DSP_DOWNLOADED) 8254 return; 8255 8256 ca0132_alt_init_analog_mics(codec); 8257 ca0132_alt_start_dsp_audio_streams(codec); 8258 sbz_connect_streams(codec); 8259 sbz_chipio_startup_data(codec); 8260 8261 /* 8262 * Sets internal input loopback to off, used to have a switch to 8263 * enable input loopback, but turned out to be way too buggy. 8264 */ 8265 tmp = FLOAT_ONE; 8266 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8267 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8268 8269 /*remove DSP headroom*/ 8270 tmp = FLOAT_ZERO; 8271 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8272 8273 /* set WUH source */ 8274 tmp = FLOAT_TWO; 8275 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8276 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8277 8278 /* Set speaker source? */ 8279 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8280 8281 ca0132_alt_dsp_initial_mic_setup(codec); 8282 8283 /* out, in effects + voicefx */ 8284 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8285 for (idx = 0; idx < num_fx; idx++) { 8286 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8287 dspio_set_uint_param(codec, 8288 ca0132_effects[idx].mid, 8289 ca0132_effects[idx].reqs[i], 8290 ca0132_effects[idx].def_vals[i]); 8291 } 8292 } 8293 8294 ca0132_alt_init_speaker_tuning(codec); 8295 } 8296 8297 /* 8298 * Setup default parameters for the Sound BlasterX AE-5 DSP. 8299 */ 8300 static void ae5_setup_defaults(struct hda_codec *codec) 8301 { 8302 struct ca0132_spec *spec = codec->spec; 8303 unsigned int tmp; 8304 int num_fx; 8305 int idx, i; 8306 8307 if (spec->dsp_state != DSP_DOWNLOADED) 8308 return; 8309 8310 ca0132_alt_init_analog_mics(codec); 8311 ca0132_alt_start_dsp_audio_streams(codec); 8312 8313 /* New, unknown SCP req's */ 8314 tmp = FLOAT_ZERO; 8315 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 8316 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 8317 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8318 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8319 8320 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8321 ca0113_mmio_gpio_set(codec, 0, false); 8322 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8323 8324 /* Internal loopback off */ 8325 tmp = FLOAT_ONE; 8326 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8327 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8328 8329 /*remove DSP headroom*/ 8330 tmp = FLOAT_ZERO; 8331 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8332 8333 /* set WUH source */ 8334 tmp = FLOAT_TWO; 8335 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8336 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8337 8338 /* Set speaker source? */ 8339 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8340 8341 ca0132_alt_dsp_initial_mic_setup(codec); 8342 ae5_post_dsp_register_set(codec); 8343 ae5_post_dsp_param_setup(codec); 8344 ae5_post_dsp_pll_setup(codec); 8345 ae5_post_dsp_stream_setup(codec); 8346 ae5_post_dsp_startup_data(codec); 8347 8348 /* out, in effects + voicefx */ 8349 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8350 for (idx = 0; idx < num_fx; idx++) { 8351 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8352 dspio_set_uint_param(codec, 8353 ca0132_effects[idx].mid, 8354 ca0132_effects[idx].reqs[i], 8355 ca0132_effects[idx].def_vals[i]); 8356 } 8357 } 8358 8359 ca0132_alt_init_speaker_tuning(codec); 8360 } 8361 8362 /* 8363 * Setup default parameters for the Sound Blaster AE-7 DSP. 8364 */ 8365 static void ae7_setup_defaults(struct hda_codec *codec) 8366 { 8367 struct ca0132_spec *spec = codec->spec; 8368 unsigned int tmp; 8369 int num_fx; 8370 int idx, i; 8371 8372 if (spec->dsp_state != DSP_DOWNLOADED) 8373 return; 8374 8375 ca0132_alt_init_analog_mics(codec); 8376 ca0132_alt_start_dsp_audio_streams(codec); 8377 ae7_post_dsp_setup_ports(codec); 8378 8379 tmp = FLOAT_ZERO; 8380 dspio_set_uint_param(codec, 0x96, 8381 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp); 8382 dspio_set_uint_param(codec, 0x96, 8383 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp); 8384 8385 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 8386 8387 /* New, unknown SCP req's */ 8388 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 8389 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 8390 8391 ca0113_mmio_gpio_set(codec, 0, false); 8392 8393 /* Internal loopback off */ 8394 tmp = FLOAT_ONE; 8395 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 8396 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 8397 8398 /*remove DSP headroom*/ 8399 tmp = FLOAT_ZERO; 8400 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 8401 8402 /* set WUH source */ 8403 tmp = FLOAT_TWO; 8404 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 8405 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8406 8407 /* Set speaker source? */ 8408 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 8409 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 8410 8411 /* 8412 * This is the second time we've called this, but this is seemingly 8413 * what Windows does. 8414 */ 8415 ca0132_alt_init_analog_mics(codec); 8416 8417 ae7_post_dsp_asi_setup(codec); 8418 8419 /* 8420 * Not sure why, but these are both set to 1. They're only set to 0 8421 * upon shutdown. 8422 */ 8423 ca0113_mmio_gpio_set(codec, 0, true); 8424 ca0113_mmio_gpio_set(codec, 1, true); 8425 8426 /* Volume control related. */ 8427 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04); 8428 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04); 8429 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80); 8430 8431 /* out, in effects + voicefx */ 8432 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 8433 for (idx = 0; idx < num_fx; idx++) { 8434 for (i = 0; i <= ca0132_effects[idx].params; i++) { 8435 dspio_set_uint_param(codec, 8436 ca0132_effects[idx].mid, 8437 ca0132_effects[idx].reqs[i], 8438 ca0132_effects[idx].def_vals[i]); 8439 } 8440 } 8441 8442 ca0132_alt_init_speaker_tuning(codec); 8443 } 8444 8445 /* 8446 * Initialization of flags in chip 8447 */ 8448 static void ca0132_init_flags(struct hda_codec *codec) 8449 { 8450 struct ca0132_spec *spec = codec->spec; 8451 8452 if (ca0132_use_alt_functions(spec)) { 8453 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 8454 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 8455 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 8456 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 8457 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 8458 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8459 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 8460 chipio_set_control_flag(codec, 8461 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8462 chipio_set_control_flag(codec, 8463 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 8464 } else { 8465 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8466 chipio_set_control_flag(codec, 8467 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 8468 chipio_set_control_flag(codec, 8469 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 8470 chipio_set_control_flag(codec, 8471 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 8472 chipio_set_control_flag(codec, 8473 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 8474 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 8475 } 8476 } 8477 8478 /* 8479 * Initialization of parameters in chip 8480 */ 8481 static void ca0132_init_params(struct hda_codec *codec) 8482 { 8483 struct ca0132_spec *spec = codec->spec; 8484 8485 if (ca0132_use_alt_functions(spec)) { 8486 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8487 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 8488 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 8489 chipio_set_control_param(codec, 0, 0); 8490 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 8491 } 8492 8493 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 8494 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 8495 } 8496 8497 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 8498 { 8499 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 8500 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 8501 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 8502 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 8503 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 8504 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 8505 8506 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 8507 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 8508 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 8509 } 8510 8511 static bool ca0132_download_dsp_images(struct hda_codec *codec) 8512 { 8513 bool dsp_loaded = false; 8514 struct ca0132_spec *spec = codec->spec; 8515 const struct dsp_image_seg *dsp_os_image; 8516 const struct firmware *fw_entry = NULL; 8517 /* 8518 * Alternate firmwares for different variants. The Recon3Di apparently 8519 * can use the default firmware, but I'll leave the option in case 8520 * it needs it again. 8521 */ 8522 switch (ca0132_quirk(spec)) { 8523 case QUIRK_SBZ: 8524 case QUIRK_R3D: 8525 case QUIRK_AE5: 8526 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 8527 codec->card->dev) != 0) 8528 codec_dbg(codec, "Desktop firmware not found."); 8529 else 8530 codec_dbg(codec, "Desktop firmware selected."); 8531 break; 8532 case QUIRK_R3DI: 8533 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 8534 codec->card->dev) != 0) 8535 codec_dbg(codec, "Recon3Di alt firmware not detected."); 8536 else 8537 codec_dbg(codec, "Recon3Di firmware selected."); 8538 break; 8539 default: 8540 break; 8541 } 8542 /* 8543 * Use default ctefx.bin if no alt firmware is detected, or if none 8544 * exists for your particular codec. 8545 */ 8546 if (!fw_entry) { 8547 codec_dbg(codec, "Default firmware selected."); 8548 if (request_firmware(&fw_entry, EFX_FILE, 8549 codec->card->dev) != 0) 8550 return false; 8551 } 8552 8553 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 8554 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 8555 codec_err(codec, "ca0132 DSP load image failed\n"); 8556 goto exit_download; 8557 } 8558 8559 dsp_loaded = dspload_wait_loaded(codec); 8560 8561 exit_download: 8562 release_firmware(fw_entry); 8563 8564 return dsp_loaded; 8565 } 8566 8567 static void ca0132_download_dsp(struct hda_codec *codec) 8568 { 8569 struct ca0132_spec *spec = codec->spec; 8570 8571 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 8572 return; /* NOP */ 8573 #endif 8574 8575 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 8576 return; /* don't retry failures */ 8577 8578 chipio_enable_clocks(codec); 8579 if (spec->dsp_state != DSP_DOWNLOADED) { 8580 spec->dsp_state = DSP_DOWNLOADING; 8581 8582 if (!ca0132_download_dsp_images(codec)) 8583 spec->dsp_state = DSP_DOWNLOAD_FAILED; 8584 else 8585 spec->dsp_state = DSP_DOWNLOADED; 8586 } 8587 8588 /* For codecs using alt functions, this is already done earlier */ 8589 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) 8590 ca0132_set_dsp_msr(codec, true); 8591 } 8592 8593 static void ca0132_process_dsp_response(struct hda_codec *codec, 8594 struct hda_jack_callback *callback) 8595 { 8596 struct ca0132_spec *spec = codec->spec; 8597 8598 codec_dbg(codec, "ca0132_process_dsp_response\n"); 8599 CLASS(snd_hda_power_pm, pm)(codec); 8600 if (spec->wait_scp) { 8601 if (dspio_get_response_data(codec) >= 0) 8602 spec->wait_scp = 0; 8603 } 8604 8605 dspio_clear_response_queue(codec); 8606 } 8607 8608 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8609 { 8610 struct ca0132_spec *spec = codec->spec; 8611 struct hda_jack_tbl *tbl; 8612 8613 /* Delay enabling the HP amp, to let the mic-detection 8614 * state machine run. 8615 */ 8616 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 8617 if (tbl) 8618 tbl->block_report = 1; 8619 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 8620 } 8621 8622 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 8623 { 8624 struct ca0132_spec *spec = codec->spec; 8625 8626 if (ca0132_use_alt_functions(spec)) 8627 ca0132_alt_select_in(codec); 8628 else 8629 ca0132_select_mic(codec); 8630 } 8631 8632 static void ca0132_setup_unsol(struct hda_codec *codec) 8633 { 8634 struct ca0132_spec *spec = codec->spec; 8635 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 8636 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 8637 amic_callback); 8638 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 8639 ca0132_process_dsp_response); 8640 /* Front headphone jack detection */ 8641 if (ca0132_use_alt_functions(spec)) 8642 snd_hda_jack_detect_enable_callback(codec, 8643 spec->unsol_tag_front_hp, hp_callback); 8644 } 8645 8646 /* 8647 * Verbs tables. 8648 */ 8649 8650 /* Sends before DSP download. */ 8651 static const struct hda_verb ca0132_base_init_verbs[] = { 8652 /*enable ct extension*/ 8653 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 8654 {} 8655 }; 8656 8657 /* Send at exit. */ 8658 static const struct hda_verb ca0132_base_exit_verbs[] = { 8659 /*set afg to D3*/ 8660 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 8661 /*disable ct extension*/ 8662 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 8663 {} 8664 }; 8665 8666 /* Other verbs tables. Sends after DSP download. */ 8667 8668 static const struct hda_verb ca0132_init_verbs0[] = { 8669 /* chip init verbs */ 8670 {0x15, 0x70D, 0xF0}, 8671 {0x15, 0x70E, 0xFE}, 8672 {0x15, 0x707, 0x75}, 8673 {0x15, 0x707, 0xD3}, 8674 {0x15, 0x707, 0x09}, 8675 {0x15, 0x707, 0x53}, 8676 {0x15, 0x707, 0xD4}, 8677 {0x15, 0x707, 0xEF}, 8678 {0x15, 0x707, 0x75}, 8679 {0x15, 0x707, 0xD3}, 8680 {0x15, 0x707, 0x09}, 8681 {0x15, 0x707, 0x02}, 8682 {0x15, 0x707, 0x37}, 8683 {0x15, 0x707, 0x78}, 8684 {0x15, 0x53C, 0xCE}, 8685 {0x15, 0x575, 0xC9}, 8686 {0x15, 0x53D, 0xCE}, 8687 {0x15, 0x5B7, 0xC9}, 8688 {0x15, 0x70D, 0xE8}, 8689 {0x15, 0x70E, 0xFE}, 8690 {0x15, 0x707, 0x02}, 8691 {0x15, 0x707, 0x68}, 8692 {0x15, 0x707, 0x62}, 8693 {0x15, 0x53A, 0xCE}, 8694 {0x15, 0x546, 0xC9}, 8695 {0x15, 0x53B, 0xCE}, 8696 {0x15, 0x5E8, 0xC9}, 8697 {} 8698 }; 8699 8700 /* Extra init verbs for desktop cards. */ 8701 static const struct hda_verb ca0132_init_verbs1[] = { 8702 {0x15, 0x70D, 0x20}, 8703 {0x15, 0x70E, 0x19}, 8704 {0x15, 0x707, 0x00}, 8705 {0x15, 0x539, 0xCE}, 8706 {0x15, 0x546, 0xC9}, 8707 {0x15, 0x70D, 0xB7}, 8708 {0x15, 0x70E, 0x09}, 8709 {0x15, 0x707, 0x10}, 8710 {0x15, 0x70D, 0xAF}, 8711 {0x15, 0x70E, 0x09}, 8712 {0x15, 0x707, 0x01}, 8713 {0x15, 0x707, 0x05}, 8714 {0x15, 0x70D, 0x73}, 8715 {0x15, 0x70E, 0x09}, 8716 {0x15, 0x707, 0x14}, 8717 {0x15, 0x6FF, 0xC4}, 8718 {} 8719 }; 8720 8721 static void ca0132_init_chip(struct hda_codec *codec) 8722 { 8723 struct ca0132_spec *spec = codec->spec; 8724 int num_fx; 8725 int i; 8726 unsigned int on; 8727 8728 mutex_init(&spec->chipio_mutex); 8729 8730 /* 8731 * The Windows driver always does this upon startup, which seems to 8732 * clear out any previous configuration. This should help issues where 8733 * a boot into Windows prior to a boot into Linux breaks things. Also, 8734 * Windows always sends the reset twice. 8735 */ 8736 if (ca0132_use_alt_functions(spec)) { 8737 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 8738 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2); 8739 8740 snd_hda_codec_write(codec, codec->core.afg, 0, 8741 AC_VERB_SET_CODEC_RESET, 0); 8742 snd_hda_codec_write(codec, codec->core.afg, 0, 8743 AC_VERB_SET_CODEC_RESET, 0); 8744 } 8745 8746 spec->cur_out_type = SPEAKER_OUT; 8747 if (!ca0132_use_alt_functions(spec)) 8748 spec->cur_mic_type = DIGITAL_MIC; 8749 else 8750 spec->cur_mic_type = REAR_MIC; 8751 8752 spec->cur_mic_boost = 0; 8753 8754 for (i = 0; i < VNODES_COUNT; i++) { 8755 spec->vnode_lvol[i] = 0x5a; 8756 spec->vnode_rvol[i] = 0x5a; 8757 spec->vnode_lswitch[i] = 0; 8758 spec->vnode_rswitch[i] = 0; 8759 } 8760 8761 /* 8762 * Default states for effects are in ca0132_effects[]. 8763 */ 8764 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 8765 for (i = 0; i < num_fx; i++) { 8766 on = (unsigned int)ca0132_effects[i].reqs[0]; 8767 spec->effects_switch[i] = on ? 1 : 0; 8768 } 8769 /* 8770 * Sets defaults for the effect slider controls, only for alternative 8771 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 8772 */ 8773 if (ca0132_use_alt_controls(spec)) { 8774 /* Set speakers to default to full range. */ 8775 spec->speaker_range_val[0] = 1; 8776 spec->speaker_range_val[1] = 1; 8777 8778 spec->xbass_xover_freq = 8; 8779 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 8780 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 8781 8782 spec->bass_redirect_xover_freq = 8; 8783 } 8784 8785 spec->voicefx_val = 0; 8786 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 8787 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 8788 8789 /* 8790 * The ZxR doesn't have a front panel header, and it's line-in is on 8791 * the daughter board. So, there is no input enum control, and we need 8792 * to make sure that spec->in_enum_val is set properly. 8793 */ 8794 if (ca0132_quirk(spec) == QUIRK_ZXR) 8795 spec->in_enum_val = REAR_MIC; 8796 8797 #ifdef ENABLE_TUNING_CONTROLS 8798 ca0132_init_tuning_defaults(codec); 8799 #endif 8800 } 8801 8802 /* 8803 * Recon3Di exit specific commands. 8804 */ 8805 /* prevents popping noise on shutdown */ 8806 static void r3di_gpio_shutdown(struct hda_codec *codec) 8807 { 8808 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 8809 } 8810 8811 /* 8812 * Sound Blaster Z exit specific commands. 8813 */ 8814 static void sbz_region2_exit(struct hda_codec *codec) 8815 { 8816 struct ca0132_spec *spec = codec->spec; 8817 unsigned int i; 8818 8819 for (i = 0; i < 4; i++) 8820 writeb(0x0, spec->mem_base + 0x100); 8821 for (i = 0; i < 8; i++) 8822 writeb(0xb3, spec->mem_base + 0x304); 8823 8824 ca0113_mmio_gpio_set(codec, 0, false); 8825 ca0113_mmio_gpio_set(codec, 1, false); 8826 ca0113_mmio_gpio_set(codec, 4, true); 8827 ca0113_mmio_gpio_set(codec, 5, false); 8828 ca0113_mmio_gpio_set(codec, 7, false); 8829 } 8830 8831 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 8832 { 8833 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 8834 unsigned int i; 8835 8836 snd_hda_codec_write(codec, 0x11, 0, 8837 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 8838 8839 for (i = 0; i < ARRAY_SIZE(pins); i++) 8840 snd_hda_codec_write(codec, pins[i], 0, 8841 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 8842 } 8843 8844 static void ca0132_clear_unsolicited(struct hda_codec *codec) 8845 { 8846 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 8847 unsigned int i; 8848 8849 for (i = 0; i < ARRAY_SIZE(pins); i++) { 8850 snd_hda_codec_write(codec, pins[i], 0, 8851 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 8852 } 8853 } 8854 8855 /* On shutdown, sends commands in sets of three */ 8856 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 8857 int mask, int data) 8858 { 8859 if (dir >= 0) 8860 snd_hda_codec_write(codec, 0x01, 0, 8861 AC_VERB_SET_GPIO_DIRECTION, dir); 8862 if (mask >= 0) 8863 snd_hda_codec_write(codec, 0x01, 0, 8864 AC_VERB_SET_GPIO_MASK, mask); 8865 8866 if (data >= 0) 8867 snd_hda_codec_write(codec, 0x01, 0, 8868 AC_VERB_SET_GPIO_DATA, data); 8869 } 8870 8871 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 8872 { 8873 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 8874 unsigned int i; 8875 8876 for (i = 0; i < ARRAY_SIZE(pins); i++) 8877 snd_hda_codec_write(codec, pins[i], 0, 8878 AC_VERB_SET_POWER_STATE, 0x03); 8879 } 8880 8881 static void sbz_exit_chip(struct hda_codec *codec) 8882 { 8883 chipio_set_stream_control(codec, 0x03, 0); 8884 chipio_set_stream_control(codec, 0x04, 0); 8885 8886 /* Mess with GPIO */ 8887 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 8888 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 8889 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 8890 8891 chipio_set_stream_control(codec, 0x14, 0); 8892 chipio_set_stream_control(codec, 0x0C, 0); 8893 8894 chipio_set_conn_rate(codec, 0x41, SR_192_000); 8895 chipio_set_conn_rate(codec, 0x91, SR_192_000); 8896 8897 chipio_write(codec, 0x18a020, 0x00000083); 8898 8899 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 8900 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 8901 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 8902 8903 chipio_set_stream_control(codec, 0x0C, 0); 8904 8905 chipio_set_control_param(codec, 0x0D, 0x24); 8906 8907 ca0132_clear_unsolicited(codec); 8908 sbz_set_pin_ctl_default(codec); 8909 8910 snd_hda_codec_write(codec, 0x0B, 0, 8911 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 8912 8913 sbz_region2_exit(codec); 8914 } 8915 8916 static void r3d_exit_chip(struct hda_codec *codec) 8917 { 8918 ca0132_clear_unsolicited(codec); 8919 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8920 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 8921 } 8922 8923 static void ae5_exit_chip(struct hda_codec *codec) 8924 { 8925 chipio_set_stream_control(codec, 0x03, 0); 8926 chipio_set_stream_control(codec, 0x04, 0); 8927 8928 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8929 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8930 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8931 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8932 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8933 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 8934 ca0113_mmio_gpio_set(codec, 0, false); 8935 ca0113_mmio_gpio_set(codec, 1, false); 8936 8937 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8938 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 8939 8940 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8941 8942 chipio_set_stream_control(codec, 0x18, 0); 8943 chipio_set_stream_control(codec, 0x0c, 0); 8944 8945 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 8946 } 8947 8948 static void ae7_exit_chip(struct hda_codec *codec) 8949 { 8950 chipio_set_stream_control(codec, 0x18, 0); 8951 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8); 8952 chipio_set_stream_channels(codec, 0x21, 0); 8953 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09); 8954 chipio_set_control_param(codec, 0x20, 0x01); 8955 8956 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 8957 8958 chipio_set_stream_control(codec, 0x18, 0); 8959 chipio_set_stream_control(codec, 0x0c, 0); 8960 8961 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 8962 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83); 8963 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 8964 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 8965 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00); 8966 ca0113_mmio_gpio_set(codec, 0, false); 8967 ca0113_mmio_gpio_set(codec, 1, false); 8968 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8969 8970 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8971 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 8972 } 8973 8974 static void zxr_exit_chip(struct hda_codec *codec) 8975 { 8976 chipio_set_stream_control(codec, 0x03, 0); 8977 chipio_set_stream_control(codec, 0x04, 0); 8978 chipio_set_stream_control(codec, 0x14, 0); 8979 chipio_set_stream_control(codec, 0x0C, 0); 8980 8981 chipio_set_conn_rate(codec, 0x41, SR_192_000); 8982 chipio_set_conn_rate(codec, 0x91, SR_192_000); 8983 8984 chipio_write(codec, 0x18a020, 0x00000083); 8985 8986 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 8987 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 8988 8989 ca0132_clear_unsolicited(codec); 8990 sbz_set_pin_ctl_default(codec); 8991 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 8992 8993 ca0113_mmio_gpio_set(codec, 5, false); 8994 ca0113_mmio_gpio_set(codec, 2, false); 8995 ca0113_mmio_gpio_set(codec, 3, false); 8996 ca0113_mmio_gpio_set(codec, 0, false); 8997 ca0113_mmio_gpio_set(codec, 4, true); 8998 ca0113_mmio_gpio_set(codec, 0, true); 8999 ca0113_mmio_gpio_set(codec, 5, true); 9000 ca0113_mmio_gpio_set(codec, 2, false); 9001 ca0113_mmio_gpio_set(codec, 3, false); 9002 } 9003 9004 static void ca0132_exit_chip(struct hda_codec *codec) 9005 { 9006 /* put any chip cleanup stuffs here. */ 9007 9008 if (dspload_is_loaded(codec)) 9009 dsp_reset(codec); 9010 } 9011 9012 /* 9013 * This fixes a problem that was hard to reproduce. Very rarely, I would 9014 * boot up, and there would be no sound, but the DSP indicated it had loaded 9015 * properly. I did a few memory dumps to see if anything was different, and 9016 * there were a few areas of memory uninitialized with a1a2a3a4. This function 9017 * checks if those areas are uninitialized, and if they are, it'll attempt to 9018 * reload the card 3 times. Usually it fixes by the second. 9019 */ 9020 static void sbz_dsp_startup_check(struct hda_codec *codec) 9021 { 9022 struct ca0132_spec *spec = codec->spec; 9023 unsigned int dsp_data_check[4]; 9024 unsigned int cur_address = 0x390; 9025 unsigned int i; 9026 unsigned int failure = 0; 9027 unsigned int reload = 3; 9028 9029 if (spec->startup_check_entered) 9030 return; 9031 9032 spec->startup_check_entered = true; 9033 9034 for (i = 0; i < 4; i++) { 9035 chipio_read(codec, cur_address, &dsp_data_check[i]); 9036 cur_address += 0x4; 9037 } 9038 for (i = 0; i < 4; i++) { 9039 if (dsp_data_check[i] == 0xa1a2a3a4) 9040 failure = 1; 9041 } 9042 9043 codec_dbg(codec, "Startup Check: %d ", failure); 9044 if (failure) 9045 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 9046 /* 9047 * While the failure condition is true, and we haven't reached our 9048 * three reload limit, continue trying to reload the driver and 9049 * fix the issue. 9050 */ 9051 while (failure && (reload != 0)) { 9052 codec_info(codec, "Reloading... Tries left: %d", reload); 9053 sbz_exit_chip(codec); 9054 spec->dsp_state = DSP_DOWNLOAD_INIT; 9055 snd_hda_codec_init(codec); 9056 failure = 0; 9057 for (i = 0; i < 4; i++) { 9058 chipio_read(codec, cur_address, &dsp_data_check[i]); 9059 cur_address += 0x4; 9060 } 9061 for (i = 0; i < 4; i++) { 9062 if (dsp_data_check[i] == 0xa1a2a3a4) 9063 failure = 1; 9064 } 9065 reload--; 9066 } 9067 9068 if (!failure && reload < 3) 9069 codec_info(codec, "DSP fixed."); 9070 9071 if (!failure) 9072 return; 9073 9074 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 9075 } 9076 9077 /* 9078 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 9079 * extra precision for decibel values. If you had the dB value in floating point 9080 * you would take the value after the decimal point, multiply by 64, and divide 9081 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 9082 * implement fixed point or floating point dB volumes. For now, I'll set them 9083 * to 0 just incase a value has lingered from a boot into Windows. 9084 */ 9085 static void ca0132_alt_vol_setup(struct hda_codec *codec) 9086 { 9087 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 9088 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 9089 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 9090 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 9091 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 9092 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 9093 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 9094 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 9095 } 9096 9097 /* 9098 * Extra commands that don't really fit anywhere else. 9099 */ 9100 static void sbz_pre_dsp_setup(struct hda_codec *codec) 9101 { 9102 struct ca0132_spec *spec = codec->spec; 9103 9104 writel(0x00820680, spec->mem_base + 0x01C); 9105 writel(0x00820680, spec->mem_base + 0x01C); 9106 9107 chipio_write(codec, 0x18b0a4, 0x000000c2); 9108 9109 snd_hda_codec_write(codec, 0x11, 0, 9110 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9111 } 9112 9113 static void r3d_pre_dsp_setup(struct hda_codec *codec) 9114 { 9115 chipio_write(codec, 0x18b0a4, 0x000000c2); 9116 9117 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9118 9119 snd_hda_codec_write(codec, 0x11, 0, 9120 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 9121 } 9122 9123 static void r3di_pre_dsp_setup(struct hda_codec *codec) 9124 { 9125 chipio_write(codec, 0x18b0a4, 0x000000c2); 9126 9127 chipio_8051_write_exram(codec, 0x1c1e, 0x5b); 9128 chipio_8051_write_exram(codec, 0x1920, 0x00); 9129 chipio_8051_write_exram(codec, 0x1921, 0x40); 9130 9131 snd_hda_codec_write(codec, 0x11, 0, 9132 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 9133 } 9134 9135 /* 9136 * The ZxR seems to use alternative DAC's for the surround channels, which 9137 * require PLL PMU setup for the clock rate, I'm guessing. Without setting 9138 * this up, we get no audio out of the surround jacks. 9139 */ 9140 static void zxr_pre_dsp_setup(struct hda_codec *codec) 9141 { 9142 static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 }; 9143 static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d }; 9144 unsigned int i; 9145 9146 chipio_write(codec, 0x189000, 0x0001f100); 9147 msleep(50); 9148 chipio_write(codec, 0x18900c, 0x0001f100); 9149 msleep(50); 9150 9151 /* 9152 * This writes a RET instruction at the entry point of the function at 9153 * 0xfa92 in exram. This function seems to have something to do with 9154 * ASI. Might be some way to prevent the card from reconfiguring the 9155 * ASI stuff itself. 9156 */ 9157 chipio_8051_write_exram(codec, 0xfa92, 0x22); 9158 9159 chipio_8051_write_pll_pmu(codec, 0x51, 0x98); 9160 9161 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82); 9162 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3); 9163 9164 chipio_write(codec, 0x18902c, 0x00000000); 9165 msleep(50); 9166 chipio_write(codec, 0x18902c, 0x00000003); 9167 msleep(50); 9168 9169 for (i = 0; i < ARRAY_SIZE(addr); i++) 9170 chipio_8051_write_pll_pmu(codec, addr[i], data[i]); 9171 } 9172 9173 /* 9174 * These are sent before the DSP is downloaded. Not sure 9175 * what they do, or if they're necessary. Could possibly 9176 * be removed. Figure they're better to leave in. 9177 */ 9178 static const unsigned int ca0113_mmio_init_address_sbz[] = { 9179 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 9180 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04 9181 }; 9182 9183 static const unsigned int ca0113_mmio_init_data_sbz[] = { 9184 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9185 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7, 9186 0x000000c1, 0x00000080 9187 }; 9188 9189 static const unsigned int ca0113_mmio_init_data_zxr[] = { 9190 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003, 9191 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 9192 0x000000c1, 0x00000080 9193 }; 9194 9195 static const unsigned int ca0113_mmio_init_address_ae5[] = { 9196 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408, 9197 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800, 9198 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c, 9199 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c 9200 }; 9201 9202 static const unsigned int ca0113_mmio_init_data_ae5[] = { 9203 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 9204 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 9205 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f, 9206 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b, 9207 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030, 9208 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003, 9209 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1, 9210 0x00000080, 0x00880680 9211 }; 9212 9213 static void ca0132_mmio_init_sbz(struct hda_codec *codec) 9214 { 9215 struct ca0132_spec *spec = codec->spec; 9216 unsigned int tmp[2], i, count, cur_addr; 9217 const unsigned int *addr, *data; 9218 9219 addr = ca0113_mmio_init_address_sbz; 9220 for (i = 0; i < 3; i++) 9221 writel(0x00000000, spec->mem_base + addr[i]); 9222 9223 cur_addr = i; 9224 switch (ca0132_quirk(spec)) { 9225 case QUIRK_ZXR: 9226 tmp[0] = 0x00880480; 9227 tmp[1] = 0x00000080; 9228 break; 9229 case QUIRK_SBZ: 9230 tmp[0] = 0x00820680; 9231 tmp[1] = 0x00000083; 9232 break; 9233 case QUIRK_R3D: 9234 tmp[0] = 0x00880680; 9235 tmp[1] = 0x00000083; 9236 break; 9237 default: 9238 tmp[0] = 0x00000000; 9239 tmp[1] = 0x00000000; 9240 break; 9241 } 9242 9243 for (i = 0; i < 2; i++) 9244 writel(tmp[i], spec->mem_base + addr[cur_addr + i]); 9245 9246 cur_addr += i; 9247 9248 switch (ca0132_quirk(spec)) { 9249 case QUIRK_ZXR: 9250 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr); 9251 data = ca0113_mmio_init_data_zxr; 9252 break; 9253 default: 9254 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz); 9255 data = ca0113_mmio_init_data_sbz; 9256 break; 9257 } 9258 9259 for (i = 0; i < count; i++) 9260 writel(data[i], spec->mem_base + addr[cur_addr + i]); 9261 } 9262 9263 static void ca0132_mmio_init_ae5(struct hda_codec *codec) 9264 { 9265 struct ca0132_spec *spec = codec->spec; 9266 const unsigned int *addr, *data; 9267 unsigned int i, count; 9268 9269 addr = ca0113_mmio_init_address_ae5; 9270 data = ca0113_mmio_init_data_ae5; 9271 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5); 9272 9273 if (ca0132_quirk(spec) == QUIRK_AE7) { 9274 writel(0x00000680, spec->mem_base + 0x1c); 9275 writel(0x00880680, spec->mem_base + 0x1c); 9276 } 9277 9278 for (i = 0; i < count; i++) { 9279 /* 9280 * AE-7 shares all writes with the AE-5, except that it writes 9281 * a different value to 0x20c. 9282 */ 9283 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) { 9284 writel(0x00800001, spec->mem_base + addr[i]); 9285 continue; 9286 } 9287 9288 writel(data[i], spec->mem_base + addr[i]); 9289 } 9290 9291 if (ca0132_quirk(spec) == QUIRK_AE5) 9292 writel(0x00880680, spec->mem_base + 0x1c); 9293 } 9294 9295 static void ca0132_mmio_init(struct hda_codec *codec) 9296 { 9297 struct ca0132_spec *spec = codec->spec; 9298 9299 switch (ca0132_quirk(spec)) { 9300 case QUIRK_R3D: 9301 case QUIRK_SBZ: 9302 case QUIRK_ZXR: 9303 ca0132_mmio_init_sbz(codec); 9304 break; 9305 case QUIRK_AE5: 9306 ca0132_mmio_init_ae5(codec); 9307 break; 9308 default: 9309 break; 9310 } 9311 } 9312 9313 static const unsigned int ca0132_ae5_register_set_addresses[] = { 9314 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304, 9315 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804 9316 }; 9317 9318 static const unsigned char ca0132_ae5_register_set_data[] = { 9319 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b, 9320 0x01, 0x6b, 0x57 9321 }; 9322 9323 /* 9324 * This function writes to some SFR's, does some region2 writes, and then 9325 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 9326 * what it does. 9327 */ 9328 static void ae5_register_set(struct hda_codec *codec) 9329 { 9330 struct ca0132_spec *spec = codec->spec; 9331 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses); 9332 const unsigned int *addr = ca0132_ae5_register_set_addresses; 9333 const unsigned char *data = ca0132_ae5_register_set_data; 9334 unsigned int i, cur_addr; 9335 unsigned char tmp[3]; 9336 9337 if (ca0132_quirk(spec) == QUIRK_AE7) 9338 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8); 9339 9340 chipio_8051_write_direct(codec, 0x93, 0x10); 9341 chipio_8051_write_pll_pmu(codec, 0x44, 0xc2); 9342 9343 if (ca0132_quirk(spec) == QUIRK_AE7) { 9344 tmp[0] = 0x03; 9345 tmp[1] = 0x03; 9346 tmp[2] = 0x07; 9347 } else { 9348 tmp[0] = 0x0f; 9349 tmp[1] = 0x0f; 9350 tmp[2] = 0x0f; 9351 } 9352 9353 for (i = cur_addr = 0; i < 3; i++, cur_addr++) 9354 writeb(tmp[i], spec->mem_base + addr[cur_addr]); 9355 9356 /* 9357 * First writes are in single bytes, final are in 4 bytes. So, we use 9358 * writeb, then writel. 9359 */ 9360 for (i = 0; cur_addr < 12; i++, cur_addr++) 9361 writeb(data[i], spec->mem_base + addr[cur_addr]); 9362 9363 for (; cur_addr < count; i++, cur_addr++) 9364 writel(data[i], spec->mem_base + addr[cur_addr]); 9365 9366 writel(0x00800001, spec->mem_base + 0x20c); 9367 9368 if (ca0132_quirk(spec) == QUIRK_AE7) { 9369 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83); 9370 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 9371 } else { 9372 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 9373 } 9374 9375 chipio_8051_write_direct(codec, 0x90, 0x00); 9376 chipio_8051_write_direct(codec, 0x90, 0x10); 9377 9378 if (ca0132_quirk(spec) == QUIRK_AE5) 9379 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 9380 } 9381 9382 /* 9383 * Extra init functions for alternative ca0132 codecs. Done 9384 * here so they don't clutter up the main ca0132_init function 9385 * anymore than they have to. 9386 */ 9387 static void ca0132_alt_init(struct hda_codec *codec) 9388 { 9389 struct ca0132_spec *spec = codec->spec; 9390 9391 ca0132_alt_vol_setup(codec); 9392 9393 switch (ca0132_quirk(spec)) { 9394 case QUIRK_SBZ: 9395 codec_dbg(codec, "SBZ alt_init"); 9396 ca0132_gpio_init(codec); 9397 sbz_pre_dsp_setup(codec); 9398 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9399 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9400 break; 9401 case QUIRK_R3DI: 9402 codec_dbg(codec, "R3DI alt_init"); 9403 ca0132_gpio_init(codec); 9404 ca0132_gpio_setup(codec); 9405 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 9406 r3di_pre_dsp_setup(codec); 9407 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9408 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 9409 break; 9410 case QUIRK_R3D: 9411 r3d_pre_dsp_setup(codec); 9412 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9413 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9414 break; 9415 case QUIRK_AE5: 9416 ca0132_gpio_init(codec); 9417 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9418 chipio_write(codec, 0x18b030, 0x00000020); 9419 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9420 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9421 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9422 break; 9423 case QUIRK_AE7: 9424 ca0132_gpio_init(codec); 9425 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9426 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9427 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9428 chipio_write(codec, 0x18b008, 0x000000f8); 9429 chipio_write(codec, 0x18b008, 0x000000f0); 9430 chipio_write(codec, 0x18b030, 0x00000020); 9431 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 9432 break; 9433 case QUIRK_ZXR: 9434 chipio_8051_write_pll_pmu(codec, 0x49, 0x88); 9435 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9436 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 9437 zxr_pre_dsp_setup(codec); 9438 break; 9439 default: 9440 break; 9441 } 9442 } 9443 9444 static int ca0132_init(struct hda_codec *codec) 9445 { 9446 struct ca0132_spec *spec = codec->spec; 9447 struct auto_pin_cfg *cfg = &spec->autocfg; 9448 int i; 9449 bool dsp_loaded; 9450 9451 /* 9452 * If the DSP is already downloaded, and init has been entered again, 9453 * there's only two reasons for it. One, the codec has awaken from a 9454 * suspended state, and in that case dspload_is_loaded will return 9455 * false, and the init will be ran again. The other reason it gets 9456 * re entered is on startup for some reason it triggers a suspend and 9457 * resume state. In this case, it will check if the DSP is downloaded, 9458 * and not run the init function again. For codecs using alt_functions, 9459 * it will check if the DSP is loaded properly. 9460 */ 9461 if (spec->dsp_state == DSP_DOWNLOADED) { 9462 dsp_loaded = dspload_is_loaded(codec); 9463 if (!dsp_loaded) { 9464 spec->dsp_reload = true; 9465 spec->dsp_state = DSP_DOWNLOAD_INIT; 9466 } else { 9467 if (ca0132_quirk(spec) == QUIRK_SBZ) 9468 sbz_dsp_startup_check(codec); 9469 return 0; 9470 } 9471 } 9472 9473 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 9474 spec->dsp_state = DSP_DOWNLOAD_INIT; 9475 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 9476 9477 if (ca0132_use_pci_mmio(spec)) 9478 ca0132_mmio_init(codec); 9479 9480 CLASS(snd_hda_power_pm, pm)(codec); 9481 9482 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7) 9483 ae5_register_set(codec); 9484 9485 ca0132_init_params(codec); 9486 ca0132_init_flags(codec); 9487 9488 snd_hda_sequence_write(codec, spec->base_init_verbs); 9489 9490 if (ca0132_use_alt_functions(spec)) 9491 ca0132_alt_init(codec); 9492 9493 ca0132_download_dsp(codec); 9494 9495 ca0132_refresh_widget_caps(codec); 9496 9497 switch (ca0132_quirk(spec)) { 9498 case QUIRK_R3DI: 9499 case QUIRK_R3D: 9500 r3d_setup_defaults(codec); 9501 break; 9502 case QUIRK_SBZ: 9503 case QUIRK_ZXR: 9504 sbz_setup_defaults(codec); 9505 break; 9506 case QUIRK_AE5: 9507 ae5_setup_defaults(codec); 9508 break; 9509 case QUIRK_AE7: 9510 ae7_setup_defaults(codec); 9511 break; 9512 default: 9513 ca0132_setup_defaults(codec); 9514 ca0132_init_analog_mic2(codec); 9515 ca0132_init_dmic(codec); 9516 break; 9517 } 9518 9519 for (i = 0; i < spec->num_outputs; i++) 9520 init_output(codec, spec->out_pins[i], spec->dacs[0]); 9521 9522 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9523 9524 for (i = 0; i < spec->num_inputs; i++) 9525 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9526 9527 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9528 9529 if (!ca0132_use_alt_functions(spec)) { 9530 snd_hda_sequence_write(codec, spec->chip_init_verbs); 9531 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9532 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 9533 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 9534 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 9535 } 9536 9537 if (ca0132_quirk(spec) == QUIRK_SBZ) 9538 ca0132_gpio_setup(codec); 9539 9540 snd_hda_sequence_write(codec, spec->spec_init_verbs); 9541 if (ca0132_use_alt_functions(spec)) { 9542 ca0132_alt_select_out(codec); 9543 ca0132_alt_select_in(codec); 9544 } else { 9545 ca0132_select_out(codec); 9546 ca0132_select_mic(codec); 9547 } 9548 9549 snd_hda_jack_report_sync(codec); 9550 9551 /* 9552 * Re set the PlayEnhancement switch on a resume event, because the 9553 * controls will not be reloaded. 9554 */ 9555 if (spec->dsp_reload) { 9556 spec->dsp_reload = false; 9557 ca0132_pe_switch_set(codec); 9558 } 9559 9560 return 0; 9561 } 9562 9563 static int dbpro_init(struct hda_codec *codec) 9564 { 9565 struct ca0132_spec *spec = codec->spec; 9566 struct auto_pin_cfg *cfg = &spec->autocfg; 9567 unsigned int i; 9568 9569 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 9570 init_input(codec, cfg->dig_in_pin, spec->dig_in); 9571 9572 for (i = 0; i < spec->num_inputs; i++) 9573 init_input(codec, spec->input_pins[i], spec->adcs[i]); 9574 9575 return 0; 9576 } 9577 9578 static void ca0132_free(struct hda_codec *codec) 9579 { 9580 struct ca0132_spec *spec = codec->spec; 9581 9582 cancel_delayed_work_sync(&spec->unsol_hp_work); 9583 snd_hda_power_up(codec); 9584 switch (ca0132_quirk(spec)) { 9585 case QUIRK_SBZ: 9586 sbz_exit_chip(codec); 9587 break; 9588 case QUIRK_ZXR: 9589 zxr_exit_chip(codec); 9590 break; 9591 case QUIRK_R3D: 9592 r3d_exit_chip(codec); 9593 break; 9594 case QUIRK_AE5: 9595 ae5_exit_chip(codec); 9596 break; 9597 case QUIRK_AE7: 9598 ae7_exit_chip(codec); 9599 break; 9600 case QUIRK_R3DI: 9601 r3di_gpio_shutdown(codec); 9602 break; 9603 default: 9604 break; 9605 } 9606 9607 snd_hda_sequence_write(codec, spec->base_exit_verbs); 9608 ca0132_exit_chip(codec); 9609 9610 snd_hda_power_down(codec); 9611 #ifdef CONFIG_PCI 9612 if (spec->mem_base) 9613 pci_iounmap(codec->bus->pci, spec->mem_base); 9614 #endif 9615 kfree(spec->spec_init_verbs); 9616 kfree(codec->spec); 9617 } 9618 9619 static void dbpro_free(struct hda_codec *codec) 9620 { 9621 struct ca0132_spec *spec = codec->spec; 9622 9623 zxr_dbpro_power_state_shutdown(codec); 9624 9625 kfree(spec->spec_init_verbs); 9626 kfree(codec->spec); 9627 } 9628 9629 static void ca0132_config(struct hda_codec *codec) 9630 { 9631 struct ca0132_spec *spec = codec->spec; 9632 9633 spec->dacs[0] = 0x2; 9634 spec->dacs[1] = 0x3; 9635 spec->dacs[2] = 0x4; 9636 9637 spec->multiout.dac_nids = spec->dacs; 9638 spec->multiout.num_dacs = 3; 9639 9640 if (!ca0132_use_alt_functions(spec)) 9641 spec->multiout.max_channels = 2; 9642 else 9643 spec->multiout.max_channels = 6; 9644 9645 switch (ca0132_quirk(spec)) { 9646 case QUIRK_ALIENWARE: 9647 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 9648 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 9649 break; 9650 case QUIRK_SBZ: 9651 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 9652 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 9653 break; 9654 case QUIRK_ZXR: 9655 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 9656 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 9657 break; 9658 case QUIRK_R3D: 9659 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 9660 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 9661 break; 9662 case QUIRK_R3DI: 9663 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 9664 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 9665 break; 9666 case QUIRK_AE5: 9667 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 9668 snd_hda_apply_pincfgs(codec, ae5_pincfgs); 9669 break; 9670 case QUIRK_AE7: 9671 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__); 9672 snd_hda_apply_pincfgs(codec, ae7_pincfgs); 9673 break; 9674 default: 9675 break; 9676 } 9677 9678 switch (ca0132_quirk(spec)) { 9679 case QUIRK_ALIENWARE: 9680 spec->num_outputs = 2; 9681 spec->out_pins[0] = 0x0b; /* speaker out */ 9682 spec->out_pins[1] = 0x0f; 9683 spec->shared_out_nid = 0x2; 9684 spec->unsol_tag_hp = 0x0f; 9685 9686 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9687 spec->adcs[1] = 0x8; /* analog mic2 */ 9688 spec->adcs[2] = 0xa; /* what u hear */ 9689 9690 spec->num_inputs = 3; 9691 spec->input_pins[0] = 0x12; 9692 spec->input_pins[1] = 0x11; 9693 spec->input_pins[2] = 0x13; 9694 spec->shared_mic_nid = 0x7; 9695 spec->unsol_tag_amic1 = 0x11; 9696 break; 9697 case QUIRK_SBZ: 9698 case QUIRK_R3D: 9699 spec->num_outputs = 2; 9700 spec->out_pins[0] = 0x0B; /* Line out */ 9701 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9702 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9703 spec->out_pins[3] = 0x11; /* Rear surround */ 9704 spec->shared_out_nid = 0x2; 9705 spec->unsol_tag_hp = spec->out_pins[1]; 9706 spec->unsol_tag_front_hp = spec->out_pins[2]; 9707 9708 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9709 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9710 spec->adcs[2] = 0xa; /* what u hear */ 9711 9712 spec->num_inputs = 2; 9713 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9714 spec->input_pins[1] = 0x13; /* What U Hear */ 9715 spec->shared_mic_nid = 0x7; 9716 spec->unsol_tag_amic1 = spec->input_pins[0]; 9717 9718 /* SPDIF I/O */ 9719 spec->dig_out = 0x05; 9720 spec->multiout.dig_out_nid = spec->dig_out; 9721 spec->dig_in = 0x09; 9722 break; 9723 case QUIRK_ZXR: 9724 spec->num_outputs = 2; 9725 spec->out_pins[0] = 0x0B; /* Line out */ 9726 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9727 spec->out_pins[2] = 0x10; /* Center/LFE */ 9728 spec->out_pins[3] = 0x11; /* Rear surround */ 9729 spec->shared_out_nid = 0x2; 9730 spec->unsol_tag_hp = spec->out_pins[1]; 9731 spec->unsol_tag_front_hp = spec->out_pins[2]; 9732 9733 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9734 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 9735 spec->adcs[2] = 0xa; /* what u hear */ 9736 9737 spec->num_inputs = 2; 9738 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9739 spec->input_pins[1] = 0x13; /* What U Hear */ 9740 spec->shared_mic_nid = 0x7; 9741 spec->unsol_tag_amic1 = spec->input_pins[0]; 9742 break; 9743 case QUIRK_ZXR_DBPRO: 9744 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 9745 9746 spec->num_inputs = 1; 9747 spec->input_pins[0] = 0x11; /* RCA Line-in */ 9748 9749 spec->dig_out = 0x05; 9750 spec->multiout.dig_out_nid = spec->dig_out; 9751 9752 spec->dig_in = 0x09; 9753 break; 9754 case QUIRK_AE5: 9755 case QUIRK_AE7: 9756 spec->num_outputs = 2; 9757 spec->out_pins[0] = 0x0B; /* Line out */ 9758 spec->out_pins[1] = 0x11; /* Rear headphone out */ 9759 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9760 spec->out_pins[3] = 0x0F; /* Rear surround */ 9761 spec->shared_out_nid = 0x2; 9762 spec->unsol_tag_hp = spec->out_pins[1]; 9763 spec->unsol_tag_front_hp = spec->out_pins[2]; 9764 9765 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 9766 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 9767 spec->adcs[2] = 0xa; /* what u hear */ 9768 9769 spec->num_inputs = 2; 9770 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9771 spec->input_pins[1] = 0x13; /* What U Hear */ 9772 spec->shared_mic_nid = 0x7; 9773 spec->unsol_tag_amic1 = spec->input_pins[0]; 9774 9775 /* SPDIF I/O */ 9776 spec->dig_out = 0x05; 9777 spec->multiout.dig_out_nid = spec->dig_out; 9778 break; 9779 case QUIRK_R3DI: 9780 spec->num_outputs = 2; 9781 spec->out_pins[0] = 0x0B; /* Line out */ 9782 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 9783 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 9784 spec->out_pins[3] = 0x11; /* Rear surround */ 9785 spec->shared_out_nid = 0x2; 9786 spec->unsol_tag_hp = spec->out_pins[1]; 9787 spec->unsol_tag_front_hp = spec->out_pins[2]; 9788 9789 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 9790 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 9791 spec->adcs[2] = 0x0a; /* what u hear */ 9792 9793 spec->num_inputs = 2; 9794 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 9795 spec->input_pins[1] = 0x13; /* What U Hear */ 9796 spec->shared_mic_nid = 0x7; 9797 spec->unsol_tag_amic1 = spec->input_pins[0]; 9798 9799 /* SPDIF I/O */ 9800 spec->dig_out = 0x05; 9801 spec->multiout.dig_out_nid = spec->dig_out; 9802 break; 9803 default: 9804 spec->num_outputs = 2; 9805 spec->out_pins[0] = 0x0b; /* speaker out */ 9806 spec->out_pins[1] = 0x10; /* headphone out */ 9807 spec->shared_out_nid = 0x2; 9808 spec->unsol_tag_hp = spec->out_pins[1]; 9809 9810 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 9811 spec->adcs[1] = 0x8; /* analog mic2 */ 9812 spec->adcs[2] = 0xa; /* what u hear */ 9813 9814 spec->num_inputs = 3; 9815 spec->input_pins[0] = 0x12; 9816 spec->input_pins[1] = 0x11; 9817 spec->input_pins[2] = 0x13; 9818 spec->shared_mic_nid = 0x7; 9819 spec->unsol_tag_amic1 = spec->input_pins[0]; 9820 9821 /* SPDIF I/O */ 9822 spec->dig_out = 0x05; 9823 spec->multiout.dig_out_nid = spec->dig_out; 9824 spec->dig_in = 0x09; 9825 break; 9826 } 9827 9828 /* Default HP/Speaker auto-detect from headphone pin verb: enable if the 9829 * pin config indicates presence detect (not AC_DEFCFG_MISC_NO_PRESENCE). 9830 */ 9831 if (spec->unsol_tag_hp && 9832 (snd_hda_query_pin_caps(codec, spec->unsol_tag_hp) & AC_PINCAP_PRES_DETECT) && 9833 !(get_defcfg_misc(snd_hda_codec_get_pincfg(codec, spec->unsol_tag_hp)) & 9834 AC_DEFCFG_MISC_NO_PRESENCE)) 9835 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID] = 1; 9836 } 9837 9838 static int ca0132_prepare_verbs(struct hda_codec *codec) 9839 { 9840 /* Verbs + terminator (an empty element) */ 9841 #define NUM_SPEC_VERBS 2 9842 struct ca0132_spec *spec = codec->spec; 9843 9844 spec->chip_init_verbs = ca0132_init_verbs0; 9845 /* 9846 * Since desktop cards use pci_mmio, this can be used to determine 9847 * whether or not to use these verbs instead of a separate bool. 9848 */ 9849 if (ca0132_use_pci_mmio(spec)) 9850 spec->desktop_init_verbs = ca0132_init_verbs1; 9851 spec->spec_init_verbs = kzalloc_objs(struct hda_verb, NUM_SPEC_VERBS); 9852 if (!spec->spec_init_verbs) 9853 return -ENOMEM; 9854 9855 /* config EAPD */ 9856 spec->spec_init_verbs[0].nid = 0x0b; 9857 spec->spec_init_verbs[0].param = 0x78D; 9858 spec->spec_init_verbs[0].verb = 0x00; 9859 9860 /* Previously commented configuration */ 9861 /* 9862 spec->spec_init_verbs[2].nid = 0x0b; 9863 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 9864 spec->spec_init_verbs[2].verb = 0x02; 9865 9866 spec->spec_init_verbs[3].nid = 0x10; 9867 spec->spec_init_verbs[3].param = 0x78D; 9868 spec->spec_init_verbs[3].verb = 0x02; 9869 9870 spec->spec_init_verbs[4].nid = 0x10; 9871 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 9872 spec->spec_init_verbs[4].verb = 0x02; 9873 */ 9874 9875 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 9876 return 0; 9877 } 9878 9879 /* 9880 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 9881 * Sound Blaster Z cards. However, they have different HDA codec subsystem 9882 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 9883 * daughter boards ID. 9884 */ 9885 static void sbz_detect_quirk(struct hda_codec *codec) 9886 { 9887 switch (codec->core.subsystem_id) { 9888 case 0x11020033: 9889 codec->fixup_id = QUIRK_ZXR; 9890 break; 9891 case 0x1102003f: 9892 codec->fixup_id = QUIRK_ZXR_DBPRO; 9893 break; 9894 default: 9895 codec->fixup_id = QUIRK_SBZ; 9896 break; 9897 } 9898 } 9899 9900 static void ca0132_codec_remove(struct hda_codec *codec) 9901 { 9902 struct ca0132_spec *spec = codec->spec; 9903 9904 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 9905 return dbpro_free(codec); 9906 else 9907 return ca0132_free(codec); 9908 } 9909 9910 static int ca0132_codec_probe(struct hda_codec *codec, 9911 const struct hda_device_id *id) 9912 { 9913 struct ca0132_spec *spec; 9914 int err; 9915 9916 codec_dbg(codec, "%s\n", __func__); 9917 9918 spec = kzalloc_obj(*spec); 9919 if (!spec) 9920 return -ENOMEM; 9921 codec->spec = spec; 9922 spec->codec = codec; 9923 9924 /* Detect codec quirk */ 9925 snd_hda_pick_fixup(codec, ca0132_quirk_models, ca0132_quirks, NULL); 9926 if (ca0132_quirk(spec) == QUIRK_SBZ) 9927 sbz_detect_quirk(codec); 9928 9929 codec->pcm_format_first = 1; 9930 codec->no_sticky_stream = 1; 9931 9932 9933 spec->dsp_state = DSP_DOWNLOAD_INIT; 9934 spec->num_mixers = 1; 9935 9936 /* Set which mixers each quirk uses. */ 9937 switch (ca0132_quirk(spec)) { 9938 case QUIRK_SBZ: 9939 spec->mixers[0] = desktop_mixer; 9940 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 9941 break; 9942 case QUIRK_ZXR: 9943 spec->mixers[0] = desktop_mixer; 9944 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 9945 break; 9946 case QUIRK_ZXR_DBPRO: 9947 break; 9948 case QUIRK_R3D: 9949 spec->mixers[0] = desktop_mixer; 9950 snd_hda_codec_set_name(codec, "Recon3D"); 9951 break; 9952 case QUIRK_R3DI: 9953 spec->mixers[0] = r3di_mixer; 9954 snd_hda_codec_set_name(codec, "Recon3Di"); 9955 break; 9956 case QUIRK_AE5: 9957 spec->mixers[0] = desktop_mixer; 9958 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 9959 break; 9960 case QUIRK_AE7: 9961 spec->mixers[0] = desktop_mixer; 9962 snd_hda_codec_set_name(codec, "Sound Blaster AE-7"); 9963 break; 9964 default: 9965 spec->mixers[0] = ca0132_mixer; 9966 break; 9967 } 9968 9969 /* Setup whether or not to use alt functions/controls/pci_mmio */ 9970 switch (ca0132_quirk(spec)) { 9971 case QUIRK_SBZ: 9972 case QUIRK_R3D: 9973 case QUIRK_AE5: 9974 case QUIRK_AE7: 9975 case QUIRK_ZXR: 9976 spec->use_alt_controls = true; 9977 spec->use_alt_functions = true; 9978 spec->use_pci_mmio = true; 9979 break; 9980 case QUIRK_R3DI: 9981 spec->use_alt_controls = true; 9982 spec->use_alt_functions = true; 9983 spec->use_pci_mmio = false; 9984 break; 9985 default: 9986 spec->use_alt_controls = false; 9987 spec->use_alt_functions = false; 9988 spec->use_pci_mmio = false; 9989 break; 9990 } 9991 9992 #ifdef CONFIG_PCI 9993 if (spec->use_pci_mmio) { 9994 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 9995 if (spec->mem_base == NULL) { 9996 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 9997 codec->fixup_id = QUIRK_NONE; 9998 } 9999 } 10000 #endif 10001 10002 spec->base_init_verbs = ca0132_base_init_verbs; 10003 spec->base_exit_verbs = ca0132_base_exit_verbs; 10004 10005 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 10006 10007 ca0132_init_chip(codec); 10008 10009 ca0132_config(codec); 10010 10011 err = ca0132_prepare_verbs(codec); 10012 if (err < 0) 10013 goto error; 10014 10015 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 10016 if (err < 0) 10017 goto error; 10018 10019 ca0132_setup_unsol(codec); 10020 10021 return 0; 10022 10023 error: 10024 ca0132_codec_remove(codec); 10025 return err; 10026 } 10027 10028 static int ca0132_codec_build_controls(struct hda_codec *codec) 10029 { 10030 struct ca0132_spec *spec = codec->spec; 10031 10032 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 10033 return dbpro_build_controls(codec); 10034 else 10035 return ca0132_build_controls(codec); 10036 } 10037 10038 static int ca0132_codec_build_pcms(struct hda_codec *codec) 10039 { 10040 struct ca0132_spec *spec = codec->spec; 10041 10042 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 10043 return dbpro_build_pcms(codec); 10044 else 10045 return ca0132_build_pcms(codec); 10046 } 10047 10048 static int ca0132_codec_init(struct hda_codec *codec) 10049 { 10050 struct ca0132_spec *spec = codec->spec; 10051 10052 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 10053 return dbpro_init(codec); 10054 else 10055 return ca0132_init(codec); 10056 } 10057 10058 static int ca0132_codec_suspend(struct hda_codec *codec) 10059 { 10060 struct ca0132_spec *spec = codec->spec; 10061 10062 cancel_delayed_work_sync(&spec->unsol_hp_work); 10063 return 0; 10064 } 10065 10066 static const struct hda_codec_ops ca0132_codec_ops = { 10067 .probe = ca0132_codec_probe, 10068 .remove = ca0132_codec_remove, 10069 .build_controls = ca0132_codec_build_controls, 10070 .build_pcms = ca0132_codec_build_pcms, 10071 .init = ca0132_codec_init, 10072 .unsol_event = snd_hda_jack_unsol_event, 10073 .suspend = ca0132_codec_suspend, 10074 }; 10075 10076 /* 10077 * driver entries 10078 */ 10079 static const struct hda_device_id snd_hda_id_ca0132[] = { 10080 HDA_CODEC_ID(0x11020011, "CA0132"), 10081 {} /* terminator */ 10082 }; 10083 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 10084 10085 MODULE_LICENSE("GPL"); 10086 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 10087 10088 static struct hda_codec_driver ca0132_driver = { 10089 .id = snd_hda_id_ca0132, 10090 .ops = &ca0132_codec_ops, 10091 }; 10092 10093 module_hda_codec_driver(ca0132_driver); 10094