1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * fireworks_command.c - a part of driver for Fireworks based devices 4 * 5 * Copyright (c) 2013-2014 Takashi Sakamoto 6 */ 7 8 #include "./fireworks.h" 9 10 /* 11 * This driver uses transaction version 1 or later to use extended hardware 12 * information. Then too old devices are not available. 13 * 14 * Each commands are not required to have continuous sequence numbers. This 15 * number is just used to match command and response. 16 * 17 * This module support a part of commands. Please see FFADO if you want to see 18 * whole commands. But there are some commands which FFADO don't implement. 19 * 20 * Fireworks also supports AV/C general commands and AV/C Stream Format 21 * Information commands. But this module don't use them. 22 */ 23 24 #define KERNEL_SEQNUM_MIN (SND_EFW_TRANSACTION_USER_SEQNUM_MAX + 2) 25 #define KERNEL_SEQNUM_MAX ((u32)~0) 26 27 /* for clock source and sampling rate */ 28 struct efc_clock { 29 u32 source; 30 u32 sampling_rate; 31 u32 index; 32 }; 33 34 /* command categories */ 35 enum efc_category { 36 EFC_CAT_HWINFO = 0, 37 EFC_CAT_TRANSPORT = 2, 38 EFC_CAT_HWCTL = 3, 39 }; 40 41 /* hardware info category commands */ 42 enum efc_cmd_hwinfo { 43 EFC_CMD_HWINFO_GET_CAPS = 0, 44 EFC_CMD_HWINFO_GET_POLLED = 1, 45 EFC_CMD_HWINFO_SET_RESP_ADDR = 2 46 }; 47 48 enum efc_cmd_transport { 49 EFC_CMD_TRANSPORT_SET_TX_MODE = 0 50 }; 51 52 /* hardware control category commands */ 53 enum efc_cmd_hwctl { 54 EFC_CMD_HWCTL_SET_CLOCK = 0, 55 EFC_CMD_HWCTL_GET_CLOCK = 1, 56 EFC_CMD_HWCTL_IDENTIFY = 5 57 }; 58 59 /* return values in response */ 60 enum efr_status { 61 EFR_STATUS_OK = 0, 62 EFR_STATUS_BAD = 1, 63 EFR_STATUS_BAD_COMMAND = 2, 64 EFR_STATUS_COMM_ERR = 3, 65 EFR_STATUS_BAD_QUAD_COUNT = 4, 66 EFR_STATUS_UNSUPPORTED = 5, 67 EFR_STATUS_1394_TIMEOUT = 6, 68 EFR_STATUS_DSP_TIMEOUT = 7, 69 EFR_STATUS_BAD_RATE = 8, 70 EFR_STATUS_BAD_CLOCK = 9, 71 EFR_STATUS_BAD_CHANNEL = 10, 72 EFR_STATUS_BAD_PAN = 11, 73 EFR_STATUS_FLASH_BUSY = 12, 74 EFR_STATUS_BAD_MIRROR = 13, 75 EFR_STATUS_BAD_LED = 14, 76 EFR_STATUS_BAD_PARAMETER = 15, 77 EFR_STATUS_INCOMPLETE = 0x80000000 78 }; 79 80 static const char *const efr_status_names[] = { 81 [EFR_STATUS_OK] = "OK", 82 [EFR_STATUS_BAD] = "bad", 83 [EFR_STATUS_BAD_COMMAND] = "bad command", 84 [EFR_STATUS_COMM_ERR] = "comm err", 85 [EFR_STATUS_BAD_QUAD_COUNT] = "bad quad count", 86 [EFR_STATUS_UNSUPPORTED] = "unsupported", 87 [EFR_STATUS_1394_TIMEOUT] = "1394 timeout", 88 [EFR_STATUS_DSP_TIMEOUT] = "DSP timeout", 89 [EFR_STATUS_BAD_RATE] = "bad rate", 90 [EFR_STATUS_BAD_CLOCK] = "bad clock", 91 [EFR_STATUS_BAD_CHANNEL] = "bad channel", 92 [EFR_STATUS_BAD_PAN] = "bad pan", 93 [EFR_STATUS_FLASH_BUSY] = "flash busy", 94 [EFR_STATUS_BAD_MIRROR] = "bad mirror", 95 [EFR_STATUS_BAD_LED] = "bad LED", 96 [EFR_STATUS_BAD_PARAMETER] = "bad parameter", 97 [EFR_STATUS_BAD_PARAMETER + 1] = "incomplete" 98 }; 99 100 static int 101 efw_transaction(struct snd_efw *efw, unsigned int category, 102 unsigned int command, 103 const __be32 *params, unsigned int param_bytes, 104 const __be32 *resp, unsigned int resp_bytes) 105 { 106 struct snd_efw_transaction *header; 107 __be32 *buf; 108 u32 seqnum; 109 unsigned int buf_bytes, cmd_bytes; 110 int err; 111 112 /* calculate buffer size*/ 113 buf_bytes = sizeof(struct snd_efw_transaction) + 114 max(param_bytes, resp_bytes); 115 116 /* keep buffer */ 117 buf = kzalloc(buf_bytes, GFP_KERNEL); 118 if (buf == NULL) 119 return -ENOMEM; 120 121 /* to keep consistency of sequence number */ 122 scoped_guard(spinlock, &efw->lock) { 123 if ((efw->seqnum < KERNEL_SEQNUM_MIN) || 124 (efw->seqnum >= KERNEL_SEQNUM_MAX - 2)) 125 efw->seqnum = KERNEL_SEQNUM_MIN; 126 else 127 efw->seqnum += 2; 128 seqnum = efw->seqnum; 129 } 130 131 /* fill transaction header fields */ 132 cmd_bytes = sizeof(struct snd_efw_transaction) + param_bytes; 133 header = (struct snd_efw_transaction *)buf; 134 header->length = cpu_to_be32(cmd_bytes / sizeof(__be32)); 135 header->version = cpu_to_be32(1); 136 header->seqnum = cpu_to_be32(seqnum); 137 header->category = cpu_to_be32(category); 138 header->command = cpu_to_be32(command); 139 header->status = 0; 140 141 /* fill transaction command parameters */ 142 memcpy(header->params, params, param_bytes); 143 144 err = snd_efw_transaction_run(efw->unit, buf, cmd_bytes, 145 buf, buf_bytes); 146 if (err < 0) 147 goto end; 148 149 /* check transaction header fields */ 150 if ((be32_to_cpu(header->version) < 1) || 151 (be32_to_cpu(header->category) != category) || 152 (be32_to_cpu(header->command) != command) || 153 (be32_to_cpu(header->status) != EFR_STATUS_OK)) { 154 u32 st = be32_to_cpu(header->status); 155 156 dev_err(&efw->unit->device, "EFW command failed [%u/%u]: %s\n", 157 be32_to_cpu(header->category), 158 be32_to_cpu(header->command), 159 st < ARRAY_SIZE(efr_status_names) ? 160 efr_status_names[st] : "unknown"); 161 err = -EIO; 162 goto end; 163 } 164 165 if (resp == NULL) 166 goto end; 167 168 /* fill transaction response parameters */ 169 memset((void *)resp, 0, resp_bytes); 170 resp_bytes = min_t(unsigned int, resp_bytes, 171 be32_to_cpu(header->length) * sizeof(__be32) - 172 sizeof(struct snd_efw_transaction)); 173 memcpy((void *)resp, &buf[6], resp_bytes); 174 end: 175 kfree(buf); 176 return err; 177 } 178 179 /* 180 * The address in host system for transaction response is changable when the 181 * device supports. struct hwinfo.flags includes its flag. The default is 182 * MEMORY_SPACE_EFW_RESPONSE. 183 */ 184 int snd_efw_command_set_resp_addr(struct snd_efw *efw, 185 u16 addr_high, u32 addr_low) 186 { 187 __be32 addr[2]; 188 189 addr[0] = cpu_to_be32(addr_high); 190 addr[1] = cpu_to_be32(addr_low); 191 192 if (!efw->resp_addr_changable) 193 return -ENOSYS; 194 195 return efw_transaction(efw, EFC_CAT_HWCTL, 196 EFC_CMD_HWINFO_SET_RESP_ADDR, 197 addr, sizeof(addr), NULL, 0); 198 } 199 200 /* 201 * This is for timestamp processing. In Windows mode, all 32bit fields of second 202 * CIP header in AMDTP transmit packet is used for 'presentation timestamp'. In 203 * 'no data' packet the value of this field is 0x90ffffff. 204 */ 205 int snd_efw_command_set_tx_mode(struct snd_efw *efw, 206 enum snd_efw_transport_mode mode) 207 { 208 __be32 param = cpu_to_be32(mode); 209 return efw_transaction(efw, EFC_CAT_TRANSPORT, 210 EFC_CMD_TRANSPORT_SET_TX_MODE, 211 ¶m, sizeof(param), NULL, 0); 212 } 213 214 int snd_efw_command_get_hwinfo(struct snd_efw *efw, 215 struct snd_efw_hwinfo *hwinfo) 216 { 217 int err; 218 219 err = efw_transaction(efw, EFC_CAT_HWINFO, 220 EFC_CMD_HWINFO_GET_CAPS, 221 NULL, 0, (__be32 *)hwinfo, sizeof(*hwinfo)); 222 if (err < 0) 223 goto end; 224 225 be32_to_cpus(&hwinfo->flags); 226 be32_to_cpus(&hwinfo->guid_hi); 227 be32_to_cpus(&hwinfo->guid_lo); 228 be32_to_cpus(&hwinfo->type); 229 be32_to_cpus(&hwinfo->version); 230 be32_to_cpus(&hwinfo->supported_clocks); 231 be32_to_cpus(&hwinfo->amdtp_rx_pcm_channels); 232 be32_to_cpus(&hwinfo->amdtp_tx_pcm_channels); 233 be32_to_cpus(&hwinfo->phys_out); 234 be32_to_cpus(&hwinfo->phys_in); 235 be32_to_cpus(&hwinfo->phys_out_grp_count); 236 be32_to_cpus(&hwinfo->phys_in_grp_count); 237 be32_to_cpus(&hwinfo->midi_out_ports); 238 be32_to_cpus(&hwinfo->midi_in_ports); 239 be32_to_cpus(&hwinfo->max_sample_rate); 240 be32_to_cpus(&hwinfo->min_sample_rate); 241 be32_to_cpus(&hwinfo->dsp_version); 242 be32_to_cpus(&hwinfo->arm_version); 243 be32_to_cpus(&hwinfo->mixer_playback_channels); 244 be32_to_cpus(&hwinfo->mixer_capture_channels); 245 be32_to_cpus(&hwinfo->fpga_version); 246 be32_to_cpus(&hwinfo->amdtp_rx_pcm_channels_2x); 247 be32_to_cpus(&hwinfo->amdtp_tx_pcm_channels_2x); 248 be32_to_cpus(&hwinfo->amdtp_rx_pcm_channels_4x); 249 be32_to_cpus(&hwinfo->amdtp_tx_pcm_channels_4x); 250 251 /* ensure terminated */ 252 hwinfo->vendor_name[HWINFO_NAME_SIZE_BYTES - 1] = '\0'; 253 hwinfo->model_name[HWINFO_NAME_SIZE_BYTES - 1] = '\0'; 254 end: 255 return err; 256 } 257 258 int snd_efw_command_get_phys_meters(struct snd_efw *efw, 259 struct snd_efw_phys_meters *meters, 260 unsigned int len) 261 { 262 u32 *buf = (u32 *)meters; 263 unsigned int i; 264 int err; 265 266 err = efw_transaction(efw, EFC_CAT_HWINFO, 267 EFC_CMD_HWINFO_GET_POLLED, 268 NULL, 0, (__be32 *)meters, len); 269 if (err >= 0) 270 for (i = 0; i < len / sizeof(u32); i++) 271 be32_to_cpus(&buf[i]); 272 273 return err; 274 } 275 276 static int 277 command_get_clock(struct snd_efw *efw, struct efc_clock *clock) 278 { 279 int err; 280 281 err = efw_transaction(efw, EFC_CAT_HWCTL, 282 EFC_CMD_HWCTL_GET_CLOCK, 283 NULL, 0, 284 (__be32 *)clock, sizeof(struct efc_clock)); 285 if (err >= 0) { 286 be32_to_cpus(&clock->source); 287 be32_to_cpus(&clock->sampling_rate); 288 be32_to_cpus(&clock->index); 289 } 290 291 return err; 292 } 293 294 /* give UINT_MAX if set nothing */ 295 static int 296 command_set_clock(struct snd_efw *efw, 297 unsigned int source, unsigned int rate) 298 { 299 struct efc_clock clock = {0}; 300 int err; 301 302 /* check arguments */ 303 if ((source == UINT_MAX) && (rate == UINT_MAX)) { 304 err = -EINVAL; 305 goto end; 306 } 307 308 /* get current status */ 309 err = command_get_clock(efw, &clock); 310 if (err < 0) 311 goto end; 312 313 /* no need */ 314 if ((clock.source == source) && (clock.sampling_rate == rate)) 315 goto end; 316 317 /* set params */ 318 if ((source != UINT_MAX) && (clock.source != source)) 319 clock.source = source; 320 if ((rate != UINT_MAX) && (clock.sampling_rate != rate)) 321 clock.sampling_rate = rate; 322 clock.index = 0; 323 324 cpu_to_be32s(&clock.source); 325 cpu_to_be32s(&clock.sampling_rate); 326 cpu_to_be32s(&clock.index); 327 328 err = efw_transaction(efw, EFC_CAT_HWCTL, 329 EFC_CMD_HWCTL_SET_CLOCK, 330 (__be32 *)&clock, sizeof(struct efc_clock), 331 NULL, 0); 332 if (err < 0) 333 goto end; 334 335 /* 336 * With firmware version 5.8, just after changing clock state, these 337 * parameters are not immediately retrieved by get command. In my 338 * trial, there needs to be 100msec to get changed parameters. 339 */ 340 msleep(150); 341 end: 342 return err; 343 } 344 345 int snd_efw_command_get_clock_source(struct snd_efw *efw, 346 enum snd_efw_clock_source *source) 347 { 348 int err; 349 struct efc_clock clock = {0}; 350 351 err = command_get_clock(efw, &clock); 352 if (err >= 0) 353 *source = clock.source; 354 355 return err; 356 } 357 358 int snd_efw_command_get_sampling_rate(struct snd_efw *efw, unsigned int *rate) 359 { 360 int err; 361 struct efc_clock clock = {0}; 362 363 err = command_get_clock(efw, &clock); 364 if (err >= 0) 365 *rate = clock.sampling_rate; 366 367 return err; 368 } 369 370 int snd_efw_command_set_sampling_rate(struct snd_efw *efw, unsigned int rate) 371 { 372 return command_set_clock(efw, UINT_MAX, rate); 373 } 374 375