1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Audio and Music Data Transmission Protocol (IEC 61883-6) streams 4 * with Common Isochronous Packet (IEC 61883-1) headers 5 * 6 * Copyright (c) Clemens Ladisch <clemens@ladisch.de> 7 */ 8 9 #include <linux/device.h> 10 #include <linux/err.h> 11 #include <linux/firewire.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <sound/pcm.h> 15 #include <sound/pcm_params.h> 16 #include "amdtp-stream.h" 17 18 #define TICKS_PER_CYCLE 3072 19 #define CYCLES_PER_SECOND 8000 20 #define TICKS_PER_SECOND (TICKS_PER_CYCLE * CYCLES_PER_SECOND) 21 22 /* Always support Linux tracing subsystem. */ 23 #define CREATE_TRACE_POINTS 24 #include "amdtp-stream-trace.h" 25 26 #define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 microseconds */ 27 28 /* isochronous header parameters */ 29 #define ISO_DATA_LENGTH_SHIFT 16 30 #define TAG_NO_CIP_HEADER 0 31 #define TAG_CIP 1 32 33 /* common isochronous packet header parameters */ 34 #define CIP_EOH_SHIFT 31 35 #define CIP_EOH (1u << CIP_EOH_SHIFT) 36 #define CIP_EOH_MASK 0x80000000 37 #define CIP_SID_SHIFT 24 38 #define CIP_SID_MASK 0x3f000000 39 #define CIP_DBS_MASK 0x00ff0000 40 #define CIP_DBS_SHIFT 16 41 #define CIP_SPH_MASK 0x00000400 42 #define CIP_SPH_SHIFT 10 43 #define CIP_DBC_MASK 0x000000ff 44 #define CIP_FMT_SHIFT 24 45 #define CIP_FMT_MASK 0x3f000000 46 #define CIP_FDF_MASK 0x00ff0000 47 #define CIP_FDF_SHIFT 16 48 #define CIP_SYT_MASK 0x0000ffff 49 #define CIP_SYT_NO_INFO 0xffff 50 51 /* Audio and Music transfer protocol specific parameters */ 52 #define CIP_FMT_AM 0x10 53 #define AMDTP_FDF_NO_DATA 0xff 54 55 /* TODO: make these configurable */ 56 #define INTERRUPT_INTERVAL 16 57 #define QUEUE_LENGTH 48 58 59 // For iso header, tstamp and 2 CIP header. 60 #define IR_CTX_HEADER_SIZE_CIP 16 61 // For iso header and tstamp. 62 #define IR_CTX_HEADER_SIZE_NO_CIP 8 63 #define HEADER_TSTAMP_MASK 0x0000ffff 64 65 #define IT_PKT_HEADER_SIZE_CIP 8 // For 2 CIP header. 66 #define IT_PKT_HEADER_SIZE_NO_CIP 0 // Nothing. 67 68 static void pcm_period_tasklet(unsigned long data); 69 70 /** 71 * amdtp_stream_init - initialize an AMDTP stream structure 72 * @s: the AMDTP stream to initialize 73 * @unit: the target of the stream 74 * @dir: the direction of stream 75 * @flags: the packet transmission method to use 76 * @fmt: the value of fmt field in CIP header 77 * @process_ctx_payloads: callback handler to process payloads of isoc context 78 * @protocol_size: the size to allocate newly for protocol 79 */ 80 int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit, 81 enum amdtp_stream_direction dir, enum cip_flags flags, 82 unsigned int fmt, 83 amdtp_stream_process_ctx_payloads_t process_ctx_payloads, 84 unsigned int protocol_size) 85 { 86 if (process_ctx_payloads == NULL) 87 return -EINVAL; 88 89 s->protocol = kzalloc(protocol_size, GFP_KERNEL); 90 if (!s->protocol) 91 return -ENOMEM; 92 93 s->unit = unit; 94 s->direction = dir; 95 s->flags = flags; 96 s->context = ERR_PTR(-1); 97 mutex_init(&s->mutex); 98 tasklet_init(&s->period_tasklet, pcm_period_tasklet, (unsigned long)s); 99 s->packet_index = 0; 100 101 init_waitqueue_head(&s->callback_wait); 102 s->callbacked = false; 103 104 s->fmt = fmt; 105 s->process_ctx_payloads = process_ctx_payloads; 106 107 if (dir == AMDTP_OUT_STREAM) 108 s->ctx_data.rx.syt_override = -1; 109 110 return 0; 111 } 112 EXPORT_SYMBOL(amdtp_stream_init); 113 114 /** 115 * amdtp_stream_destroy - free stream resources 116 * @s: the AMDTP stream to destroy 117 */ 118 void amdtp_stream_destroy(struct amdtp_stream *s) 119 { 120 /* Not initialized. */ 121 if (s->protocol == NULL) 122 return; 123 124 WARN_ON(amdtp_stream_running(s)); 125 kfree(s->protocol); 126 mutex_destroy(&s->mutex); 127 } 128 EXPORT_SYMBOL(amdtp_stream_destroy); 129 130 const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = { 131 [CIP_SFC_32000] = 8, 132 [CIP_SFC_44100] = 8, 133 [CIP_SFC_48000] = 8, 134 [CIP_SFC_88200] = 16, 135 [CIP_SFC_96000] = 16, 136 [CIP_SFC_176400] = 32, 137 [CIP_SFC_192000] = 32, 138 }; 139 EXPORT_SYMBOL(amdtp_syt_intervals); 140 141 const unsigned int amdtp_rate_table[CIP_SFC_COUNT] = { 142 [CIP_SFC_32000] = 32000, 143 [CIP_SFC_44100] = 44100, 144 [CIP_SFC_48000] = 48000, 145 [CIP_SFC_88200] = 88200, 146 [CIP_SFC_96000] = 96000, 147 [CIP_SFC_176400] = 176400, 148 [CIP_SFC_192000] = 192000, 149 }; 150 EXPORT_SYMBOL(amdtp_rate_table); 151 152 static int apply_constraint_to_size(struct snd_pcm_hw_params *params, 153 struct snd_pcm_hw_rule *rule) 154 { 155 struct snd_interval *s = hw_param_interval(params, rule->var); 156 const struct snd_interval *r = 157 hw_param_interval_c(params, SNDRV_PCM_HW_PARAM_RATE); 158 struct snd_interval t = {0}; 159 unsigned int step = 0; 160 int i; 161 162 for (i = 0; i < CIP_SFC_COUNT; ++i) { 163 if (snd_interval_test(r, amdtp_rate_table[i])) 164 step = max(step, amdtp_syt_intervals[i]); 165 } 166 167 t.min = roundup(s->min, step); 168 t.max = rounddown(s->max, step); 169 t.integer = 1; 170 171 return snd_interval_refine(s, &t); 172 } 173 174 /** 175 * amdtp_stream_add_pcm_hw_constraints - add hw constraints for PCM substream 176 * @s: the AMDTP stream, which must be initialized. 177 * @runtime: the PCM substream runtime 178 */ 179 int amdtp_stream_add_pcm_hw_constraints(struct amdtp_stream *s, 180 struct snd_pcm_runtime *runtime) 181 { 182 struct snd_pcm_hardware *hw = &runtime->hw; 183 int err; 184 185 hw->info = SNDRV_PCM_INFO_BATCH | 186 SNDRV_PCM_INFO_BLOCK_TRANSFER | 187 SNDRV_PCM_INFO_INTERLEAVED | 188 SNDRV_PCM_INFO_JOINT_DUPLEX | 189 SNDRV_PCM_INFO_MMAP | 190 SNDRV_PCM_INFO_MMAP_VALID; 191 192 /* SNDRV_PCM_INFO_BATCH */ 193 hw->periods_min = 2; 194 hw->periods_max = UINT_MAX; 195 196 /* bytes for a frame */ 197 hw->period_bytes_min = 4 * hw->channels_max; 198 199 /* Just to prevent from allocating much pages. */ 200 hw->period_bytes_max = hw->period_bytes_min * 2048; 201 hw->buffer_bytes_max = hw->period_bytes_max * hw->periods_min; 202 203 /* 204 * Currently firewire-lib processes 16 packets in one software 205 * interrupt callback. This equals to 2msec but actually the 206 * interval of the interrupts has a jitter. 207 * Additionally, even if adding a constraint to fit period size to 208 * 2msec, actual calculated frames per period doesn't equal to 2msec, 209 * depending on sampling rate. 210 * Anyway, the interval to call snd_pcm_period_elapsed() cannot 2msec. 211 * Here let us use 5msec for safe period interrupt. 212 */ 213 err = snd_pcm_hw_constraint_minmax(runtime, 214 SNDRV_PCM_HW_PARAM_PERIOD_TIME, 215 5000, UINT_MAX); 216 if (err < 0) 217 goto end; 218 219 /* Non-Blocking stream has no more constraints */ 220 if (!(s->flags & CIP_BLOCKING)) 221 goto end; 222 223 /* 224 * One AMDTP packet can include some frames. In blocking mode, the 225 * number equals to SYT_INTERVAL. So the number is 8, 16 or 32, 226 * depending on its sampling rate. For accurate period interrupt, it's 227 * preferrable to align period/buffer sizes to current SYT_INTERVAL. 228 */ 229 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 230 apply_constraint_to_size, NULL, 231 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 232 SNDRV_PCM_HW_PARAM_RATE, -1); 233 if (err < 0) 234 goto end; 235 err = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 236 apply_constraint_to_size, NULL, 237 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 238 SNDRV_PCM_HW_PARAM_RATE, -1); 239 if (err < 0) 240 goto end; 241 end: 242 return err; 243 } 244 EXPORT_SYMBOL(amdtp_stream_add_pcm_hw_constraints); 245 246 /** 247 * amdtp_stream_set_parameters - set stream parameters 248 * @s: the AMDTP stream to configure 249 * @rate: the sample rate 250 * @data_block_quadlets: the size of a data block in quadlet unit 251 * 252 * The parameters must be set before the stream is started, and must not be 253 * changed while the stream is running. 254 */ 255 int amdtp_stream_set_parameters(struct amdtp_stream *s, unsigned int rate, 256 unsigned int data_block_quadlets) 257 { 258 unsigned int sfc; 259 260 for (sfc = 0; sfc < ARRAY_SIZE(amdtp_rate_table); ++sfc) { 261 if (amdtp_rate_table[sfc] == rate) 262 break; 263 } 264 if (sfc == ARRAY_SIZE(amdtp_rate_table)) 265 return -EINVAL; 266 267 s->sfc = sfc; 268 s->data_block_quadlets = data_block_quadlets; 269 s->syt_interval = amdtp_syt_intervals[sfc]; 270 271 // default buffering in the device. 272 if (s->direction == AMDTP_OUT_STREAM) { 273 s->ctx_data.rx.transfer_delay = 274 TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE; 275 276 if (s->flags & CIP_BLOCKING) { 277 // additional buffering needed to adjust for no-data 278 // packets. 279 s->ctx_data.rx.transfer_delay += 280 TICKS_PER_SECOND * s->syt_interval / rate; 281 } 282 } 283 284 return 0; 285 } 286 EXPORT_SYMBOL(amdtp_stream_set_parameters); 287 288 /** 289 * amdtp_stream_get_max_payload - get the stream's packet size 290 * @s: the AMDTP stream 291 * 292 * This function must not be called before the stream has been configured 293 * with amdtp_stream_set_parameters(). 294 */ 295 unsigned int amdtp_stream_get_max_payload(struct amdtp_stream *s) 296 { 297 unsigned int multiplier = 1; 298 unsigned int cip_header_size = 0; 299 300 if (s->flags & CIP_JUMBO_PAYLOAD) 301 multiplier = 5; 302 if (!(s->flags & CIP_NO_HEADER)) 303 cip_header_size = sizeof(__be32) * 2; 304 305 return cip_header_size + 306 s->syt_interval * s->data_block_quadlets * sizeof(__be32) * multiplier; 307 } 308 EXPORT_SYMBOL(amdtp_stream_get_max_payload); 309 310 /** 311 * amdtp_stream_pcm_prepare - prepare PCM device for running 312 * @s: the AMDTP stream 313 * 314 * This function should be called from the PCM device's .prepare callback. 315 */ 316 void amdtp_stream_pcm_prepare(struct amdtp_stream *s) 317 { 318 tasklet_kill(&s->period_tasklet); 319 s->pcm_buffer_pointer = 0; 320 s->pcm_period_pointer = 0; 321 } 322 EXPORT_SYMBOL(amdtp_stream_pcm_prepare); 323 324 static unsigned int calculate_data_blocks(struct amdtp_stream *s, 325 unsigned int syt) 326 { 327 unsigned int phase, data_blocks; 328 329 /* Blocking mode. */ 330 if (s->flags & CIP_BLOCKING) { 331 /* This module generate empty packet for 'no data'. */ 332 if (syt == CIP_SYT_NO_INFO) 333 data_blocks = 0; 334 else 335 data_blocks = s->syt_interval; 336 /* Non-blocking mode. */ 337 } else { 338 if (!cip_sfc_is_base_44100(s->sfc)) { 339 // Sample_rate / 8000 is an integer, and precomputed. 340 data_blocks = s->ctx_data.rx.data_block_state; 341 } else { 342 phase = s->ctx_data.rx.data_block_state; 343 344 /* 345 * This calculates the number of data blocks per packet so that 346 * 1) the overall rate is correct and exactly synchronized to 347 * the bus clock, and 348 * 2) packets with a rounded-up number of blocks occur as early 349 * as possible in the sequence (to prevent underruns of the 350 * device's buffer). 351 */ 352 if (s->sfc == CIP_SFC_44100) 353 /* 6 6 5 6 5 6 5 ... */ 354 data_blocks = 5 + ((phase & 1) ^ 355 (phase == 0 || phase >= 40)); 356 else 357 /* 12 11 11 11 11 ... or 23 22 22 22 22 ... */ 358 data_blocks = 11 * (s->sfc >> 1) + (phase == 0); 359 if (++phase >= (80 >> (s->sfc >> 1))) 360 phase = 0; 361 s->ctx_data.rx.data_block_state = phase; 362 } 363 } 364 365 return data_blocks; 366 } 367 368 static unsigned int calculate_syt(struct amdtp_stream *s, 369 unsigned int cycle) 370 { 371 unsigned int syt_offset, phase, index, syt; 372 373 if (s->ctx_data.rx.last_syt_offset < TICKS_PER_CYCLE) { 374 if (!cip_sfc_is_base_44100(s->sfc)) 375 syt_offset = s->ctx_data.rx.last_syt_offset + 376 s->ctx_data.rx.syt_offset_state; 377 else { 378 /* 379 * The time, in ticks, of the n'th SYT_INTERVAL sample is: 380 * n * SYT_INTERVAL * 24576000 / sample_rate 381 * Modulo TICKS_PER_CYCLE, the difference between successive 382 * elements is about 1386.23. Rounding the results of this 383 * formula to the SYT precision results in a sequence of 384 * differences that begins with: 385 * 1386 1386 1387 1386 1386 1386 1387 1386 1386 1386 1387 ... 386 * This code generates _exactly_ the same sequence. 387 */ 388 phase = s->ctx_data.rx.syt_offset_state; 389 index = phase % 13; 390 syt_offset = s->ctx_data.rx.last_syt_offset; 391 syt_offset += 1386 + ((index && !(index & 3)) || 392 phase == 146); 393 if (++phase >= 147) 394 phase = 0; 395 s->ctx_data.rx.syt_offset_state = phase; 396 } 397 } else 398 syt_offset = s->ctx_data.rx.last_syt_offset - TICKS_PER_CYCLE; 399 s->ctx_data.rx.last_syt_offset = syt_offset; 400 401 if (syt_offset < TICKS_PER_CYCLE) { 402 syt_offset += s->ctx_data.rx.transfer_delay; 403 syt = (cycle + syt_offset / TICKS_PER_CYCLE) << 12; 404 syt += syt_offset % TICKS_PER_CYCLE; 405 406 return syt & CIP_SYT_MASK; 407 } else { 408 return CIP_SYT_NO_INFO; 409 } 410 } 411 412 static void update_pcm_pointers(struct amdtp_stream *s, 413 struct snd_pcm_substream *pcm, 414 unsigned int frames) 415 { 416 unsigned int ptr; 417 418 ptr = s->pcm_buffer_pointer + frames; 419 if (ptr >= pcm->runtime->buffer_size) 420 ptr -= pcm->runtime->buffer_size; 421 WRITE_ONCE(s->pcm_buffer_pointer, ptr); 422 423 s->pcm_period_pointer += frames; 424 if (s->pcm_period_pointer >= pcm->runtime->period_size) { 425 s->pcm_period_pointer -= pcm->runtime->period_size; 426 tasklet_hi_schedule(&s->period_tasklet); 427 } 428 } 429 430 static void pcm_period_tasklet(unsigned long data) 431 { 432 struct amdtp_stream *s = (void *)data; 433 struct snd_pcm_substream *pcm = READ_ONCE(s->pcm); 434 435 if (pcm) 436 snd_pcm_period_elapsed(pcm); 437 } 438 439 static int queue_packet(struct amdtp_stream *s, struct fw_iso_packet *params) 440 { 441 int err; 442 443 params->interrupt = IS_ALIGNED(s->packet_index + 1, INTERRUPT_INTERVAL); 444 params->tag = s->tag; 445 params->sy = 0; 446 447 err = fw_iso_context_queue(s->context, params, &s->buffer.iso_buffer, 448 s->buffer.packets[s->packet_index].offset); 449 if (err < 0) { 450 dev_err(&s->unit->device, "queueing error: %d\n", err); 451 goto end; 452 } 453 454 if (++s->packet_index >= QUEUE_LENGTH) 455 s->packet_index = 0; 456 end: 457 return err; 458 } 459 460 static inline int queue_out_packet(struct amdtp_stream *s, 461 struct fw_iso_packet *params) 462 { 463 params->skip = 464 !!(params->header_length == 0 && params->payload_length == 0); 465 return queue_packet(s, params); 466 } 467 468 static inline int queue_in_packet(struct amdtp_stream *s, 469 struct fw_iso_packet *params) 470 { 471 // Queue one packet for IR context. 472 params->header_length = s->ctx_data.tx.ctx_header_size; 473 params->payload_length = s->ctx_data.tx.max_ctx_payload_length; 474 params->skip = false; 475 return queue_packet(s, params); 476 } 477 478 static void generate_cip_header(struct amdtp_stream *s, __be32 cip_header[2], 479 unsigned int data_block_counter, unsigned int syt) 480 { 481 cip_header[0] = cpu_to_be32(READ_ONCE(s->source_node_id_field) | 482 (s->data_block_quadlets << CIP_DBS_SHIFT) | 483 ((s->sph << CIP_SPH_SHIFT) & CIP_SPH_MASK) | 484 data_block_counter); 485 cip_header[1] = cpu_to_be32(CIP_EOH | 486 ((s->fmt << CIP_FMT_SHIFT) & CIP_FMT_MASK) | 487 ((s->ctx_data.rx.fdf << CIP_FDF_SHIFT) & CIP_FDF_MASK) | 488 (syt & CIP_SYT_MASK)); 489 } 490 491 static void build_it_pkt_header(struct amdtp_stream *s, unsigned int cycle, 492 struct fw_iso_packet *params, 493 unsigned int data_blocks, 494 unsigned int data_block_counter, 495 unsigned int syt, unsigned int index) 496 { 497 unsigned int payload_length; 498 __be32 *cip_header; 499 500 payload_length = data_blocks * sizeof(__be32) * s->data_block_quadlets; 501 params->payload_length = payload_length; 502 503 if (!(s->flags & CIP_NO_HEADER)) { 504 cip_header = (__be32 *)params->header; 505 generate_cip_header(s, cip_header, data_block_counter, syt); 506 params->header_length = 2 * sizeof(__be32); 507 payload_length += params->header_length; 508 } else { 509 cip_header = NULL; 510 } 511 512 trace_amdtp_packet(s, cycle, cip_header, payload_length, data_blocks, 513 data_block_counter, index); 514 } 515 516 static int check_cip_header(struct amdtp_stream *s, const __be32 *buf, 517 unsigned int payload_length, 518 unsigned int *data_blocks, 519 unsigned int *data_block_counter, unsigned int *syt) 520 { 521 u32 cip_header[2]; 522 unsigned int sph; 523 unsigned int fmt; 524 unsigned int fdf; 525 unsigned int dbc; 526 bool lost; 527 528 cip_header[0] = be32_to_cpu(buf[0]); 529 cip_header[1] = be32_to_cpu(buf[1]); 530 531 /* 532 * This module supports 'Two-quadlet CIP header with SYT field'. 533 * For convenience, also check FMT field is AM824 or not. 534 */ 535 if ((((cip_header[0] & CIP_EOH_MASK) == CIP_EOH) || 536 ((cip_header[1] & CIP_EOH_MASK) != CIP_EOH)) && 537 (!(s->flags & CIP_HEADER_WITHOUT_EOH))) { 538 dev_info_ratelimited(&s->unit->device, 539 "Invalid CIP header for AMDTP: %08X:%08X\n", 540 cip_header[0], cip_header[1]); 541 return -EAGAIN; 542 } 543 544 /* Check valid protocol or not. */ 545 sph = (cip_header[0] & CIP_SPH_MASK) >> CIP_SPH_SHIFT; 546 fmt = (cip_header[1] & CIP_FMT_MASK) >> CIP_FMT_SHIFT; 547 if (sph != s->sph || fmt != s->fmt) { 548 dev_info_ratelimited(&s->unit->device, 549 "Detect unexpected protocol: %08x %08x\n", 550 cip_header[0], cip_header[1]); 551 return -EAGAIN; 552 } 553 554 /* Calculate data blocks */ 555 fdf = (cip_header[1] & CIP_FDF_MASK) >> CIP_FDF_SHIFT; 556 if (payload_length < sizeof(__be32) * 2 || 557 (fmt == CIP_FMT_AM && fdf == AMDTP_FDF_NO_DATA)) { 558 *data_blocks = 0; 559 } else { 560 unsigned int data_block_quadlets = 561 (cip_header[0] & CIP_DBS_MASK) >> CIP_DBS_SHIFT; 562 /* avoid division by zero */ 563 if (data_block_quadlets == 0) { 564 dev_err(&s->unit->device, 565 "Detect invalid value in dbs field: %08X\n", 566 cip_header[0]); 567 return -EPROTO; 568 } 569 if (s->flags & CIP_WRONG_DBS) 570 data_block_quadlets = s->data_block_quadlets; 571 572 *data_blocks = (payload_length / sizeof(__be32) - 2) / 573 data_block_quadlets; 574 } 575 576 /* Check data block counter continuity */ 577 dbc = cip_header[0] & CIP_DBC_MASK; 578 if (*data_blocks == 0 && (s->flags & CIP_EMPTY_HAS_WRONG_DBC) && 579 *data_block_counter != UINT_MAX) 580 dbc = *data_block_counter; 581 582 if ((dbc == 0x00 && (s->flags & CIP_SKIP_DBC_ZERO_CHECK)) || 583 *data_block_counter == UINT_MAX) { 584 lost = false; 585 } else if (!(s->flags & CIP_DBC_IS_END_EVENT)) { 586 lost = dbc != *data_block_counter; 587 } else { 588 unsigned int dbc_interval; 589 590 if (*data_blocks > 0 && s->ctx_data.tx.dbc_interval > 0) 591 dbc_interval = s->ctx_data.tx.dbc_interval; 592 else 593 dbc_interval = *data_blocks; 594 595 lost = dbc != ((*data_block_counter + dbc_interval) & 0xff); 596 } 597 598 if (lost) { 599 dev_err(&s->unit->device, 600 "Detect discontinuity of CIP: %02X %02X\n", 601 *data_block_counter, dbc); 602 return -EIO; 603 } 604 605 *data_block_counter = dbc; 606 607 *syt = cip_header[1] & CIP_SYT_MASK; 608 609 return 0; 610 } 611 612 static int parse_ir_ctx_header(struct amdtp_stream *s, unsigned int cycle, 613 const __be32 *ctx_header, 614 unsigned int *payload_length, 615 unsigned int *data_blocks, 616 unsigned int *data_block_counter, 617 unsigned int *syt, unsigned int index) 618 { 619 const __be32 *cip_header; 620 int err; 621 622 *payload_length = be32_to_cpu(ctx_header[0]) >> ISO_DATA_LENGTH_SHIFT; 623 if (*payload_length > s->ctx_data.tx.ctx_header_size + 624 s->ctx_data.tx.max_ctx_payload_length) { 625 dev_err(&s->unit->device, 626 "Detect jumbo payload: %04x %04x\n", 627 *payload_length, s->ctx_data.tx.max_ctx_payload_length); 628 return -EIO; 629 } 630 631 if (!(s->flags & CIP_NO_HEADER)) { 632 cip_header = ctx_header + 2; 633 err = check_cip_header(s, cip_header, *payload_length, 634 data_blocks, data_block_counter, syt); 635 if (err < 0) 636 return err; 637 } else { 638 cip_header = NULL; 639 err = 0; 640 *data_blocks = *payload_length / sizeof(__be32) / 641 s->data_block_quadlets; 642 *syt = 0; 643 644 if (*data_block_counter == UINT_MAX) 645 *data_block_counter = 0; 646 } 647 648 trace_amdtp_packet(s, cycle, cip_header, *payload_length, *data_blocks, 649 *data_block_counter, index); 650 651 return err; 652 } 653 654 // In CYCLE_TIMER register of IEEE 1394, 7 bits are used to represent second. On 655 // the other hand, in DMA descriptors of 1394 OHCI, 3 bits are used to represent 656 // it. Thus, via Linux firewire subsystem, we can get the 3 bits for second. 657 static inline u32 compute_cycle_count(__be32 ctx_header_tstamp) 658 { 659 u32 tstamp = be32_to_cpu(ctx_header_tstamp) & HEADER_TSTAMP_MASK; 660 return (((tstamp >> 13) & 0x07) * 8000) + (tstamp & 0x1fff); 661 } 662 663 static inline u32 increment_cycle_count(u32 cycle, unsigned int addend) 664 { 665 cycle += addend; 666 if (cycle >= 8 * CYCLES_PER_SECOND) 667 cycle -= 8 * CYCLES_PER_SECOND; 668 return cycle; 669 } 670 671 // Align to actual cycle count for the packet which is going to be scheduled. 672 // This module queued the same number of isochronous cycle as QUEUE_LENGTH to 673 // skip isochronous cycle, therefore it's OK to just increment the cycle by 674 // QUEUE_LENGTH for scheduled cycle. 675 static inline u32 compute_it_cycle(const __be32 ctx_header_tstamp) 676 { 677 u32 cycle = compute_cycle_count(ctx_header_tstamp); 678 return increment_cycle_count(cycle, QUEUE_LENGTH); 679 } 680 681 static int generate_device_pkt_descs(struct amdtp_stream *s, 682 struct pkt_desc *descs, 683 const __be32 *ctx_header, 684 unsigned int packets) 685 { 686 unsigned int dbc = s->data_block_counter; 687 int i; 688 int err; 689 690 for (i = 0; i < packets; ++i) { 691 struct pkt_desc *desc = descs + i; 692 unsigned int index = (s->packet_index + i) % QUEUE_LENGTH; 693 unsigned int cycle; 694 unsigned int payload_length; 695 unsigned int data_blocks; 696 unsigned int syt; 697 698 cycle = compute_cycle_count(ctx_header[1]); 699 700 err = parse_ir_ctx_header(s, cycle, ctx_header, &payload_length, 701 &data_blocks, &dbc, &syt, i); 702 if (err < 0) 703 return err; 704 705 desc->cycle = cycle; 706 desc->syt = syt; 707 desc->data_blocks = data_blocks; 708 desc->data_block_counter = dbc; 709 desc->ctx_payload = s->buffer.packets[index].buffer; 710 711 if (!(s->flags & CIP_DBC_IS_END_EVENT)) 712 dbc = (dbc + desc->data_blocks) & 0xff; 713 714 ctx_header += 715 s->ctx_data.tx.ctx_header_size / sizeof(*ctx_header); 716 } 717 718 s->data_block_counter = dbc; 719 720 return 0; 721 } 722 723 static void generate_ideal_pkt_descs(struct amdtp_stream *s, 724 struct pkt_desc *descs, 725 const __be32 *ctx_header, 726 unsigned int packets) 727 { 728 unsigned int dbc = s->data_block_counter; 729 int i; 730 731 for (i = 0; i < packets; ++i) { 732 struct pkt_desc *desc = descs + i; 733 unsigned int index = (s->packet_index + i) % QUEUE_LENGTH; 734 735 desc->cycle = compute_it_cycle(*ctx_header); 736 desc->syt = calculate_syt(s, desc->cycle); 737 desc->data_blocks = calculate_data_blocks(s, desc->syt); 738 739 if (s->flags & CIP_DBC_IS_END_EVENT) 740 dbc = (dbc + desc->data_blocks) & 0xff; 741 742 desc->data_block_counter = dbc; 743 744 if (!(s->flags & CIP_DBC_IS_END_EVENT)) 745 dbc = (dbc + desc->data_blocks) & 0xff; 746 747 desc->ctx_payload = s->buffer.packets[index].buffer; 748 749 ++ctx_header; 750 } 751 752 s->data_block_counter = dbc; 753 } 754 755 static inline void cancel_stream(struct amdtp_stream *s) 756 { 757 s->packet_index = -1; 758 if (in_interrupt()) 759 amdtp_stream_pcm_abort(s); 760 WRITE_ONCE(s->pcm_buffer_pointer, SNDRV_PCM_POS_XRUN); 761 } 762 763 static void process_ctx_payloads(struct amdtp_stream *s, 764 const struct pkt_desc *descs, 765 unsigned int packets) 766 { 767 struct snd_pcm_substream *pcm; 768 unsigned int pcm_frames; 769 770 pcm = READ_ONCE(s->pcm); 771 pcm_frames = s->process_ctx_payloads(s, descs, packets, pcm); 772 if (pcm) 773 update_pcm_pointers(s, pcm, pcm_frames); 774 } 775 776 static void out_stream_callback(struct fw_iso_context *context, u32 tstamp, 777 size_t header_length, void *header, 778 void *private_data) 779 { 780 struct amdtp_stream *s = private_data; 781 const __be32 *ctx_header = header; 782 unsigned int packets = header_length / sizeof(*ctx_header); 783 int i; 784 785 if (s->packet_index < 0) 786 return; 787 788 generate_ideal_pkt_descs(s, s->pkt_descs, ctx_header, packets); 789 790 process_ctx_payloads(s, s->pkt_descs, packets); 791 792 for (i = 0; i < packets; ++i) { 793 const struct pkt_desc *desc = s->pkt_descs + i; 794 unsigned int syt; 795 struct { 796 struct fw_iso_packet params; 797 __be32 header[IT_PKT_HEADER_SIZE_CIP / sizeof(__be32)]; 798 } template = { {0}, {0} }; 799 800 if (s->ctx_data.rx.syt_override < 0) 801 syt = desc->syt; 802 else 803 syt = s->ctx_data.rx.syt_override; 804 805 build_it_pkt_header(s, desc->cycle, &template.params, 806 desc->data_blocks, desc->data_block_counter, 807 syt, i); 808 809 if (queue_out_packet(s, &template.params) < 0) { 810 cancel_stream(s); 811 return; 812 } 813 } 814 815 fw_iso_context_queue_flush(s->context); 816 } 817 818 static void in_stream_callback(struct fw_iso_context *context, u32 tstamp, 819 size_t header_length, void *header, 820 void *private_data) 821 { 822 struct amdtp_stream *s = private_data; 823 unsigned int packets; 824 __be32 *ctx_header = header; 825 int i; 826 int err; 827 828 if (s->packet_index < 0) 829 return; 830 831 // The number of packets in buffer. 832 packets = header_length / s->ctx_data.tx.ctx_header_size; 833 834 err = generate_device_pkt_descs(s, s->pkt_descs, ctx_header, packets); 835 if (err < 0) { 836 if (err != -EAGAIN) { 837 cancel_stream(s); 838 return; 839 } 840 } else { 841 process_ctx_payloads(s, s->pkt_descs, packets); 842 } 843 844 for (i = 0; i < packets; ++i) { 845 struct fw_iso_packet params = {0}; 846 847 if (queue_in_packet(s, ¶ms) < 0) { 848 cancel_stream(s); 849 return; 850 } 851 } 852 853 fw_iso_context_queue_flush(s->context); 854 } 855 856 /* this is executed one time */ 857 static void amdtp_stream_first_callback(struct fw_iso_context *context, 858 u32 tstamp, size_t header_length, 859 void *header, void *private_data) 860 { 861 struct amdtp_stream *s = private_data; 862 const __be32 *ctx_header = header; 863 u32 cycle; 864 865 /* 866 * For in-stream, first packet has come. 867 * For out-stream, prepared to transmit first packet 868 */ 869 s->callbacked = true; 870 wake_up(&s->callback_wait); 871 872 if (s->direction == AMDTP_IN_STREAM) { 873 cycle = compute_cycle_count(ctx_header[1]); 874 875 context->callback.sc = in_stream_callback; 876 } else { 877 cycle = compute_it_cycle(*ctx_header); 878 879 context->callback.sc = out_stream_callback; 880 } 881 882 s->start_cycle = cycle; 883 884 context->callback.sc(context, tstamp, header_length, header, s); 885 } 886 887 /** 888 * amdtp_stream_start - start transferring packets 889 * @s: the AMDTP stream to start 890 * @channel: the isochronous channel on the bus 891 * @speed: firewire speed code 892 * 893 * The stream cannot be started until it has been configured with 894 * amdtp_stream_set_parameters() and it must be started before any PCM or MIDI 895 * device can be started. 896 */ 897 static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed) 898 { 899 static const struct { 900 unsigned int data_block; 901 unsigned int syt_offset; 902 } *entry, initial_state[] = { 903 [CIP_SFC_32000] = { 4, 3072 }, 904 [CIP_SFC_48000] = { 6, 1024 }, 905 [CIP_SFC_96000] = { 12, 1024 }, 906 [CIP_SFC_192000] = { 24, 1024 }, 907 [CIP_SFC_44100] = { 0, 67 }, 908 [CIP_SFC_88200] = { 0, 67 }, 909 [CIP_SFC_176400] = { 0, 67 }, 910 }; 911 unsigned int ctx_header_size; 912 unsigned int max_ctx_payload_size; 913 enum dma_data_direction dir; 914 int type, tag, err; 915 916 mutex_lock(&s->mutex); 917 918 if (WARN_ON(amdtp_stream_running(s) || 919 (s->data_block_quadlets < 1))) { 920 err = -EBADFD; 921 goto err_unlock; 922 } 923 924 if (s->direction == AMDTP_IN_STREAM) { 925 s->data_block_counter = UINT_MAX; 926 } else { 927 entry = &initial_state[s->sfc]; 928 929 s->data_block_counter = 0; 930 s->ctx_data.rx.data_block_state = entry->data_block; 931 s->ctx_data.rx.syt_offset_state = entry->syt_offset; 932 s->ctx_data.rx.last_syt_offset = TICKS_PER_CYCLE; 933 } 934 935 /* initialize packet buffer */ 936 if (s->direction == AMDTP_IN_STREAM) { 937 dir = DMA_FROM_DEVICE; 938 type = FW_ISO_CONTEXT_RECEIVE; 939 if (!(s->flags & CIP_NO_HEADER)) 940 ctx_header_size = IR_CTX_HEADER_SIZE_CIP; 941 else 942 ctx_header_size = IR_CTX_HEADER_SIZE_NO_CIP; 943 944 max_ctx_payload_size = amdtp_stream_get_max_payload(s) - 945 ctx_header_size; 946 } else { 947 dir = DMA_TO_DEVICE; 948 type = FW_ISO_CONTEXT_TRANSMIT; 949 ctx_header_size = 0; // No effect for IT context. 950 951 max_ctx_payload_size = amdtp_stream_get_max_payload(s); 952 if (!(s->flags & CIP_NO_HEADER)) 953 max_ctx_payload_size -= IT_PKT_HEADER_SIZE_CIP; 954 } 955 956 err = iso_packets_buffer_init(&s->buffer, s->unit, QUEUE_LENGTH, 957 max_ctx_payload_size, dir); 958 if (err < 0) 959 goto err_unlock; 960 961 s->context = fw_iso_context_create(fw_parent_device(s->unit)->card, 962 type, channel, speed, ctx_header_size, 963 amdtp_stream_first_callback, s); 964 if (IS_ERR(s->context)) { 965 err = PTR_ERR(s->context); 966 if (err == -EBUSY) 967 dev_err(&s->unit->device, 968 "no free stream on this controller\n"); 969 goto err_buffer; 970 } 971 972 amdtp_stream_update(s); 973 974 if (s->direction == AMDTP_IN_STREAM) { 975 s->ctx_data.tx.max_ctx_payload_length = max_ctx_payload_size; 976 s->ctx_data.tx.ctx_header_size = ctx_header_size; 977 } 978 979 if (s->flags & CIP_NO_HEADER) 980 s->tag = TAG_NO_CIP_HEADER; 981 else 982 s->tag = TAG_CIP; 983 984 s->pkt_descs = kcalloc(INTERRUPT_INTERVAL, sizeof(*s->pkt_descs), 985 GFP_KERNEL); 986 if (!s->pkt_descs) { 987 err = -ENOMEM; 988 goto err_context; 989 } 990 991 s->packet_index = 0; 992 do { 993 struct fw_iso_packet params; 994 if (s->direction == AMDTP_IN_STREAM) { 995 err = queue_in_packet(s, ¶ms); 996 } else { 997 params.header_length = 0; 998 params.payload_length = 0; 999 err = queue_out_packet(s, ¶ms); 1000 } 1001 if (err < 0) 1002 goto err_pkt_descs; 1003 } while (s->packet_index > 0); 1004 1005 /* NOTE: TAG1 matches CIP. This just affects in stream. */ 1006 tag = FW_ISO_CONTEXT_MATCH_TAG1; 1007 if ((s->flags & CIP_EMPTY_WITH_TAG0) || (s->flags & CIP_NO_HEADER)) 1008 tag |= FW_ISO_CONTEXT_MATCH_TAG0; 1009 1010 s->callbacked = false; 1011 err = fw_iso_context_start(s->context, -1, 0, tag); 1012 if (err < 0) 1013 goto err_pkt_descs; 1014 1015 mutex_unlock(&s->mutex); 1016 1017 return 0; 1018 err_pkt_descs: 1019 kfree(s->pkt_descs); 1020 err_context: 1021 fw_iso_context_destroy(s->context); 1022 s->context = ERR_PTR(-1); 1023 err_buffer: 1024 iso_packets_buffer_destroy(&s->buffer, s->unit); 1025 err_unlock: 1026 mutex_unlock(&s->mutex); 1027 1028 return err; 1029 } 1030 1031 /** 1032 * amdtp_stream_pcm_pointer - get the PCM buffer position 1033 * @s: the AMDTP stream that transports the PCM data 1034 * 1035 * Returns the current buffer position, in frames. 1036 */ 1037 unsigned long amdtp_stream_pcm_pointer(struct amdtp_stream *s) 1038 { 1039 /* 1040 * This function is called in software IRQ context of period_tasklet or 1041 * process context. 1042 * 1043 * When the software IRQ context was scheduled by software IRQ context 1044 * of IR/IT contexts, queued packets were already handled. Therefore, 1045 * no need to flush the queue in buffer anymore. 1046 * 1047 * When the process context reach here, some packets will be already 1048 * queued in the buffer. These packets should be handled immediately 1049 * to keep better granularity of PCM pointer. 1050 * 1051 * Later, the process context will sometimes schedules software IRQ 1052 * context of the period_tasklet. Then, no need to flush the queue by 1053 * the same reason as described for IR/IT contexts. 1054 */ 1055 if (!in_interrupt() && amdtp_stream_running(s)) 1056 fw_iso_context_flush_completions(s->context); 1057 1058 return READ_ONCE(s->pcm_buffer_pointer); 1059 } 1060 EXPORT_SYMBOL(amdtp_stream_pcm_pointer); 1061 1062 /** 1063 * amdtp_stream_pcm_ack - acknowledge queued PCM frames 1064 * @s: the AMDTP stream that transfers the PCM frames 1065 * 1066 * Returns zero always. 1067 */ 1068 int amdtp_stream_pcm_ack(struct amdtp_stream *s) 1069 { 1070 /* 1071 * Process isochronous packets for recent isochronous cycle to handle 1072 * queued PCM frames. 1073 */ 1074 if (amdtp_stream_running(s)) 1075 fw_iso_context_flush_completions(s->context); 1076 1077 return 0; 1078 } 1079 EXPORT_SYMBOL(amdtp_stream_pcm_ack); 1080 1081 /** 1082 * amdtp_stream_update - update the stream after a bus reset 1083 * @s: the AMDTP stream 1084 */ 1085 void amdtp_stream_update(struct amdtp_stream *s) 1086 { 1087 /* Precomputing. */ 1088 WRITE_ONCE(s->source_node_id_field, 1089 (fw_parent_device(s->unit)->card->node_id << CIP_SID_SHIFT) & CIP_SID_MASK); 1090 } 1091 EXPORT_SYMBOL(amdtp_stream_update); 1092 1093 /** 1094 * amdtp_stream_stop - stop sending packets 1095 * @s: the AMDTP stream to stop 1096 * 1097 * All PCM and MIDI devices of the stream must be stopped before the stream 1098 * itself can be stopped. 1099 */ 1100 static void amdtp_stream_stop(struct amdtp_stream *s) 1101 { 1102 mutex_lock(&s->mutex); 1103 1104 if (!amdtp_stream_running(s)) { 1105 mutex_unlock(&s->mutex); 1106 return; 1107 } 1108 1109 tasklet_kill(&s->period_tasklet); 1110 fw_iso_context_stop(s->context); 1111 fw_iso_context_destroy(s->context); 1112 s->context = ERR_PTR(-1); 1113 iso_packets_buffer_destroy(&s->buffer, s->unit); 1114 kfree(s->pkt_descs); 1115 1116 s->callbacked = false; 1117 1118 mutex_unlock(&s->mutex); 1119 } 1120 1121 /** 1122 * amdtp_stream_pcm_abort - abort the running PCM device 1123 * @s: the AMDTP stream about to be stopped 1124 * 1125 * If the isochronous stream needs to be stopped asynchronously, call this 1126 * function first to stop the PCM device. 1127 */ 1128 void amdtp_stream_pcm_abort(struct amdtp_stream *s) 1129 { 1130 struct snd_pcm_substream *pcm; 1131 1132 pcm = READ_ONCE(s->pcm); 1133 if (pcm) 1134 snd_pcm_stop_xrun(pcm); 1135 } 1136 EXPORT_SYMBOL(amdtp_stream_pcm_abort); 1137 1138 /** 1139 * amdtp_domain_init - initialize an AMDTP domain structure 1140 * @d: the AMDTP domain to initialize. 1141 */ 1142 int amdtp_domain_init(struct amdtp_domain *d) 1143 { 1144 INIT_LIST_HEAD(&d->streams); 1145 1146 return 0; 1147 } 1148 EXPORT_SYMBOL_GPL(amdtp_domain_init); 1149 1150 /** 1151 * amdtp_domain_destroy - destroy an AMDTP domain structure 1152 * @d: the AMDTP domain to destroy. 1153 */ 1154 void amdtp_domain_destroy(struct amdtp_domain *d) 1155 { 1156 // At present nothing to do. 1157 return; 1158 } 1159 EXPORT_SYMBOL_GPL(amdtp_domain_destroy); 1160 1161 /** 1162 * amdtp_domain_add_stream - register isoc context into the domain. 1163 * @d: the AMDTP domain. 1164 * @s: the AMDTP stream. 1165 * @channel: the isochronous channel on the bus. 1166 * @speed: firewire speed code. 1167 */ 1168 int amdtp_domain_add_stream(struct amdtp_domain *d, struct amdtp_stream *s, 1169 int channel, int speed) 1170 { 1171 struct amdtp_stream *tmp; 1172 1173 list_for_each_entry(tmp, &d->streams, list) { 1174 if (s == tmp) 1175 return -EBUSY; 1176 } 1177 1178 list_add(&s->list, &d->streams); 1179 1180 s->channel = channel; 1181 s->speed = speed; 1182 1183 return 0; 1184 } 1185 EXPORT_SYMBOL_GPL(amdtp_domain_add_stream); 1186 1187 /** 1188 * amdtp_domain_start - start sending packets for isoc context in the domain. 1189 * @d: the AMDTP domain. 1190 */ 1191 int amdtp_domain_start(struct amdtp_domain *d) 1192 { 1193 struct amdtp_stream *s; 1194 int err = 0; 1195 1196 list_for_each_entry(s, &d->streams, list) { 1197 err = amdtp_stream_start(s, s->channel, s->speed); 1198 if (err < 0) 1199 break; 1200 } 1201 1202 if (err < 0) { 1203 list_for_each_entry(s, &d->streams, list) 1204 amdtp_stream_stop(s); 1205 } 1206 1207 return err; 1208 } 1209 EXPORT_SYMBOL_GPL(amdtp_domain_start); 1210 1211 /** 1212 * amdtp_domain_stop - stop sending packets for isoc context in the same domain. 1213 * @d: the AMDTP domain to which the isoc contexts belong. 1214 */ 1215 void amdtp_domain_stop(struct amdtp_domain *d) 1216 { 1217 struct amdtp_stream *s, *next; 1218 1219 list_for_each_entry_safe(s, next, &d->streams, list) { 1220 list_del(&s->list); 1221 1222 amdtp_stream_stop(s); 1223 } 1224 } 1225 EXPORT_SYMBOL_GPL(amdtp_domain_stop); 1226