1*cb5a6ffcSRussell King /* 2*cb5a6ffcSRussell King * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver 3*cb5a6ffcSRussell King * 4*cb5a6ffcSRussell King * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. 5*cb5a6ffcSRussell King * 6*cb5a6ffcSRussell King * This program is free software; you can redistribute it and/or modify 7*cb5a6ffcSRussell King * it under the terms of the GNU General Public License version 2 as 8*cb5a6ffcSRussell King * published by the Free Software Foundation. 9*cb5a6ffcSRussell King */ 10*cb5a6ffcSRussell King #ifndef AACI_H 11*cb5a6ffcSRussell King #define AACI_H 12*cb5a6ffcSRussell King 13*cb5a6ffcSRussell King /* 14*cb5a6ffcSRussell King * Control and status register offsets 15*cb5a6ffcSRussell King * P39. 16*cb5a6ffcSRussell King */ 17*cb5a6ffcSRussell King #define AACI_CSCH1 0x000 18*cb5a6ffcSRussell King #define AACI_CSCH2 0x014 19*cb5a6ffcSRussell King #define AACI_CSCH3 0x028 20*cb5a6ffcSRussell King #define AACI_CSCH4 0x03c 21*cb5a6ffcSRussell King 22*cb5a6ffcSRussell King #define AACI_RXCR 0x000 /* 29 bits Control Rx FIFO */ 23*cb5a6ffcSRussell King #define AACI_TXCR 0x004 /* 17 bits Control Tx FIFO */ 24*cb5a6ffcSRussell King #define AACI_SR 0x008 /* 12 bits Status */ 25*cb5a6ffcSRussell King #define AACI_ISR 0x00c /* 7 bits Int Status */ 26*cb5a6ffcSRussell King #define AACI_IE 0x010 /* 7 bits Int Enable */ 27*cb5a6ffcSRussell King 28*cb5a6ffcSRussell King /* 29*cb5a6ffcSRussell King * Other registers 30*cb5a6ffcSRussell King */ 31*cb5a6ffcSRussell King #define AACI_SL1RX 0x050 32*cb5a6ffcSRussell King #define AACI_SL1TX 0x054 33*cb5a6ffcSRussell King #define AACI_SL2RX 0x058 34*cb5a6ffcSRussell King #define AACI_SL2TX 0x05c 35*cb5a6ffcSRussell King #define AACI_SL12RX 0x060 36*cb5a6ffcSRussell King #define AACI_SL12TX 0x064 37*cb5a6ffcSRussell King #define AACI_SLFR 0x068 /* slot flags */ 38*cb5a6ffcSRussell King #define AACI_SLISTAT 0x06c /* slot interrupt status */ 39*cb5a6ffcSRussell King #define AACI_SLIEN 0x070 /* slot interrupt enable */ 40*cb5a6ffcSRussell King #define AACI_INTCLR 0x074 /* interrupt clear */ 41*cb5a6ffcSRussell King #define AACI_MAINCR 0x078 /* main control */ 42*cb5a6ffcSRussell King #define AACI_RESET 0x07c /* reset control */ 43*cb5a6ffcSRussell King #define AACI_SYNC 0x080 /* sync control */ 44*cb5a6ffcSRussell King #define AACI_ALLINTS 0x084 /* all fifo interrupt status */ 45*cb5a6ffcSRussell King #define AACI_MAINFR 0x088 /* main flag register */ 46*cb5a6ffcSRussell King #define AACI_DR1 0x090 /* data read/written fifo 1 */ 47*cb5a6ffcSRussell King #define AACI_DR2 0x0b0 /* data read/written fifo 2 */ 48*cb5a6ffcSRussell King #define AACI_DR3 0x0d0 /* data read/written fifo 3 */ 49*cb5a6ffcSRussell King #define AACI_DR4 0x0f0 /* data read/written fifo 4 */ 50*cb5a6ffcSRussell King 51*cb5a6ffcSRussell King /* 52*cb5a6ffcSRussell King * transmit fifo control register. P48 53*cb5a6ffcSRussell King */ 54*cb5a6ffcSRussell King #define TXCR_FEN (1 << 16) /* fifo enable */ 55*cb5a6ffcSRussell King #define TXCR_COMPACT (1 << 15) /* compact mode */ 56*cb5a6ffcSRussell King #define TXCR_TSZ16 (0 << 13) /* 16 bits */ 57*cb5a6ffcSRussell King #define TXCR_TSZ18 (1 << 13) /* 18 bits */ 58*cb5a6ffcSRussell King #define TXCR_TSZ20 (2 << 13) /* 20 bits */ 59*cb5a6ffcSRussell King #define TXCR_TSZ12 (3 << 13) /* 12 bits */ 60*cb5a6ffcSRussell King #define TXCR_TX12 (1 << 12) /* transmits slot 12 */ 61*cb5a6ffcSRussell King #define TXCR_TX11 (1 << 11) /* transmits slot 12 */ 62*cb5a6ffcSRussell King #define TXCR_TX10 (1 << 10) /* transmits slot 12 */ 63*cb5a6ffcSRussell King #define TXCR_TX9 (1 << 9) /* transmits slot 12 */ 64*cb5a6ffcSRussell King #define TXCR_TX8 (1 << 8) /* transmits slot 12 */ 65*cb5a6ffcSRussell King #define TXCR_TX7 (1 << 7) /* transmits slot 12 */ 66*cb5a6ffcSRussell King #define TXCR_TX6 (1 << 6) /* transmits slot 12 */ 67*cb5a6ffcSRussell King #define TXCR_TX5 (1 << 5) /* transmits slot 12 */ 68*cb5a6ffcSRussell King #define TXCR_TX4 (1 << 4) /* transmits slot 12 */ 69*cb5a6ffcSRussell King #define TXCR_TX3 (1 << 3) /* transmits slot 12 */ 70*cb5a6ffcSRussell King #define TXCR_TX2 (1 << 2) /* transmits slot 12 */ 71*cb5a6ffcSRussell King #define TXCR_TX1 (1 << 1) /* transmits slot 12 */ 72*cb5a6ffcSRussell King #define TXCR_TXEN (1 << 0) /* transmit enable */ 73*cb5a6ffcSRussell King 74*cb5a6ffcSRussell King /* 75*cb5a6ffcSRussell King * status register bits. P49 76*cb5a6ffcSRussell King */ 77*cb5a6ffcSRussell King #define SR_RXTOFE (1 << 11) /* rx timeout fifo empty */ 78*cb5a6ffcSRussell King #define SR_TXTO (1 << 10) /* rx timeout fifo nonempty */ 79*cb5a6ffcSRussell King #define SR_TXU (1 << 9) /* tx underrun */ 80*cb5a6ffcSRussell King #define SR_RXO (1 << 8) /* rx overrun */ 81*cb5a6ffcSRussell King #define SR_TXB (1 << 7) /* tx busy */ 82*cb5a6ffcSRussell King #define SR_RXB (1 << 6) /* rx busy */ 83*cb5a6ffcSRussell King #define SR_TXFF (1 << 5) /* tx fifo full */ 84*cb5a6ffcSRussell King #define SR_RXFF (1 << 4) /* rx fifo full */ 85*cb5a6ffcSRussell King #define SR_TXHE (1 << 3) /* tx fifo half empty */ 86*cb5a6ffcSRussell King #define SR_RXHF (1 << 2) /* rx fifo half full */ 87*cb5a6ffcSRussell King #define SR_TXFE (1 << 1) /* tx fifo empty */ 88*cb5a6ffcSRussell King #define SR_RXFE (1 << 0) /* rx fifo empty */ 89*cb5a6ffcSRussell King 90*cb5a6ffcSRussell King /* 91*cb5a6ffcSRussell King * interrupt status register bits. 92*cb5a6ffcSRussell King */ 93*cb5a6ffcSRussell King #define ISR_RXTOFEINTR (1 << 6) /* rx fifo empty */ 94*cb5a6ffcSRussell King #define ISR_URINTR (1 << 5) /* tx underflow */ 95*cb5a6ffcSRussell King #define ISR_ORINTR (1 << 4) /* rx overflow */ 96*cb5a6ffcSRussell King #define ISR_RXINTR (1 << 3) /* rx fifo */ 97*cb5a6ffcSRussell King #define ISR_TXINTR (1 << 2) /* tx fifo intr */ 98*cb5a6ffcSRussell King #define ISR_RXTOINTR (1 << 1) /* tx timeout */ 99*cb5a6ffcSRussell King #define ISR_TXCINTR (1 << 0) /* tx complete */ 100*cb5a6ffcSRussell King 101*cb5a6ffcSRussell King /* 102*cb5a6ffcSRussell King * interrupt enable register bits. 103*cb5a6ffcSRussell King */ 104*cb5a6ffcSRussell King #define IE_RXTOIE (1 << 6) 105*cb5a6ffcSRussell King #define IE_URIE (1 << 5) 106*cb5a6ffcSRussell King #define IE_ORIE (1 << 4) 107*cb5a6ffcSRussell King #define IE_RXIE (1 << 3) 108*cb5a6ffcSRussell King #define IE_TXIE (1 << 2) 109*cb5a6ffcSRussell King #define IE_RXTIE (1 << 1) 110*cb5a6ffcSRussell King #define IE_TXCIE (1 << 0) 111*cb5a6ffcSRussell King 112*cb5a6ffcSRussell King /* 113*cb5a6ffcSRussell King * interrupt status. P51 114*cb5a6ffcSRussell King */ 115*cb5a6ffcSRussell King #define ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */ 116*cb5a6ffcSRussell King #define ISR_UR (1 << 5) /* tx fifo underrun */ 117*cb5a6ffcSRussell King #define ISR_OR (1 << 4) /* rx fifo overrun */ 118*cb5a6ffcSRussell King #define ISR_RX (1 << 3) /* rx interrupt status */ 119*cb5a6ffcSRussell King #define ISR_TX (1 << 2) /* tx interrupt status */ 120*cb5a6ffcSRussell King #define ISR_RXTO (1 << 1) /* rx timeout */ 121*cb5a6ffcSRussell King #define ISR_TXC (1 << 0) /* tx complete */ 122*cb5a6ffcSRussell King 123*cb5a6ffcSRussell King /* 124*cb5a6ffcSRussell King * interrupt enable. P52 125*cb5a6ffcSRussell King */ 126*cb5a6ffcSRussell King #define IE_RXTOFE (1 << 6) /* rx timeout fifo empty */ 127*cb5a6ffcSRussell King #define IE_UR (1 << 5) /* tx fifo underrun */ 128*cb5a6ffcSRussell King #define IE_OR (1 << 4) /* rx fifo overrun */ 129*cb5a6ffcSRussell King #define IE_RX (1 << 3) /* rx interrupt status */ 130*cb5a6ffcSRussell King #define IE_TX (1 << 2) /* tx interrupt status */ 131*cb5a6ffcSRussell King #define IE_RXTO (1 << 1) /* rx timeout */ 132*cb5a6ffcSRussell King #define IE_TXC (1 << 0) /* tx complete */ 133*cb5a6ffcSRussell King 134*cb5a6ffcSRussell King /* 135*cb5a6ffcSRussell King * slot flag register bits. P56 136*cb5a6ffcSRussell King */ 137*cb5a6ffcSRussell King #define SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */ 138*cb5a6ffcSRussell King #define SLFR_RGPIOINTR (1 << 12) /* raw gpio interrupt */ 139*cb5a6ffcSRussell King #define SLFR_12TXE (1 << 11) /* slot 12 tx empty */ 140*cb5a6ffcSRussell King #define SLFR_12RXV (1 << 10) /* slot 12 rx valid */ 141*cb5a6ffcSRussell King #define SLFR_2TXE (1 << 9) /* slot 2 tx empty */ 142*cb5a6ffcSRussell King #define SLFR_2RXV (1 << 8) /* slot 2 rx valid */ 143*cb5a6ffcSRussell King #define SLFR_1TXE (1 << 7) /* slot 1 tx empty */ 144*cb5a6ffcSRussell King #define SLFR_1RXV (1 << 6) /* slot 1 rx valid */ 145*cb5a6ffcSRussell King #define SLFR_12TXB (1 << 5) /* slot 12 tx busy */ 146*cb5a6ffcSRussell King #define SLFR_12RXB (1 << 4) /* slot 12 rx busy */ 147*cb5a6ffcSRussell King #define SLFR_2TXB (1 << 3) /* slot 2 tx busy */ 148*cb5a6ffcSRussell King #define SLFR_2RXB (1 << 2) /* slot 2 rx busy */ 149*cb5a6ffcSRussell King #define SLFR_1TXB (1 << 1) /* slot 1 tx busy */ 150*cb5a6ffcSRussell King #define SLFR_1RXB (1 << 0) /* slot 1 rx busy */ 151*cb5a6ffcSRussell King 152*cb5a6ffcSRussell King /* 153*cb5a6ffcSRussell King * Interrupt clear register. 154*cb5a6ffcSRussell King */ 155*cb5a6ffcSRussell King #define ICLR_RXTOFEC4 (1 << 12) 156*cb5a6ffcSRussell King #define ICLR_RXTOFEC3 (1 << 11) 157*cb5a6ffcSRussell King #define ICLR_RXTOFEC2 (1 << 10) 158*cb5a6ffcSRussell King #define ICLR_RXTOFEC1 (1 << 9) 159*cb5a6ffcSRussell King #define ICLR_TXUEC4 (1 << 8) 160*cb5a6ffcSRussell King #define ICLR_TXUEC3 (1 << 7) 161*cb5a6ffcSRussell King #define ICLR_TXUEC2 (1 << 6) 162*cb5a6ffcSRussell King #define ICLR_TXUEC1 (1 << 5) 163*cb5a6ffcSRussell King #define ICLR_RXOEC4 (1 << 4) 164*cb5a6ffcSRussell King #define ICLR_RXOEC3 (1 << 3) 165*cb5a6ffcSRussell King #define ICLR_RXOEC2 (1 << 2) 166*cb5a6ffcSRussell King #define ICLR_RXOEC1 (1 << 1) 167*cb5a6ffcSRussell King #define ICLR_WISC (1 << 0) 168*cb5a6ffcSRussell King 169*cb5a6ffcSRussell King /* 170*cb5a6ffcSRussell King * Main control register bits. P62 171*cb5a6ffcSRussell King */ 172*cb5a6ffcSRussell King #define MAINCR_SCRA(x) ((x) << 10) /* secondary codec reg access */ 173*cb5a6ffcSRussell King #define MAINCR_DMAEN (1 << 9) /* dma enable */ 174*cb5a6ffcSRussell King #define MAINCR_SL12TXEN (1 << 8) /* slot 12 transmit enable */ 175*cb5a6ffcSRussell King #define MAINCR_SL12RXEN (1 << 7) /* slot 12 receive enable */ 176*cb5a6ffcSRussell King #define MAINCR_SL2TXEN (1 << 6) /* slot 2 transmit enable */ 177*cb5a6ffcSRussell King #define MAINCR_SL2RXEN (1 << 5) /* slot 2 receive enable */ 178*cb5a6ffcSRussell King #define MAINCR_SL1TXEN (1 << 4) /* slot 1 transmit enable */ 179*cb5a6ffcSRussell King #define MAINCR_SL1RXEN (1 << 3) /* slot 1 receive enable */ 180*cb5a6ffcSRussell King #define MAINCR_LPM (1 << 2) /* low power mode */ 181*cb5a6ffcSRussell King #define MAINCR_LOOPBK (1 << 1) /* loopback */ 182*cb5a6ffcSRussell King #define MAINCR_IE (1 << 0) /* aaci interface enable */ 183*cb5a6ffcSRussell King 184*cb5a6ffcSRussell King /* 185*cb5a6ffcSRussell King * Reset register bits. P65 186*cb5a6ffcSRussell King */ 187*cb5a6ffcSRussell King #define RESET_NRST (1 << 0) 188*cb5a6ffcSRussell King 189*cb5a6ffcSRussell King /* 190*cb5a6ffcSRussell King * Sync register bits. P65 191*cb5a6ffcSRussell King */ 192*cb5a6ffcSRussell King #define SYNC_FORCE (1 << 0) 193*cb5a6ffcSRussell King 194*cb5a6ffcSRussell King /* 195*cb5a6ffcSRussell King * Main flag register bits. P66 196*cb5a6ffcSRussell King */ 197*cb5a6ffcSRussell King #define MAINFR_TXB (1 << 1) /* transmit busy */ 198*cb5a6ffcSRussell King #define MAINFR_RXB (1 << 0) /* receive busy */ 199*cb5a6ffcSRussell King 200*cb5a6ffcSRussell King 201*cb5a6ffcSRussell King 202*cb5a6ffcSRussell King struct aaci_runtime { 203*cb5a6ffcSRussell King void *base; 204*cb5a6ffcSRussell King void *fifo; 205*cb5a6ffcSRussell King 206*cb5a6ffcSRussell King struct ac97_pcm *pcm; 207*cb5a6ffcSRussell King int pcm_open; 208*cb5a6ffcSRussell King 209*cb5a6ffcSRussell King u32 cr; 210*cb5a6ffcSRussell King snd_pcm_substream_t *substream; 211*cb5a6ffcSRussell King 212*cb5a6ffcSRussell King /* 213*cb5a6ffcSRussell King * PIO support 214*cb5a6ffcSRussell King */ 215*cb5a6ffcSRussell King void *start; 216*cb5a6ffcSRussell King void *end; 217*cb5a6ffcSRussell King void *ptr; 218*cb5a6ffcSRussell King int bytes; 219*cb5a6ffcSRussell King unsigned int period; 220*cb5a6ffcSRussell King unsigned int fifosz; 221*cb5a6ffcSRussell King }; 222*cb5a6ffcSRussell King 223*cb5a6ffcSRussell King struct aaci { 224*cb5a6ffcSRussell King struct amba_device *dev; 225*cb5a6ffcSRussell King snd_card_t *card; 226*cb5a6ffcSRussell King void *base; 227*cb5a6ffcSRussell King unsigned int fifosize; 228*cb5a6ffcSRussell King 229*cb5a6ffcSRussell King /* AC'97 */ 230*cb5a6ffcSRussell King struct semaphore ac97_sem; 231*cb5a6ffcSRussell King ac97_bus_t *ac97_bus; 232*cb5a6ffcSRussell King 233*cb5a6ffcSRussell King u32 maincr; 234*cb5a6ffcSRussell King spinlock_t lock; 235*cb5a6ffcSRussell King 236*cb5a6ffcSRussell King struct aaci_runtime playback; 237*cb5a6ffcSRussell King struct aaci_runtime capture; 238*cb5a6ffcSRussell King 239*cb5a6ffcSRussell King snd_pcm_t *pcm; 240*cb5a6ffcSRussell King }; 241*cb5a6ffcSRussell King 242*cb5a6ffcSRussell King #define ACSTREAM_FRONT 0 243*cb5a6ffcSRussell King #define ACSTREAM_SURROUND 1 244*cb5a6ffcSRussell King #define ACSTREAM_LFE 2 245*cb5a6ffcSRussell King 246*cb5a6ffcSRussell King #endif 247