xref: /linux/scripts/dtc/include-prefixes/riscv/starfive/jh7110.dtsi (revision e2c510d6d630fe6593a0cf87531913b4b08ebeb1)

// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
 * Copyright (C) 2022 StarFive Technology Co., Ltd.
 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
 */

/dts-v1/;
#include <dt-bindings/clock/starfive,jh7110-crg.h>
#include <dt-bindings/reset/starfive,jh7110-crg.h>

/ {
	compatible = "starfive,jh7110";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		S7_0: cpu@0 {
			compatible = "sifive,s7", "riscv";
			reg = <0>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <16384>;
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imac_zba_zbb";
			status = "disabled";

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		U74_1: cpu@1 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <1>;
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <40>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <40>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			operating-points-v2 = <&cpu_opp>;
			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
			clock-names = "cpu";

			cpu1_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		U74_2: cpu@2 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <2>;
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <40>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <40>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			operating-points-v2 = <&cpu_opp>;
			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
			clock-names = "cpu";

			cpu2_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		U74_3: cpu@3 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <3>;
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <40>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <40>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			operating-points-v2 = <&cpu_opp>;
			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
			clock-names = "cpu";

			cpu3_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		U74_4: cpu@4 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <4>;
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <40>;
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <64>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <40>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			operating-points-v2 = <&cpu_opp>;
			clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
			clock-names = "cpu";

			cpu4_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&S7_0>;
				};

				core1 {
					cpu = <&U74_1>;
				};

				core2 {
					cpu = <&U74_2>;
				};

				core3 {
					cpu = <&U74_3>;
				};

				core4 {
					cpu = <&U74_4>;
				};
			};
		};
	};

	cpu_opp: opp-table-0 {
			compatible = "operating-points-v2";
			opp-shared;
			opp-375000000 {
					opp-hz = /bits/ 64 <375000000>;
					opp-microvolt = <800000>;
			};
			opp-500000000 {
					opp-hz = /bits/ 64 <500000000>;
					opp-microvolt = <800000>;
			};
			opp-750000000 {
					opp-hz = /bits/ 64 <750000000>;
					opp-microvolt = <800000>;
			};
			opp-1500000000 {
					opp-hz = /bits/ 64 <1500000000>;
					opp-microvolt = <1040000>;
			};
	};

	gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
		compatible = "fixed-clock";
		clock-output-names = "gmac0_rgmii_rxin";
		#clock-cells = <0>;
	};

	gmac0_rmii_refin: gmac0-rmii-refin-clock {
		compatible = "fixed-clock";
		clock-output-names = "gmac0_rmii_refin";
		#clock-cells = <0>;
	};

	gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
		compatible = "fixed-clock";
		clock-output-names = "gmac1_rgmii_rxin";
		#clock-cells = <0>;
	};

	gmac1_rmii_refin: gmac1-rmii-refin-clock {
		compatible = "fixed-clock";
		clock-output-names = "gmac1_rmii_refin";
		#clock-cells = <0>;
	};

	i2srx_bclk_ext: i2srx-bclk-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "i2srx_bclk_ext";
		#clock-cells = <0>;
	};

	i2srx_lrck_ext: i2srx-lrck-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "i2srx_lrck_ext";
		#clock-cells = <0>;
	};

	i2stx_bclk_ext: i2stx-bclk-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "i2stx_bclk_ext";
		#clock-cells = <0>;
	};

	i2stx_lrck_ext: i2stx-lrck-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "i2stx_lrck_ext";
		#clock-cells = <0>;
	};

	mclk_ext: mclk-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "mclk_ext";
		#clock-cells = <0>;
	};

	osc: oscillator {
		compatible = "fixed-clock";
		clock-output-names = "osc";
		#clock-cells = <0>;
	};

	rtc_osc: rtc-oscillator {
		compatible = "fixed-clock";
		clock-output-names = "rtc_osc";
		#clock-cells = <0>;
	};

	tdm_ext: tdm-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "tdm_ext";
		#clock-cells = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&plic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		clint: timer@2000000 {
			compatible = "starfive,jh7110-clint", "sifive,clint0";
			reg = <0x0 0x2000000 0x0 0x10000>;
			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
					      <&cpu1_intc 3>, <&cpu1_intc 7>,
					      <&cpu2_intc 3>, <&cpu2_intc 7>,
					      <&cpu3_intc 3>, <&cpu3_intc 7>,
					      <&cpu4_intc 3>, <&cpu4_intc 7>;
		};

		ccache: cache-controller@2010000 {
			compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
			reg = <0x0 0x2010000 0x0 0x4000>;
			interrupts = <1>, <3>, <4>, <2>;
			cache-block-size = <64>;
			cache-level = <2>;
			cache-sets = <2048>;
			cache-size = <2097152>;
			cache-unified;
		};

		plic: interrupt-controller@c000000 {
			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
			reg = <0x0 0xc000000 0x0 0x4000000>;
			interrupts-extended = <&cpu0_intc 11>,
					      <&cpu1_intc 11>, <&cpu1_intc 9>,
					      <&cpu2_intc 11>, <&cpu2_intc 9>,
					      <&cpu3_intc 11>, <&cpu3_intc 9>,
					      <&cpu4_intc 11>, <&cpu4_intc 9>;
			interrupt-controller;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			riscv,ndev = <136>;
		};

		uart0: serial@10000000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x10000000 0x0 0x10000>;
			clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
				 <&syscrg JH7110_SYSCLK_UART0_APB>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&syscrg JH7110_SYSRST_UART0_APB>;
			interrupts = <32>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart1: serial@10010000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x10010000 0x0 0x10000>;
			clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
				 <&syscrg JH7110_SYSCLK_UART1_APB>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&syscrg JH7110_SYSRST_UART1_APB>;
			interrupts = <33>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart2: serial@10020000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x10020000 0x0 0x10000>;
			clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
				 <&syscrg JH7110_SYSCLK_UART2_APB>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&syscrg JH7110_SYSRST_UART2_APB>;
			interrupts = <34>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		i2c0: i2c@10030000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0x10030000 0x0 0x10000>;
			clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
			clock-names = "ref";
			resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
			interrupts = <35>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@10040000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0x10040000 0x0 0x10000>;
			clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
			clock-names = "ref";
			resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
			interrupts = <36>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@10050000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0x10050000 0x0 0x10000>;
			clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
			clock-names = "ref";
			resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
			interrupts = <37>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		uart3: serial@12000000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x12000000 0x0 0x10000>;
			clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
				 <&syscrg JH7110_SYSCLK_UART3_APB>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&syscrg JH7110_SYSRST_UART3_APB>;
			interrupts = <45>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart4: serial@12010000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x12010000 0x0 0x10000>;
			clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
				 <&syscrg JH7110_SYSCLK_UART4_APB>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&syscrg JH7110_SYSRST_UART4_APB>;
			interrupts = <46>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart5: serial@12020000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x12020000 0x0 0x10000>;
			clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
				 <&syscrg JH7110_SYSCLK_UART5_APB>;
			clock-names = "baudclk", "apb_pclk";
			resets = <&syscrg JH7110_SYSRST_UART5_APB>;
			interrupts = <47>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		i2c3: i2c@12030000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0x12030000 0x0 0x10000>;
			clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
			clock-names = "ref";
			resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
			interrupts = <48>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c4: i2c@12040000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0x12040000 0x0 0x10000>;
			clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
			clock-names = "ref";
			resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
			interrupts = <49>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c5: i2c@12050000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0x12050000 0x0 0x10000>;
			clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
			clock-names = "ref";
			resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
			interrupts = <50>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c6: i2c@12060000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0x12060000 0x0 0x10000>;
			clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
			clock-names = "ref";
			resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
			interrupts = <51>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		syscrg: clock-controller@13020000 {
			compatible = "starfive,jh7110-syscrg";
			reg = <0x0 0x13020000 0x0 0x10000>;
			clocks = <&osc>, <&gmac1_rmii_refin>,
				 <&gmac1_rgmii_rxin>,
				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
				 <&tdm_ext>, <&mclk_ext>;
			clock-names = "osc", "gmac1_rmii_refin",
				      "gmac1_rgmii_rxin",
				      "i2stx_bclk_ext", "i2stx_lrck_ext",
				      "i2srx_bclk_ext", "i2srx_lrck_ext",
				      "tdm_ext", "mclk_ext";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		sysgpio: pinctrl@13040000 {
			compatible = "starfive,jh7110-sys-pinctrl";
			reg = <0x0 0x13040000 0x0 0x10000>;
			clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
			resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
			interrupts = <86>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		watchdog@13070000 {
			compatible = "starfive,jh7110-wdt";
			reg = <0x0 0x13070000 0x0 0x10000>;
			clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
				 <&syscrg JH7110_SYSCLK_WDT_CORE>;
			clock-names = "apb", "core";
			resets = <&syscrg JH7110_SYSRST_WDT_APB>,
				 <&syscrg JH7110_SYSRST_WDT_CORE>;
		};

		aoncrg: clock-controller@17000000 {
			compatible = "starfive,jh7110-aoncrg";
			reg = <0x0 0x17000000 0x0 0x10000>;
			clocks = <&osc>, <&gmac0_rmii_refin>,
				 <&gmac0_rgmii_rxin>,
				 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
				 <&syscrg JH7110_SYSCLK_APB_BUS>,
				 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
				 <&rtc_osc>;
			clock-names = "osc", "gmac0_rmii_refin",
				      "gmac0_rgmii_rxin", "stg_axiahb",
				      "apb_bus", "gmac0_gtxclk",
				      "rtc_osc";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		aongpio: pinctrl@17020000 {
			compatible = "starfive,jh7110-aon-pinctrl";
			reg = <0x0 0x17020000 0x0 0x10000>;
			resets = <&aoncrg JH7110_AONRST_IOMUX>;
			interrupts = <85>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
		};

		pwrc: power-controller@17030000 {
			compatible = "starfive,jh7110-pmu";
			reg = <0x0 0x17030000 0x0 0x10000>;
			interrupts = <111>;
			#power-domain-cells = <1>;
		};
	};
};