19276baddSJisheng Zhang// SPDX-License-Identifier: GPL-2.0 OR MIT 29276baddSJisheng Zhang/* 39276baddSJisheng Zhang * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 49276baddSJisheng Zhang */ 59276baddSJisheng Zhang 69276baddSJisheng Zhang/dts-v1/; 79276baddSJisheng Zhang#include "jh7110-common.dtsi" 89276baddSJisheng Zhang 99276baddSJisheng Zhang/ { 109276baddSJisheng Zhang model = "Milk-V Mars"; 119276baddSJisheng Zhang compatible = "milkv,mars", "starfive,jh7110"; 129276baddSJisheng Zhang}; 139276baddSJisheng Zhang 149276baddSJisheng Zhang&gmac0 { 159276baddSJisheng Zhang starfive,tx-use-rgmii-clk; 169276baddSJisheng Zhang assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; 179276baddSJisheng Zhang assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; 189276baddSJisheng Zhang}; 199276baddSJisheng Zhang 20*2904244aSMinda Chen&pcie0 { 21*2904244aSMinda Chen status = "okay"; 22*2904244aSMinda Chen}; 23*2904244aSMinda Chen 24*2904244aSMinda Chen&pcie1 { 25*2904244aSMinda Chen status = "okay"; 26*2904244aSMinda Chen}; 279276baddSJisheng Zhang 289276baddSJisheng Zhang&phy0 { 299276baddSJisheng Zhang motorcomm,tx-clk-adj-enabled; 309276baddSJisheng Zhang motorcomm,tx-clk-10-inverted; 319276baddSJisheng Zhang motorcomm,tx-clk-100-inverted; 329276baddSJisheng Zhang motorcomm,tx-clk-1000-inverted; 339276baddSJisheng Zhang motorcomm,rx-clk-drv-microamp = <3970>; 349276baddSJisheng Zhang motorcomm,rx-data-drv-microamp = <2910>; 359276baddSJisheng Zhang rx-internal-delay-ps = <1500>; 369276baddSJisheng Zhang tx-internal-delay-ps = <1500>; 379276baddSJisheng Zhang}; 38