1ac9a37e2SJisheng Zhang// SPDX-License-Identifier: GPL-2.0 OR MIT 2ac9a37e2SJisheng Zhang/* 3ac9a37e2SJisheng Zhang * Copyright (C) 2022 StarFive Technology Co., Ltd. 4ac9a37e2SJisheng Zhang * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 5ac9a37e2SJisheng Zhang */ 6ac9a37e2SJisheng Zhang 7ac9a37e2SJisheng Zhang/dts-v1/; 8ac9a37e2SJisheng Zhang#include "jh7110.dtsi" 9ac9a37e2SJisheng Zhang#include "jh7110-pinfunc.h" 10ac9a37e2SJisheng Zhang#include <dt-bindings/gpio/gpio.h> 11ac9a37e2SJisheng Zhang 12ac9a37e2SJisheng Zhang/ { 13ac9a37e2SJisheng Zhang aliases { 14ac9a37e2SJisheng Zhang ethernet0 = &gmac0; 15ac9a37e2SJisheng Zhang i2c0 = &i2c0; 16ac9a37e2SJisheng Zhang i2c2 = &i2c2; 17ac9a37e2SJisheng Zhang i2c5 = &i2c5; 18ac9a37e2SJisheng Zhang i2c6 = &i2c6; 19ac9a37e2SJisheng Zhang mmc0 = &mmc0; 20ac9a37e2SJisheng Zhang mmc1 = &mmc1; 21ac9a37e2SJisheng Zhang serial0 = &uart0; 22ac9a37e2SJisheng Zhang }; 23ac9a37e2SJisheng Zhang 24ac9a37e2SJisheng Zhang chosen { 25ac9a37e2SJisheng Zhang stdout-path = "serial0:115200n8"; 26ac9a37e2SJisheng Zhang }; 27ac9a37e2SJisheng Zhang 28ac9a37e2SJisheng Zhang memory@40000000 { 29ac9a37e2SJisheng Zhang device_type = "memory"; 30ac9a37e2SJisheng Zhang reg = <0x0 0x40000000 0x1 0x0>; 31ac9a37e2SJisheng Zhang }; 32ac9a37e2SJisheng Zhang 33ac9a37e2SJisheng Zhang gpio-restart { 34ac9a37e2SJisheng Zhang compatible = "gpio-restart"; 35ac9a37e2SJisheng Zhang gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; 36ac9a37e2SJisheng Zhang priority = <224>; 37ac9a37e2SJisheng Zhang }; 38ac9a37e2SJisheng Zhang 39ac9a37e2SJisheng Zhang pwmdac_codec: audio-codec { 40ac9a37e2SJisheng Zhang compatible = "linux,spdif-dit"; 41ac9a37e2SJisheng Zhang #sound-dai-cells = <0>; 42ac9a37e2SJisheng Zhang }; 43ac9a37e2SJisheng Zhang 44ac9a37e2SJisheng Zhang sound { 45ac9a37e2SJisheng Zhang compatible = "simple-audio-card"; 46ac9a37e2SJisheng Zhang simple-audio-card,name = "StarFive-PWMDAC-Sound-Card"; 47ac9a37e2SJisheng Zhang #address-cells = <1>; 48ac9a37e2SJisheng Zhang #size-cells = <0>; 49ac9a37e2SJisheng Zhang 50ac9a37e2SJisheng Zhang simple-audio-card,dai-link@0 { 51ac9a37e2SJisheng Zhang reg = <0>; 52ac9a37e2SJisheng Zhang format = "left_j"; 53ac9a37e2SJisheng Zhang bitclock-master = <&sndcpu0>; 54ac9a37e2SJisheng Zhang frame-master = <&sndcpu0>; 55ac9a37e2SJisheng Zhang 56ac9a37e2SJisheng Zhang sndcpu0: cpu { 57ac9a37e2SJisheng Zhang sound-dai = <&pwmdac>; 58ac9a37e2SJisheng Zhang }; 59ac9a37e2SJisheng Zhang 60ac9a37e2SJisheng Zhang codec { 61ac9a37e2SJisheng Zhang sound-dai = <&pwmdac_codec>; 62ac9a37e2SJisheng Zhang }; 63ac9a37e2SJisheng Zhang }; 64ac9a37e2SJisheng Zhang }; 65ac9a37e2SJisheng Zhang}; 66ac9a37e2SJisheng Zhang 67ac9a37e2SJisheng Zhang&cpus { 68ac9a37e2SJisheng Zhang timebase-frequency = <4000000>; 69ac9a37e2SJisheng Zhang}; 70ac9a37e2SJisheng Zhang 71ac9a37e2SJisheng Zhang&dvp_clk { 72ac9a37e2SJisheng Zhang clock-frequency = <74250000>; 73ac9a37e2SJisheng Zhang}; 74ac9a37e2SJisheng Zhang 75ac9a37e2SJisheng Zhang&gmac0_rgmii_rxin { 76ac9a37e2SJisheng Zhang clock-frequency = <125000000>; 77ac9a37e2SJisheng Zhang}; 78ac9a37e2SJisheng Zhang 79ac9a37e2SJisheng Zhang&gmac0_rmii_refin { 80ac9a37e2SJisheng Zhang clock-frequency = <50000000>; 81ac9a37e2SJisheng Zhang}; 82ac9a37e2SJisheng Zhang 83ac9a37e2SJisheng Zhang&gmac1_rgmii_rxin { 84ac9a37e2SJisheng Zhang clock-frequency = <125000000>; 85ac9a37e2SJisheng Zhang}; 86ac9a37e2SJisheng Zhang 87ac9a37e2SJisheng Zhang&gmac1_rmii_refin { 88ac9a37e2SJisheng Zhang clock-frequency = <50000000>; 89ac9a37e2SJisheng Zhang}; 90ac9a37e2SJisheng Zhang 91ac9a37e2SJisheng Zhang&hdmitx0_pixelclk { 92ac9a37e2SJisheng Zhang clock-frequency = <297000000>; 93ac9a37e2SJisheng Zhang}; 94ac9a37e2SJisheng Zhang 95ac9a37e2SJisheng Zhang&i2srx_bclk_ext { 96ac9a37e2SJisheng Zhang clock-frequency = <12288000>; 97ac9a37e2SJisheng Zhang}; 98ac9a37e2SJisheng Zhang 99ac9a37e2SJisheng Zhang&i2srx_lrck_ext { 100ac9a37e2SJisheng Zhang clock-frequency = <192000>; 101ac9a37e2SJisheng Zhang}; 102ac9a37e2SJisheng Zhang 103ac9a37e2SJisheng Zhang&i2stx_bclk_ext { 104ac9a37e2SJisheng Zhang clock-frequency = <12288000>; 105ac9a37e2SJisheng Zhang}; 106ac9a37e2SJisheng Zhang 107ac9a37e2SJisheng Zhang&i2stx_lrck_ext { 108ac9a37e2SJisheng Zhang clock-frequency = <192000>; 109ac9a37e2SJisheng Zhang}; 110ac9a37e2SJisheng Zhang 111ac9a37e2SJisheng Zhang&mclk_ext { 112ac9a37e2SJisheng Zhang clock-frequency = <12288000>; 113ac9a37e2SJisheng Zhang}; 114ac9a37e2SJisheng Zhang 115ac9a37e2SJisheng Zhang&osc { 116ac9a37e2SJisheng Zhang clock-frequency = <24000000>; 117ac9a37e2SJisheng Zhang}; 118ac9a37e2SJisheng Zhang 119ac9a37e2SJisheng Zhang&rtc_osc { 120ac9a37e2SJisheng Zhang clock-frequency = <32768>; 121ac9a37e2SJisheng Zhang}; 122ac9a37e2SJisheng Zhang 123ac9a37e2SJisheng Zhang&tdm_ext { 124ac9a37e2SJisheng Zhang clock-frequency = <49152000>; 125ac9a37e2SJisheng Zhang}; 126ac9a37e2SJisheng Zhang 127ac9a37e2SJisheng Zhang&camss { 128ac9a37e2SJisheng Zhang assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>, 129ac9a37e2SJisheng Zhang <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>; 130ac9a37e2SJisheng Zhang assigned-clock-rates = <49500000>, <198000000>; 131ac9a37e2SJisheng Zhang status = "okay"; 132ac9a37e2SJisheng Zhang 133ac9a37e2SJisheng Zhang ports { 134ac9a37e2SJisheng Zhang #address-cells = <1>; 135ac9a37e2SJisheng Zhang #size-cells = <0>; 136ac9a37e2SJisheng Zhang 137ac9a37e2SJisheng Zhang port@0 { 138ac9a37e2SJisheng Zhang reg = <0>; 139ac9a37e2SJisheng Zhang }; 140ac9a37e2SJisheng Zhang 141ac9a37e2SJisheng Zhang port@1 { 142ac9a37e2SJisheng Zhang reg = <1>; 143ac9a37e2SJisheng Zhang 144ac9a37e2SJisheng Zhang camss_from_csi2rx: endpoint { 145ac9a37e2SJisheng Zhang remote-endpoint = <&csi2rx_to_camss>; 146ac9a37e2SJisheng Zhang }; 147ac9a37e2SJisheng Zhang }; 148ac9a37e2SJisheng Zhang }; 149ac9a37e2SJisheng Zhang}; 150ac9a37e2SJisheng Zhang 151ac9a37e2SJisheng Zhang&csi2rx { 152ac9a37e2SJisheng Zhang assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>; 153ac9a37e2SJisheng Zhang assigned-clock-rates = <297000000>; 154ac9a37e2SJisheng Zhang status = "okay"; 155ac9a37e2SJisheng Zhang 156ac9a37e2SJisheng Zhang ports { 157ac9a37e2SJisheng Zhang #address-cells = <1>; 158ac9a37e2SJisheng Zhang #size-cells = <0>; 159ac9a37e2SJisheng Zhang 160ac9a37e2SJisheng Zhang port@0 { 161ac9a37e2SJisheng Zhang reg = <0>; 162ac9a37e2SJisheng Zhang 163ac9a37e2SJisheng Zhang /* remote MIPI sensor endpoint */ 164ac9a37e2SJisheng Zhang }; 165ac9a37e2SJisheng Zhang 166ac9a37e2SJisheng Zhang port@1 { 167ac9a37e2SJisheng Zhang reg = <1>; 168ac9a37e2SJisheng Zhang 169ac9a37e2SJisheng Zhang csi2rx_to_camss: endpoint { 170ac9a37e2SJisheng Zhang remote-endpoint = <&camss_from_csi2rx>; 171ac9a37e2SJisheng Zhang }; 172ac9a37e2SJisheng Zhang }; 173ac9a37e2SJisheng Zhang }; 174ac9a37e2SJisheng Zhang}; 175ac9a37e2SJisheng Zhang 176ac9a37e2SJisheng Zhang&gmac0 { 177ac9a37e2SJisheng Zhang phy-handle = <&phy0>; 178ac9a37e2SJisheng Zhang phy-mode = "rgmii-id"; 179ac9a37e2SJisheng Zhang status = "okay"; 180ac9a37e2SJisheng Zhang 181ac9a37e2SJisheng Zhang mdio { 182ac9a37e2SJisheng Zhang #address-cells = <1>; 183ac9a37e2SJisheng Zhang #size-cells = <0>; 184ac9a37e2SJisheng Zhang compatible = "snps,dwmac-mdio"; 185ac9a37e2SJisheng Zhang 186ac9a37e2SJisheng Zhang phy0: ethernet-phy@0 { 187ac9a37e2SJisheng Zhang reg = <0>; 188ac9a37e2SJisheng Zhang }; 189ac9a37e2SJisheng Zhang }; 190ac9a37e2SJisheng Zhang}; 191ac9a37e2SJisheng Zhang 192ac9a37e2SJisheng Zhang&i2c0 { 193ac9a37e2SJisheng Zhang clock-frequency = <100000>; 194ac9a37e2SJisheng Zhang i2c-sda-hold-time-ns = <300>; 195ac9a37e2SJisheng Zhang i2c-sda-falling-time-ns = <510>; 196ac9a37e2SJisheng Zhang i2c-scl-falling-time-ns = <510>; 197ac9a37e2SJisheng Zhang pinctrl-names = "default"; 198ac9a37e2SJisheng Zhang pinctrl-0 = <&i2c0_pins>; 199ac9a37e2SJisheng Zhang status = "okay"; 200ac9a37e2SJisheng Zhang}; 201ac9a37e2SJisheng Zhang 202ac9a37e2SJisheng Zhang&i2c2 { 203ac9a37e2SJisheng Zhang clock-frequency = <100000>; 204ac9a37e2SJisheng Zhang i2c-sda-hold-time-ns = <300>; 205ac9a37e2SJisheng Zhang i2c-sda-falling-time-ns = <510>; 206ac9a37e2SJisheng Zhang i2c-scl-falling-time-ns = <510>; 207ac9a37e2SJisheng Zhang pinctrl-names = "default"; 208ac9a37e2SJisheng Zhang pinctrl-0 = <&i2c2_pins>; 209ac9a37e2SJisheng Zhang status = "okay"; 210ac9a37e2SJisheng Zhang}; 211ac9a37e2SJisheng Zhang 212ac9a37e2SJisheng Zhang&i2c5 { 213ac9a37e2SJisheng Zhang clock-frequency = <100000>; 214ac9a37e2SJisheng Zhang i2c-sda-hold-time-ns = <300>; 215ac9a37e2SJisheng Zhang i2c-sda-falling-time-ns = <510>; 216ac9a37e2SJisheng Zhang i2c-scl-falling-time-ns = <510>; 217ac9a37e2SJisheng Zhang pinctrl-names = "default"; 218ac9a37e2SJisheng Zhang pinctrl-0 = <&i2c5_pins>; 219ac9a37e2SJisheng Zhang status = "okay"; 220ac9a37e2SJisheng Zhang 221ac9a37e2SJisheng Zhang axp15060: pmic@36 { 222ac9a37e2SJisheng Zhang compatible = "x-powers,axp15060"; 223ac9a37e2SJisheng Zhang reg = <0x36>; 224ac9a37e2SJisheng Zhang interrupt-controller; 225ac9a37e2SJisheng Zhang #interrupt-cells = <1>; 226ac9a37e2SJisheng Zhang 227ac9a37e2SJisheng Zhang regulators { 228ac9a37e2SJisheng Zhang vcc_3v3: dcdc1 { 229ac9a37e2SJisheng Zhang regulator-boot-on; 230ac9a37e2SJisheng Zhang regulator-always-on; 231ac9a37e2SJisheng Zhang regulator-min-microvolt = <3300000>; 232ac9a37e2SJisheng Zhang regulator-max-microvolt = <3300000>; 233ac9a37e2SJisheng Zhang regulator-name = "vcc_3v3"; 234ac9a37e2SJisheng Zhang }; 235ac9a37e2SJisheng Zhang 236ac9a37e2SJisheng Zhang vdd_cpu: dcdc2 { 237ac9a37e2SJisheng Zhang regulator-always-on; 238ac9a37e2SJisheng Zhang regulator-min-microvolt = <500000>; 239ac9a37e2SJisheng Zhang regulator-max-microvolt = <1540000>; 240ac9a37e2SJisheng Zhang regulator-name = "vdd-cpu"; 241ac9a37e2SJisheng Zhang }; 242ac9a37e2SJisheng Zhang 243ac9a37e2SJisheng Zhang emmc_vdd: aldo4 { 244ac9a37e2SJisheng Zhang regulator-boot-on; 245ac9a37e2SJisheng Zhang regulator-always-on; 246ac9a37e2SJisheng Zhang regulator-min-microvolt = <1800000>; 247ac9a37e2SJisheng Zhang regulator-max-microvolt = <1800000>; 248ac9a37e2SJisheng Zhang regulator-name = "emmc_vdd"; 249ac9a37e2SJisheng Zhang }; 250ac9a37e2SJisheng Zhang }; 251ac9a37e2SJisheng Zhang }; 252ac9a37e2SJisheng Zhang}; 253ac9a37e2SJisheng Zhang 254ac9a37e2SJisheng Zhang&i2c6 { 255ac9a37e2SJisheng Zhang clock-frequency = <100000>; 256ac9a37e2SJisheng Zhang i2c-sda-hold-time-ns = <300>; 257ac9a37e2SJisheng Zhang i2c-sda-falling-time-ns = <510>; 258ac9a37e2SJisheng Zhang i2c-scl-falling-time-ns = <510>; 259ac9a37e2SJisheng Zhang pinctrl-names = "default"; 260ac9a37e2SJisheng Zhang pinctrl-0 = <&i2c6_pins>; 261ac9a37e2SJisheng Zhang status = "okay"; 262ac9a37e2SJisheng Zhang}; 263ac9a37e2SJisheng Zhang 264ac9a37e2SJisheng Zhang&mmc0 { 265ac9a37e2SJisheng Zhang max-frequency = <100000000>; 266ac9a37e2SJisheng Zhang assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; 267ac9a37e2SJisheng Zhang assigned-clock-rates = <50000000>; 268ac9a37e2SJisheng Zhang bus-width = <8>; 269ac9a37e2SJisheng Zhang cap-mmc-highspeed; 270ac9a37e2SJisheng Zhang mmc-ddr-1_8v; 271ac9a37e2SJisheng Zhang mmc-hs200-1_8v; 272ac9a37e2SJisheng Zhang cap-mmc-hw-reset; 273ac9a37e2SJisheng Zhang post-power-on-delay-ms = <200>; 274ac9a37e2SJisheng Zhang pinctrl-names = "default"; 275ac9a37e2SJisheng Zhang pinctrl-0 = <&mmc0_pins>; 276ac9a37e2SJisheng Zhang vmmc-supply = <&vcc_3v3>; 277ac9a37e2SJisheng Zhang vqmmc-supply = <&emmc_vdd>; 278ac9a37e2SJisheng Zhang status = "okay"; 279ac9a37e2SJisheng Zhang}; 280ac9a37e2SJisheng Zhang 281ac9a37e2SJisheng Zhang&mmc1 { 282ac9a37e2SJisheng Zhang max-frequency = <100000000>; 283ac9a37e2SJisheng Zhang assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; 284ac9a37e2SJisheng Zhang assigned-clock-rates = <50000000>; 285ac9a37e2SJisheng Zhang bus-width = <4>; 286ac9a37e2SJisheng Zhang no-sdio; 287ac9a37e2SJisheng Zhang no-mmc; 288ac9a37e2SJisheng Zhang cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; 289ac9a37e2SJisheng Zhang disable-wp; 290ac9a37e2SJisheng Zhang cap-sd-highspeed; 291ac9a37e2SJisheng Zhang post-power-on-delay-ms = <200>; 292ac9a37e2SJisheng Zhang pinctrl-names = "default"; 293ac9a37e2SJisheng Zhang pinctrl-0 = <&mmc1_pins>; 294ac9a37e2SJisheng Zhang status = "okay"; 295ac9a37e2SJisheng Zhang}; 296ac9a37e2SJisheng Zhang 297ac9a37e2SJisheng Zhang&pwmdac { 298ac9a37e2SJisheng Zhang pinctrl-names = "default"; 299ac9a37e2SJisheng Zhang pinctrl-0 = <&pwmdac_pins>; 300ac9a37e2SJisheng Zhang status = "okay"; 301ac9a37e2SJisheng Zhang}; 302ac9a37e2SJisheng Zhang 303ac9a37e2SJisheng Zhang&qspi { 304ac9a37e2SJisheng Zhang #address-cells = <1>; 305ac9a37e2SJisheng Zhang #size-cells = <0>; 306ac9a37e2SJisheng Zhang status = "okay"; 307ac9a37e2SJisheng Zhang 308ac9a37e2SJisheng Zhang nor_flash: flash@0 { 309ac9a37e2SJisheng Zhang compatible = "jedec,spi-nor"; 310ac9a37e2SJisheng Zhang reg = <0>; 311ac9a37e2SJisheng Zhang cdns,read-delay = <5>; 312ac9a37e2SJisheng Zhang spi-max-frequency = <12000000>; 313ac9a37e2SJisheng Zhang cdns,tshsl-ns = <1>; 314ac9a37e2SJisheng Zhang cdns,tsd2d-ns = <1>; 315ac9a37e2SJisheng Zhang cdns,tchsh-ns = <1>; 316ac9a37e2SJisheng Zhang cdns,tslch-ns = <1>; 317ac9a37e2SJisheng Zhang 318ac9a37e2SJisheng Zhang partitions { 319ac9a37e2SJisheng Zhang compatible = "fixed-partitions"; 320ac9a37e2SJisheng Zhang #address-cells = <1>; 321ac9a37e2SJisheng Zhang #size-cells = <1>; 322ac9a37e2SJisheng Zhang 323ac9a37e2SJisheng Zhang spl@0 { 324*edbce932SMatthias Brugger reg = <0x0 0xf0000>; 325ac9a37e2SJisheng Zhang }; 326ac9a37e2SJisheng Zhang uboot-env@f0000 { 327ac9a37e2SJisheng Zhang reg = <0xf0000 0x10000>; 328ac9a37e2SJisheng Zhang }; 329ac9a37e2SJisheng Zhang uboot@100000 { 330*edbce932SMatthias Brugger reg = <0x100000 0xf00000>; 331ac9a37e2SJisheng Zhang }; 332ac9a37e2SJisheng Zhang }; 333ac9a37e2SJisheng Zhang }; 334ac9a37e2SJisheng Zhang}; 335ac9a37e2SJisheng Zhang 336ac9a37e2SJisheng Zhang&pwm { 337ac9a37e2SJisheng Zhang pinctrl-names = "default"; 338ac9a37e2SJisheng Zhang pinctrl-0 = <&pwm_pins>; 339ac9a37e2SJisheng Zhang status = "okay"; 340ac9a37e2SJisheng Zhang}; 341ac9a37e2SJisheng Zhang 342ac9a37e2SJisheng Zhang&spi0 { 343ac9a37e2SJisheng Zhang pinctrl-names = "default"; 344ac9a37e2SJisheng Zhang pinctrl-0 = <&spi0_pins>; 345ac9a37e2SJisheng Zhang status = "okay"; 346ac9a37e2SJisheng Zhang 347ac9a37e2SJisheng Zhang spi_dev0: spi@0 { 348ac9a37e2SJisheng Zhang compatible = "rohm,dh2228fv"; 349ac9a37e2SJisheng Zhang reg = <0>; 350ac9a37e2SJisheng Zhang spi-max-frequency = <10000000>; 351ac9a37e2SJisheng Zhang }; 352ac9a37e2SJisheng Zhang}; 353ac9a37e2SJisheng Zhang 354ac9a37e2SJisheng Zhang&sysgpio { 355ac9a37e2SJisheng Zhang i2c0_pins: i2c0-0 { 356ac9a37e2SJisheng Zhang i2c-pins { 357ac9a37e2SJisheng Zhang pinmux = <GPIOMUX(57, GPOUT_LOW, 358ac9a37e2SJisheng Zhang GPOEN_SYS_I2C0_CLK, 359ac9a37e2SJisheng Zhang GPI_SYS_I2C0_CLK)>, 360ac9a37e2SJisheng Zhang <GPIOMUX(58, GPOUT_LOW, 361ac9a37e2SJisheng Zhang GPOEN_SYS_I2C0_DATA, 362ac9a37e2SJisheng Zhang GPI_SYS_I2C0_DATA)>; 363ac9a37e2SJisheng Zhang bias-disable; /* external pull-up */ 364ac9a37e2SJisheng Zhang input-enable; 365ac9a37e2SJisheng Zhang input-schmitt-enable; 366ac9a37e2SJisheng Zhang }; 367ac9a37e2SJisheng Zhang }; 368ac9a37e2SJisheng Zhang 369ac9a37e2SJisheng Zhang i2c2_pins: i2c2-0 { 370ac9a37e2SJisheng Zhang i2c-pins { 371ac9a37e2SJisheng Zhang pinmux = <GPIOMUX(3, GPOUT_LOW, 372ac9a37e2SJisheng Zhang GPOEN_SYS_I2C2_CLK, 373ac9a37e2SJisheng Zhang GPI_SYS_I2C2_CLK)>, 374ac9a37e2SJisheng Zhang <GPIOMUX(2, GPOUT_LOW, 375ac9a37e2SJisheng Zhang GPOEN_SYS_I2C2_DATA, 376ac9a37e2SJisheng Zhang GPI_SYS_I2C2_DATA)>; 377ac9a37e2SJisheng Zhang bias-disable; /* external pull-up */ 378ac9a37e2SJisheng Zhang input-enable; 379ac9a37e2SJisheng Zhang input-schmitt-enable; 380ac9a37e2SJisheng Zhang }; 381ac9a37e2SJisheng Zhang }; 382ac9a37e2SJisheng Zhang 383ac9a37e2SJisheng Zhang i2c5_pins: i2c5-0 { 384ac9a37e2SJisheng Zhang i2c-pins { 385ac9a37e2SJisheng Zhang pinmux = <GPIOMUX(19, GPOUT_LOW, 386ac9a37e2SJisheng Zhang GPOEN_SYS_I2C5_CLK, 387ac9a37e2SJisheng Zhang GPI_SYS_I2C5_CLK)>, 388ac9a37e2SJisheng Zhang <GPIOMUX(20, GPOUT_LOW, 389ac9a37e2SJisheng Zhang GPOEN_SYS_I2C5_DATA, 390ac9a37e2SJisheng Zhang GPI_SYS_I2C5_DATA)>; 391ac9a37e2SJisheng Zhang bias-disable; /* external pull-up */ 392ac9a37e2SJisheng Zhang input-enable; 393ac9a37e2SJisheng Zhang input-schmitt-enable; 394ac9a37e2SJisheng Zhang }; 395ac9a37e2SJisheng Zhang }; 396ac9a37e2SJisheng Zhang 397ac9a37e2SJisheng Zhang i2c6_pins: i2c6-0 { 398ac9a37e2SJisheng Zhang i2c-pins { 399ac9a37e2SJisheng Zhang pinmux = <GPIOMUX(16, GPOUT_LOW, 400ac9a37e2SJisheng Zhang GPOEN_SYS_I2C6_CLK, 401ac9a37e2SJisheng Zhang GPI_SYS_I2C6_CLK)>, 402ac9a37e2SJisheng Zhang <GPIOMUX(17, GPOUT_LOW, 403ac9a37e2SJisheng Zhang GPOEN_SYS_I2C6_DATA, 404ac9a37e2SJisheng Zhang GPI_SYS_I2C6_DATA)>; 405ac9a37e2SJisheng Zhang bias-disable; /* external pull-up */ 406ac9a37e2SJisheng Zhang input-enable; 407ac9a37e2SJisheng Zhang input-schmitt-enable; 408ac9a37e2SJisheng Zhang }; 409ac9a37e2SJisheng Zhang }; 410ac9a37e2SJisheng Zhang 411ac9a37e2SJisheng Zhang mmc0_pins: mmc0-0 { 412ac9a37e2SJisheng Zhang rst-pins { 413ac9a37e2SJisheng Zhang pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, 414ac9a37e2SJisheng Zhang GPOEN_ENABLE, 415ac9a37e2SJisheng Zhang GPI_NONE)>; 416ac9a37e2SJisheng Zhang bias-pull-up; 417ac9a37e2SJisheng Zhang drive-strength = <12>; 418ac9a37e2SJisheng Zhang input-disable; 419ac9a37e2SJisheng Zhang input-schmitt-disable; 420ac9a37e2SJisheng Zhang slew-rate = <0>; 421ac9a37e2SJisheng Zhang }; 422ac9a37e2SJisheng Zhang 423ac9a37e2SJisheng Zhang mmc-pins { 424ac9a37e2SJisheng Zhang pinmux = <PINMUX(64, 0)>, 425ac9a37e2SJisheng Zhang <PINMUX(65, 0)>, 426ac9a37e2SJisheng Zhang <PINMUX(66, 0)>, 427ac9a37e2SJisheng Zhang <PINMUX(67, 0)>, 428ac9a37e2SJisheng Zhang <PINMUX(68, 0)>, 429ac9a37e2SJisheng Zhang <PINMUX(69, 0)>, 430ac9a37e2SJisheng Zhang <PINMUX(70, 0)>, 431ac9a37e2SJisheng Zhang <PINMUX(71, 0)>, 432ac9a37e2SJisheng Zhang <PINMUX(72, 0)>, 433ac9a37e2SJisheng Zhang <PINMUX(73, 0)>; 434ac9a37e2SJisheng Zhang bias-pull-up; 435ac9a37e2SJisheng Zhang drive-strength = <12>; 436ac9a37e2SJisheng Zhang input-enable; 437ac9a37e2SJisheng Zhang }; 438ac9a37e2SJisheng Zhang }; 439ac9a37e2SJisheng Zhang 440ac9a37e2SJisheng Zhang mmc1_pins: mmc1-0 { 441ac9a37e2SJisheng Zhang clk-pins { 442ac9a37e2SJisheng Zhang pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK, 443ac9a37e2SJisheng Zhang GPOEN_ENABLE, 444ac9a37e2SJisheng Zhang GPI_NONE)>; 445ac9a37e2SJisheng Zhang bias-pull-up; 446ac9a37e2SJisheng Zhang drive-strength = <12>; 447ac9a37e2SJisheng Zhang input-disable; 448ac9a37e2SJisheng Zhang input-schmitt-disable; 449ac9a37e2SJisheng Zhang slew-rate = <0>; 450ac9a37e2SJisheng Zhang }; 451ac9a37e2SJisheng Zhang 452ac9a37e2SJisheng Zhang mmc-pins { 453ac9a37e2SJisheng Zhang pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD, 454ac9a37e2SJisheng Zhang GPOEN_SYS_SDIO1_CMD, 455ac9a37e2SJisheng Zhang GPI_SYS_SDIO1_CMD)>, 456ac9a37e2SJisheng Zhang <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0, 457ac9a37e2SJisheng Zhang GPOEN_SYS_SDIO1_DATA0, 458ac9a37e2SJisheng Zhang GPI_SYS_SDIO1_DATA0)>, 459ac9a37e2SJisheng Zhang <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1, 460ac9a37e2SJisheng Zhang GPOEN_SYS_SDIO1_DATA1, 461ac9a37e2SJisheng Zhang GPI_SYS_SDIO1_DATA1)>, 462ac9a37e2SJisheng Zhang <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2, 463ac9a37e2SJisheng Zhang GPOEN_SYS_SDIO1_DATA2, 464ac9a37e2SJisheng Zhang GPI_SYS_SDIO1_DATA2)>, 465ac9a37e2SJisheng Zhang <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3, 466ac9a37e2SJisheng Zhang GPOEN_SYS_SDIO1_DATA3, 467ac9a37e2SJisheng Zhang GPI_SYS_SDIO1_DATA3)>; 468ac9a37e2SJisheng Zhang bias-pull-up; 469ac9a37e2SJisheng Zhang drive-strength = <12>; 470ac9a37e2SJisheng Zhang input-enable; 471ac9a37e2SJisheng Zhang input-schmitt-enable; 472ac9a37e2SJisheng Zhang slew-rate = <0>; 473ac9a37e2SJisheng Zhang }; 474ac9a37e2SJisheng Zhang }; 475ac9a37e2SJisheng Zhang 476ac9a37e2SJisheng Zhang pwmdac_pins: pwmdac-0 { 477ac9a37e2SJisheng Zhang pwmdac-pins { 478ac9a37e2SJisheng Zhang pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT, 479ac9a37e2SJisheng Zhang GPOEN_ENABLE, 480ac9a37e2SJisheng Zhang GPI_NONE)>, 481ac9a37e2SJisheng Zhang <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT, 482ac9a37e2SJisheng Zhang GPOEN_ENABLE, 483ac9a37e2SJisheng Zhang GPI_NONE)>; 484ac9a37e2SJisheng Zhang bias-disable; 485ac9a37e2SJisheng Zhang drive-strength = <2>; 486ac9a37e2SJisheng Zhang input-disable; 487ac9a37e2SJisheng Zhang input-schmitt-disable; 488ac9a37e2SJisheng Zhang slew-rate = <0>; 489ac9a37e2SJisheng Zhang }; 490ac9a37e2SJisheng Zhang }; 491ac9a37e2SJisheng Zhang 492ac9a37e2SJisheng Zhang pwm_pins: pwm-0 { 493ac9a37e2SJisheng Zhang pwm-pins { 494ac9a37e2SJisheng Zhang pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0, 495ac9a37e2SJisheng Zhang GPOEN_SYS_PWM0_CHANNEL0, 496ac9a37e2SJisheng Zhang GPI_NONE)>, 497ac9a37e2SJisheng Zhang <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1, 498ac9a37e2SJisheng Zhang GPOEN_SYS_PWM0_CHANNEL1, 499ac9a37e2SJisheng Zhang GPI_NONE)>; 500ac9a37e2SJisheng Zhang bias-disable; 501ac9a37e2SJisheng Zhang drive-strength = <12>; 502ac9a37e2SJisheng Zhang input-disable; 503ac9a37e2SJisheng Zhang input-schmitt-disable; 504ac9a37e2SJisheng Zhang slew-rate = <0>; 505ac9a37e2SJisheng Zhang }; 506ac9a37e2SJisheng Zhang }; 507ac9a37e2SJisheng Zhang 508ac9a37e2SJisheng Zhang spi0_pins: spi0-0 { 509ac9a37e2SJisheng Zhang mosi-pins { 510ac9a37e2SJisheng Zhang pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD, 511ac9a37e2SJisheng Zhang GPOEN_ENABLE, 512ac9a37e2SJisheng Zhang GPI_NONE)>; 513ac9a37e2SJisheng Zhang bias-disable; 514ac9a37e2SJisheng Zhang input-disable; 515ac9a37e2SJisheng Zhang input-schmitt-disable; 516ac9a37e2SJisheng Zhang }; 517ac9a37e2SJisheng Zhang 518ac9a37e2SJisheng Zhang miso-pins { 519ac9a37e2SJisheng Zhang pinmux = <GPIOMUX(53, GPOUT_LOW, 520ac9a37e2SJisheng Zhang GPOEN_DISABLE, 521ac9a37e2SJisheng Zhang GPI_SYS_SPI0_RXD)>; 522ac9a37e2SJisheng Zhang bias-pull-up; 523ac9a37e2SJisheng Zhang input-enable; 524ac9a37e2SJisheng Zhang input-schmitt-enable; 525ac9a37e2SJisheng Zhang }; 526ac9a37e2SJisheng Zhang 527ac9a37e2SJisheng Zhang sck-pins { 528ac9a37e2SJisheng Zhang pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK, 529ac9a37e2SJisheng Zhang GPOEN_ENABLE, 530ac9a37e2SJisheng Zhang GPI_SYS_SPI0_CLK)>; 531ac9a37e2SJisheng Zhang bias-disable; 532ac9a37e2SJisheng Zhang input-disable; 533ac9a37e2SJisheng Zhang input-schmitt-disable; 534ac9a37e2SJisheng Zhang }; 535ac9a37e2SJisheng Zhang 536ac9a37e2SJisheng Zhang ss-pins { 537ac9a37e2SJisheng Zhang pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS, 538ac9a37e2SJisheng Zhang GPOEN_ENABLE, 539ac9a37e2SJisheng Zhang GPI_SYS_SPI0_FSS)>; 540ac9a37e2SJisheng Zhang bias-disable; 541ac9a37e2SJisheng Zhang input-disable; 542ac9a37e2SJisheng Zhang input-schmitt-disable; 543ac9a37e2SJisheng Zhang }; 544ac9a37e2SJisheng Zhang }; 545ac9a37e2SJisheng Zhang 546ac9a37e2SJisheng Zhang uart0_pins: uart0-0 { 547ac9a37e2SJisheng Zhang tx-pins { 548ac9a37e2SJisheng Zhang pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, 549ac9a37e2SJisheng Zhang GPOEN_ENABLE, 550ac9a37e2SJisheng Zhang GPI_NONE)>; 551ac9a37e2SJisheng Zhang bias-disable; 552ac9a37e2SJisheng Zhang drive-strength = <12>; 553ac9a37e2SJisheng Zhang input-disable; 554ac9a37e2SJisheng Zhang input-schmitt-disable; 555ac9a37e2SJisheng Zhang slew-rate = <0>; 556ac9a37e2SJisheng Zhang }; 557ac9a37e2SJisheng Zhang 558ac9a37e2SJisheng Zhang rx-pins { 559ac9a37e2SJisheng Zhang pinmux = <GPIOMUX(6, GPOUT_LOW, 560ac9a37e2SJisheng Zhang GPOEN_DISABLE, 561ac9a37e2SJisheng Zhang GPI_SYS_UART0_RX)>; 562ac9a37e2SJisheng Zhang bias-disable; /* external pull-up */ 563ac9a37e2SJisheng Zhang drive-strength = <2>; 564ac9a37e2SJisheng Zhang input-enable; 565ac9a37e2SJisheng Zhang input-schmitt-enable; 566ac9a37e2SJisheng Zhang slew-rate = <0>; 567ac9a37e2SJisheng Zhang }; 568ac9a37e2SJisheng Zhang }; 569ac9a37e2SJisheng Zhang}; 570ac9a37e2SJisheng Zhang 571ac9a37e2SJisheng Zhang&uart0 { 572ac9a37e2SJisheng Zhang pinctrl-names = "default"; 573ac9a37e2SJisheng Zhang pinctrl-0 = <&uart0_pins>; 574ac9a37e2SJisheng Zhang status = "okay"; 575ac9a37e2SJisheng Zhang}; 576ac9a37e2SJisheng Zhang 577ac9a37e2SJisheng Zhang&usb0 { 578ac9a37e2SJisheng Zhang dr_mode = "peripheral"; 579ac9a37e2SJisheng Zhang status = "okay"; 580ac9a37e2SJisheng Zhang}; 581ac9a37e2SJisheng Zhang 582ac9a37e2SJisheng Zhang&U74_1 { 583ac9a37e2SJisheng Zhang cpu-supply = <&vdd_cpu>; 584ac9a37e2SJisheng Zhang}; 585ac9a37e2SJisheng Zhang 586ac9a37e2SJisheng Zhang&U74_2 { 587ac9a37e2SJisheng Zhang cpu-supply = <&vdd_cpu>; 588ac9a37e2SJisheng Zhang}; 589ac9a37e2SJisheng Zhang 590ac9a37e2SJisheng Zhang&U74_3 { 591ac9a37e2SJisheng Zhang cpu-supply = <&vdd_cpu>; 592ac9a37e2SJisheng Zhang}; 593ac9a37e2SJisheng Zhang 594ac9a37e2SJisheng Zhang&U74_4 { 595ac9a37e2SJisheng Zhang cpu-supply = <&vdd_cpu>; 596ac9a37e2SJisheng Zhang}; 597