xref: /linux/scripts/dtc/include-prefixes/riscv/starfive/jh7110-common.dtsi (revision ac9a37e2d6b6373d657366a365d9e05b32221e3d)
1*ac9a37e2SJisheng Zhang// SPDX-License-Identifier: GPL-2.0 OR MIT
2*ac9a37e2SJisheng Zhang/*
3*ac9a37e2SJisheng Zhang * Copyright (C) 2022 StarFive Technology Co., Ltd.
4*ac9a37e2SJisheng Zhang * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5*ac9a37e2SJisheng Zhang */
6*ac9a37e2SJisheng Zhang
7*ac9a37e2SJisheng Zhang/dts-v1/;
8*ac9a37e2SJisheng Zhang#include "jh7110.dtsi"
9*ac9a37e2SJisheng Zhang#include "jh7110-pinfunc.h"
10*ac9a37e2SJisheng Zhang#include <dt-bindings/gpio/gpio.h>
11*ac9a37e2SJisheng Zhang
12*ac9a37e2SJisheng Zhang/ {
13*ac9a37e2SJisheng Zhang	aliases {
14*ac9a37e2SJisheng Zhang		ethernet0 = &gmac0;
15*ac9a37e2SJisheng Zhang		i2c0 = &i2c0;
16*ac9a37e2SJisheng Zhang		i2c2 = &i2c2;
17*ac9a37e2SJisheng Zhang		i2c5 = &i2c5;
18*ac9a37e2SJisheng Zhang		i2c6 = &i2c6;
19*ac9a37e2SJisheng Zhang		mmc0 = &mmc0;
20*ac9a37e2SJisheng Zhang		mmc1 = &mmc1;
21*ac9a37e2SJisheng Zhang		serial0 = &uart0;
22*ac9a37e2SJisheng Zhang	};
23*ac9a37e2SJisheng Zhang
24*ac9a37e2SJisheng Zhang	chosen {
25*ac9a37e2SJisheng Zhang		stdout-path = "serial0:115200n8";
26*ac9a37e2SJisheng Zhang	};
27*ac9a37e2SJisheng Zhang
28*ac9a37e2SJisheng Zhang	memory@40000000 {
29*ac9a37e2SJisheng Zhang		device_type = "memory";
30*ac9a37e2SJisheng Zhang		reg = <0x0 0x40000000 0x1 0x0>;
31*ac9a37e2SJisheng Zhang	};
32*ac9a37e2SJisheng Zhang
33*ac9a37e2SJisheng Zhang	gpio-restart {
34*ac9a37e2SJisheng Zhang		compatible = "gpio-restart";
35*ac9a37e2SJisheng Zhang		gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
36*ac9a37e2SJisheng Zhang		priority = <224>;
37*ac9a37e2SJisheng Zhang	};
38*ac9a37e2SJisheng Zhang
39*ac9a37e2SJisheng Zhang	pwmdac_codec: audio-codec {
40*ac9a37e2SJisheng Zhang		compatible = "linux,spdif-dit";
41*ac9a37e2SJisheng Zhang		#sound-dai-cells = <0>;
42*ac9a37e2SJisheng Zhang	};
43*ac9a37e2SJisheng Zhang
44*ac9a37e2SJisheng Zhang	sound {
45*ac9a37e2SJisheng Zhang		compatible = "simple-audio-card";
46*ac9a37e2SJisheng Zhang		simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
47*ac9a37e2SJisheng Zhang		#address-cells = <1>;
48*ac9a37e2SJisheng Zhang		#size-cells = <0>;
49*ac9a37e2SJisheng Zhang
50*ac9a37e2SJisheng Zhang		simple-audio-card,dai-link@0 {
51*ac9a37e2SJisheng Zhang			reg = <0>;
52*ac9a37e2SJisheng Zhang			format = "left_j";
53*ac9a37e2SJisheng Zhang			bitclock-master = <&sndcpu0>;
54*ac9a37e2SJisheng Zhang			frame-master = <&sndcpu0>;
55*ac9a37e2SJisheng Zhang
56*ac9a37e2SJisheng Zhang			sndcpu0: cpu {
57*ac9a37e2SJisheng Zhang				sound-dai = <&pwmdac>;
58*ac9a37e2SJisheng Zhang			};
59*ac9a37e2SJisheng Zhang
60*ac9a37e2SJisheng Zhang			codec {
61*ac9a37e2SJisheng Zhang				sound-dai = <&pwmdac_codec>;
62*ac9a37e2SJisheng Zhang			};
63*ac9a37e2SJisheng Zhang		};
64*ac9a37e2SJisheng Zhang	};
65*ac9a37e2SJisheng Zhang};
66*ac9a37e2SJisheng Zhang
67*ac9a37e2SJisheng Zhang&cpus {
68*ac9a37e2SJisheng Zhang	timebase-frequency = <4000000>;
69*ac9a37e2SJisheng Zhang};
70*ac9a37e2SJisheng Zhang
71*ac9a37e2SJisheng Zhang&dvp_clk {
72*ac9a37e2SJisheng Zhang	clock-frequency = <74250000>;
73*ac9a37e2SJisheng Zhang};
74*ac9a37e2SJisheng Zhang
75*ac9a37e2SJisheng Zhang&gmac0_rgmii_rxin {
76*ac9a37e2SJisheng Zhang	clock-frequency = <125000000>;
77*ac9a37e2SJisheng Zhang};
78*ac9a37e2SJisheng Zhang
79*ac9a37e2SJisheng Zhang&gmac0_rmii_refin {
80*ac9a37e2SJisheng Zhang	clock-frequency = <50000000>;
81*ac9a37e2SJisheng Zhang};
82*ac9a37e2SJisheng Zhang
83*ac9a37e2SJisheng Zhang&gmac1_rgmii_rxin {
84*ac9a37e2SJisheng Zhang	clock-frequency = <125000000>;
85*ac9a37e2SJisheng Zhang};
86*ac9a37e2SJisheng Zhang
87*ac9a37e2SJisheng Zhang&gmac1_rmii_refin {
88*ac9a37e2SJisheng Zhang	clock-frequency = <50000000>;
89*ac9a37e2SJisheng Zhang};
90*ac9a37e2SJisheng Zhang
91*ac9a37e2SJisheng Zhang&hdmitx0_pixelclk {
92*ac9a37e2SJisheng Zhang	clock-frequency = <297000000>;
93*ac9a37e2SJisheng Zhang};
94*ac9a37e2SJisheng Zhang
95*ac9a37e2SJisheng Zhang&i2srx_bclk_ext {
96*ac9a37e2SJisheng Zhang	clock-frequency = <12288000>;
97*ac9a37e2SJisheng Zhang};
98*ac9a37e2SJisheng Zhang
99*ac9a37e2SJisheng Zhang&i2srx_lrck_ext {
100*ac9a37e2SJisheng Zhang	clock-frequency = <192000>;
101*ac9a37e2SJisheng Zhang};
102*ac9a37e2SJisheng Zhang
103*ac9a37e2SJisheng Zhang&i2stx_bclk_ext {
104*ac9a37e2SJisheng Zhang	clock-frequency = <12288000>;
105*ac9a37e2SJisheng Zhang};
106*ac9a37e2SJisheng Zhang
107*ac9a37e2SJisheng Zhang&i2stx_lrck_ext {
108*ac9a37e2SJisheng Zhang	clock-frequency = <192000>;
109*ac9a37e2SJisheng Zhang};
110*ac9a37e2SJisheng Zhang
111*ac9a37e2SJisheng Zhang&mclk_ext {
112*ac9a37e2SJisheng Zhang	clock-frequency = <12288000>;
113*ac9a37e2SJisheng Zhang};
114*ac9a37e2SJisheng Zhang
115*ac9a37e2SJisheng Zhang&osc {
116*ac9a37e2SJisheng Zhang	clock-frequency = <24000000>;
117*ac9a37e2SJisheng Zhang};
118*ac9a37e2SJisheng Zhang
119*ac9a37e2SJisheng Zhang&rtc_osc {
120*ac9a37e2SJisheng Zhang	clock-frequency = <32768>;
121*ac9a37e2SJisheng Zhang};
122*ac9a37e2SJisheng Zhang
123*ac9a37e2SJisheng Zhang&tdm_ext {
124*ac9a37e2SJisheng Zhang	clock-frequency = <49152000>;
125*ac9a37e2SJisheng Zhang};
126*ac9a37e2SJisheng Zhang
127*ac9a37e2SJisheng Zhang&camss {
128*ac9a37e2SJisheng Zhang	assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
129*ac9a37e2SJisheng Zhang			  <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
130*ac9a37e2SJisheng Zhang	assigned-clock-rates = <49500000>, <198000000>;
131*ac9a37e2SJisheng Zhang	status = "okay";
132*ac9a37e2SJisheng Zhang
133*ac9a37e2SJisheng Zhang	ports {
134*ac9a37e2SJisheng Zhang		#address-cells = <1>;
135*ac9a37e2SJisheng Zhang		#size-cells = <0>;
136*ac9a37e2SJisheng Zhang
137*ac9a37e2SJisheng Zhang		port@0 {
138*ac9a37e2SJisheng Zhang			reg = <0>;
139*ac9a37e2SJisheng Zhang		};
140*ac9a37e2SJisheng Zhang
141*ac9a37e2SJisheng Zhang		port@1 {
142*ac9a37e2SJisheng Zhang			reg = <1>;
143*ac9a37e2SJisheng Zhang
144*ac9a37e2SJisheng Zhang			camss_from_csi2rx: endpoint {
145*ac9a37e2SJisheng Zhang				remote-endpoint = <&csi2rx_to_camss>;
146*ac9a37e2SJisheng Zhang			};
147*ac9a37e2SJisheng Zhang		};
148*ac9a37e2SJisheng Zhang	};
149*ac9a37e2SJisheng Zhang};
150*ac9a37e2SJisheng Zhang
151*ac9a37e2SJisheng Zhang&csi2rx {
152*ac9a37e2SJisheng Zhang	assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
153*ac9a37e2SJisheng Zhang	assigned-clock-rates = <297000000>;
154*ac9a37e2SJisheng Zhang	status = "okay";
155*ac9a37e2SJisheng Zhang
156*ac9a37e2SJisheng Zhang	ports {
157*ac9a37e2SJisheng Zhang		#address-cells = <1>;
158*ac9a37e2SJisheng Zhang		#size-cells = <0>;
159*ac9a37e2SJisheng Zhang
160*ac9a37e2SJisheng Zhang		port@0 {
161*ac9a37e2SJisheng Zhang			reg = <0>;
162*ac9a37e2SJisheng Zhang
163*ac9a37e2SJisheng Zhang			/* remote MIPI sensor endpoint */
164*ac9a37e2SJisheng Zhang		};
165*ac9a37e2SJisheng Zhang
166*ac9a37e2SJisheng Zhang		port@1 {
167*ac9a37e2SJisheng Zhang			reg = <1>;
168*ac9a37e2SJisheng Zhang
169*ac9a37e2SJisheng Zhang			csi2rx_to_camss: endpoint {
170*ac9a37e2SJisheng Zhang				remote-endpoint = <&camss_from_csi2rx>;
171*ac9a37e2SJisheng Zhang			};
172*ac9a37e2SJisheng Zhang		};
173*ac9a37e2SJisheng Zhang	};
174*ac9a37e2SJisheng Zhang};
175*ac9a37e2SJisheng Zhang
176*ac9a37e2SJisheng Zhang&gmac0 {
177*ac9a37e2SJisheng Zhang	phy-handle = <&phy0>;
178*ac9a37e2SJisheng Zhang	phy-mode = "rgmii-id";
179*ac9a37e2SJisheng Zhang	status = "okay";
180*ac9a37e2SJisheng Zhang
181*ac9a37e2SJisheng Zhang	mdio {
182*ac9a37e2SJisheng Zhang		#address-cells = <1>;
183*ac9a37e2SJisheng Zhang		#size-cells = <0>;
184*ac9a37e2SJisheng Zhang		compatible = "snps,dwmac-mdio";
185*ac9a37e2SJisheng Zhang
186*ac9a37e2SJisheng Zhang		phy0: ethernet-phy@0 {
187*ac9a37e2SJisheng Zhang			reg = <0>;
188*ac9a37e2SJisheng Zhang		};
189*ac9a37e2SJisheng Zhang	};
190*ac9a37e2SJisheng Zhang};
191*ac9a37e2SJisheng Zhang
192*ac9a37e2SJisheng Zhang&i2c0 {
193*ac9a37e2SJisheng Zhang	clock-frequency = <100000>;
194*ac9a37e2SJisheng Zhang	i2c-sda-hold-time-ns = <300>;
195*ac9a37e2SJisheng Zhang	i2c-sda-falling-time-ns = <510>;
196*ac9a37e2SJisheng Zhang	i2c-scl-falling-time-ns = <510>;
197*ac9a37e2SJisheng Zhang	pinctrl-names = "default";
198*ac9a37e2SJisheng Zhang	pinctrl-0 = <&i2c0_pins>;
199*ac9a37e2SJisheng Zhang	status = "okay";
200*ac9a37e2SJisheng Zhang};
201*ac9a37e2SJisheng Zhang
202*ac9a37e2SJisheng Zhang&i2c2 {
203*ac9a37e2SJisheng Zhang	clock-frequency = <100000>;
204*ac9a37e2SJisheng Zhang	i2c-sda-hold-time-ns = <300>;
205*ac9a37e2SJisheng Zhang	i2c-sda-falling-time-ns = <510>;
206*ac9a37e2SJisheng Zhang	i2c-scl-falling-time-ns = <510>;
207*ac9a37e2SJisheng Zhang	pinctrl-names = "default";
208*ac9a37e2SJisheng Zhang	pinctrl-0 = <&i2c2_pins>;
209*ac9a37e2SJisheng Zhang	status = "okay";
210*ac9a37e2SJisheng Zhang};
211*ac9a37e2SJisheng Zhang
212*ac9a37e2SJisheng Zhang&i2c5 {
213*ac9a37e2SJisheng Zhang	clock-frequency = <100000>;
214*ac9a37e2SJisheng Zhang	i2c-sda-hold-time-ns = <300>;
215*ac9a37e2SJisheng Zhang	i2c-sda-falling-time-ns = <510>;
216*ac9a37e2SJisheng Zhang	i2c-scl-falling-time-ns = <510>;
217*ac9a37e2SJisheng Zhang	pinctrl-names = "default";
218*ac9a37e2SJisheng Zhang	pinctrl-0 = <&i2c5_pins>;
219*ac9a37e2SJisheng Zhang	status = "okay";
220*ac9a37e2SJisheng Zhang
221*ac9a37e2SJisheng Zhang	axp15060: pmic@36 {
222*ac9a37e2SJisheng Zhang		compatible = "x-powers,axp15060";
223*ac9a37e2SJisheng Zhang		reg = <0x36>;
224*ac9a37e2SJisheng Zhang		interrupt-controller;
225*ac9a37e2SJisheng Zhang		#interrupt-cells = <1>;
226*ac9a37e2SJisheng Zhang
227*ac9a37e2SJisheng Zhang		regulators {
228*ac9a37e2SJisheng Zhang			vcc_3v3: dcdc1 {
229*ac9a37e2SJisheng Zhang				regulator-boot-on;
230*ac9a37e2SJisheng Zhang				regulator-always-on;
231*ac9a37e2SJisheng Zhang				regulator-min-microvolt = <3300000>;
232*ac9a37e2SJisheng Zhang				regulator-max-microvolt = <3300000>;
233*ac9a37e2SJisheng Zhang				regulator-name = "vcc_3v3";
234*ac9a37e2SJisheng Zhang			};
235*ac9a37e2SJisheng Zhang
236*ac9a37e2SJisheng Zhang			vdd_cpu: dcdc2 {
237*ac9a37e2SJisheng Zhang				regulator-always-on;
238*ac9a37e2SJisheng Zhang				regulator-min-microvolt = <500000>;
239*ac9a37e2SJisheng Zhang				regulator-max-microvolt = <1540000>;
240*ac9a37e2SJisheng Zhang				regulator-name = "vdd-cpu";
241*ac9a37e2SJisheng Zhang			};
242*ac9a37e2SJisheng Zhang
243*ac9a37e2SJisheng Zhang			emmc_vdd: aldo4 {
244*ac9a37e2SJisheng Zhang				regulator-boot-on;
245*ac9a37e2SJisheng Zhang				regulator-always-on;
246*ac9a37e2SJisheng Zhang				regulator-min-microvolt = <1800000>;
247*ac9a37e2SJisheng Zhang				regulator-max-microvolt = <1800000>;
248*ac9a37e2SJisheng Zhang				regulator-name = "emmc_vdd";
249*ac9a37e2SJisheng Zhang			};
250*ac9a37e2SJisheng Zhang		};
251*ac9a37e2SJisheng Zhang	};
252*ac9a37e2SJisheng Zhang};
253*ac9a37e2SJisheng Zhang
254*ac9a37e2SJisheng Zhang&i2c6 {
255*ac9a37e2SJisheng Zhang	clock-frequency = <100000>;
256*ac9a37e2SJisheng Zhang	i2c-sda-hold-time-ns = <300>;
257*ac9a37e2SJisheng Zhang	i2c-sda-falling-time-ns = <510>;
258*ac9a37e2SJisheng Zhang	i2c-scl-falling-time-ns = <510>;
259*ac9a37e2SJisheng Zhang	pinctrl-names = "default";
260*ac9a37e2SJisheng Zhang	pinctrl-0 = <&i2c6_pins>;
261*ac9a37e2SJisheng Zhang	status = "okay";
262*ac9a37e2SJisheng Zhang};
263*ac9a37e2SJisheng Zhang
264*ac9a37e2SJisheng Zhang&mmc0 {
265*ac9a37e2SJisheng Zhang	max-frequency = <100000000>;
266*ac9a37e2SJisheng Zhang	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
267*ac9a37e2SJisheng Zhang	assigned-clock-rates = <50000000>;
268*ac9a37e2SJisheng Zhang	bus-width = <8>;
269*ac9a37e2SJisheng Zhang	cap-mmc-highspeed;
270*ac9a37e2SJisheng Zhang	mmc-ddr-1_8v;
271*ac9a37e2SJisheng Zhang	mmc-hs200-1_8v;
272*ac9a37e2SJisheng Zhang	cap-mmc-hw-reset;
273*ac9a37e2SJisheng Zhang	post-power-on-delay-ms = <200>;
274*ac9a37e2SJisheng Zhang	pinctrl-names = "default";
275*ac9a37e2SJisheng Zhang	pinctrl-0 = <&mmc0_pins>;
276*ac9a37e2SJisheng Zhang	vmmc-supply = <&vcc_3v3>;
277*ac9a37e2SJisheng Zhang	vqmmc-supply = <&emmc_vdd>;
278*ac9a37e2SJisheng Zhang	status = "okay";
279*ac9a37e2SJisheng Zhang};
280*ac9a37e2SJisheng Zhang
281*ac9a37e2SJisheng Zhang&mmc1 {
282*ac9a37e2SJisheng Zhang	max-frequency = <100000000>;
283*ac9a37e2SJisheng Zhang	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
284*ac9a37e2SJisheng Zhang	assigned-clock-rates = <50000000>;
285*ac9a37e2SJisheng Zhang	bus-width = <4>;
286*ac9a37e2SJisheng Zhang	no-sdio;
287*ac9a37e2SJisheng Zhang	no-mmc;
288*ac9a37e2SJisheng Zhang	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
289*ac9a37e2SJisheng Zhang	disable-wp;
290*ac9a37e2SJisheng Zhang	cap-sd-highspeed;
291*ac9a37e2SJisheng Zhang	post-power-on-delay-ms = <200>;
292*ac9a37e2SJisheng Zhang	pinctrl-names = "default";
293*ac9a37e2SJisheng Zhang	pinctrl-0 = <&mmc1_pins>;
294*ac9a37e2SJisheng Zhang	status = "okay";
295*ac9a37e2SJisheng Zhang};
296*ac9a37e2SJisheng Zhang
297*ac9a37e2SJisheng Zhang&pwmdac {
298*ac9a37e2SJisheng Zhang	pinctrl-names = "default";
299*ac9a37e2SJisheng Zhang	pinctrl-0 = <&pwmdac_pins>;
300*ac9a37e2SJisheng Zhang	status = "okay";
301*ac9a37e2SJisheng Zhang};
302*ac9a37e2SJisheng Zhang
303*ac9a37e2SJisheng Zhang&qspi {
304*ac9a37e2SJisheng Zhang	#address-cells = <1>;
305*ac9a37e2SJisheng Zhang	#size-cells = <0>;
306*ac9a37e2SJisheng Zhang	status = "okay";
307*ac9a37e2SJisheng Zhang
308*ac9a37e2SJisheng Zhang	nor_flash: flash@0 {
309*ac9a37e2SJisheng Zhang		compatible = "jedec,spi-nor";
310*ac9a37e2SJisheng Zhang		reg = <0>;
311*ac9a37e2SJisheng Zhang		cdns,read-delay = <5>;
312*ac9a37e2SJisheng Zhang		spi-max-frequency = <12000000>;
313*ac9a37e2SJisheng Zhang		cdns,tshsl-ns = <1>;
314*ac9a37e2SJisheng Zhang		cdns,tsd2d-ns = <1>;
315*ac9a37e2SJisheng Zhang		cdns,tchsh-ns = <1>;
316*ac9a37e2SJisheng Zhang		cdns,tslch-ns = <1>;
317*ac9a37e2SJisheng Zhang
318*ac9a37e2SJisheng Zhang		partitions {
319*ac9a37e2SJisheng Zhang			compatible = "fixed-partitions";
320*ac9a37e2SJisheng Zhang			#address-cells = <1>;
321*ac9a37e2SJisheng Zhang			#size-cells = <1>;
322*ac9a37e2SJisheng Zhang
323*ac9a37e2SJisheng Zhang			spl@0 {
324*ac9a37e2SJisheng Zhang				reg = <0x0 0x80000>;
325*ac9a37e2SJisheng Zhang			};
326*ac9a37e2SJisheng Zhang			uboot-env@f0000 {
327*ac9a37e2SJisheng Zhang				reg = <0xf0000 0x10000>;
328*ac9a37e2SJisheng Zhang			};
329*ac9a37e2SJisheng Zhang			uboot@100000 {
330*ac9a37e2SJisheng Zhang				reg = <0x100000 0x400000>;
331*ac9a37e2SJisheng Zhang			};
332*ac9a37e2SJisheng Zhang			reserved-data@600000 {
333*ac9a37e2SJisheng Zhang				reg = <0x600000 0xa00000>;
334*ac9a37e2SJisheng Zhang			};
335*ac9a37e2SJisheng Zhang		};
336*ac9a37e2SJisheng Zhang	};
337*ac9a37e2SJisheng Zhang};
338*ac9a37e2SJisheng Zhang
339*ac9a37e2SJisheng Zhang&pwm {
340*ac9a37e2SJisheng Zhang	pinctrl-names = "default";
341*ac9a37e2SJisheng Zhang	pinctrl-0 = <&pwm_pins>;
342*ac9a37e2SJisheng Zhang	status = "okay";
343*ac9a37e2SJisheng Zhang};
344*ac9a37e2SJisheng Zhang
345*ac9a37e2SJisheng Zhang&spi0 {
346*ac9a37e2SJisheng Zhang	pinctrl-names = "default";
347*ac9a37e2SJisheng Zhang	pinctrl-0 = <&spi0_pins>;
348*ac9a37e2SJisheng Zhang	status = "okay";
349*ac9a37e2SJisheng Zhang
350*ac9a37e2SJisheng Zhang	spi_dev0: spi@0 {
351*ac9a37e2SJisheng Zhang		compatible = "rohm,dh2228fv";
352*ac9a37e2SJisheng Zhang		reg = <0>;
353*ac9a37e2SJisheng Zhang		spi-max-frequency = <10000000>;
354*ac9a37e2SJisheng Zhang	};
355*ac9a37e2SJisheng Zhang};
356*ac9a37e2SJisheng Zhang
357*ac9a37e2SJisheng Zhang&sysgpio {
358*ac9a37e2SJisheng Zhang	i2c0_pins: i2c0-0 {
359*ac9a37e2SJisheng Zhang		i2c-pins {
360*ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(57, GPOUT_LOW,
361*ac9a37e2SJisheng Zhang					      GPOEN_SYS_I2C0_CLK,
362*ac9a37e2SJisheng Zhang					      GPI_SYS_I2C0_CLK)>,
363*ac9a37e2SJisheng Zhang				 <GPIOMUX(58, GPOUT_LOW,
364*ac9a37e2SJisheng Zhang					      GPOEN_SYS_I2C0_DATA,
365*ac9a37e2SJisheng Zhang					      GPI_SYS_I2C0_DATA)>;
366*ac9a37e2SJisheng Zhang			bias-disable; /* external pull-up */
367*ac9a37e2SJisheng Zhang			input-enable;
368*ac9a37e2SJisheng Zhang			input-schmitt-enable;
369*ac9a37e2SJisheng Zhang		};
370*ac9a37e2SJisheng Zhang	};
371*ac9a37e2SJisheng Zhang
372*ac9a37e2SJisheng Zhang	i2c2_pins: i2c2-0 {
373*ac9a37e2SJisheng Zhang		i2c-pins {
374*ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(3, GPOUT_LOW,
375*ac9a37e2SJisheng Zhang					     GPOEN_SYS_I2C2_CLK,
376*ac9a37e2SJisheng Zhang					     GPI_SYS_I2C2_CLK)>,
377*ac9a37e2SJisheng Zhang				 <GPIOMUX(2, GPOUT_LOW,
378*ac9a37e2SJisheng Zhang					     GPOEN_SYS_I2C2_DATA,
379*ac9a37e2SJisheng Zhang					     GPI_SYS_I2C2_DATA)>;
380*ac9a37e2SJisheng Zhang			bias-disable; /* external pull-up */
381*ac9a37e2SJisheng Zhang			input-enable;
382*ac9a37e2SJisheng Zhang			input-schmitt-enable;
383*ac9a37e2SJisheng Zhang		};
384*ac9a37e2SJisheng Zhang	};
385*ac9a37e2SJisheng Zhang
386*ac9a37e2SJisheng Zhang	i2c5_pins: i2c5-0 {
387*ac9a37e2SJisheng Zhang		i2c-pins {
388*ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(19, GPOUT_LOW,
389*ac9a37e2SJisheng Zhang					      GPOEN_SYS_I2C5_CLK,
390*ac9a37e2SJisheng Zhang					      GPI_SYS_I2C5_CLK)>,
391*ac9a37e2SJisheng Zhang				 <GPIOMUX(20, GPOUT_LOW,
392*ac9a37e2SJisheng Zhang					      GPOEN_SYS_I2C5_DATA,
393*ac9a37e2SJisheng Zhang					      GPI_SYS_I2C5_DATA)>;
394*ac9a37e2SJisheng Zhang			bias-disable; /* external pull-up */
395*ac9a37e2SJisheng Zhang			input-enable;
396*ac9a37e2SJisheng Zhang			input-schmitt-enable;
397*ac9a37e2SJisheng Zhang		};
398*ac9a37e2SJisheng Zhang	};
399*ac9a37e2SJisheng Zhang
400*ac9a37e2SJisheng Zhang	i2c6_pins: i2c6-0 {
401*ac9a37e2SJisheng Zhang		i2c-pins {
402*ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(16, GPOUT_LOW,
403*ac9a37e2SJisheng Zhang					      GPOEN_SYS_I2C6_CLK,
404*ac9a37e2SJisheng Zhang					      GPI_SYS_I2C6_CLK)>,
405*ac9a37e2SJisheng Zhang				 <GPIOMUX(17, GPOUT_LOW,
406*ac9a37e2SJisheng Zhang					      GPOEN_SYS_I2C6_DATA,
407*ac9a37e2SJisheng Zhang					      GPI_SYS_I2C6_DATA)>;
408*ac9a37e2SJisheng Zhang			bias-disable; /* external pull-up */
409*ac9a37e2SJisheng Zhang			input-enable;
410*ac9a37e2SJisheng Zhang			input-schmitt-enable;
411*ac9a37e2SJisheng Zhang		};
412*ac9a37e2SJisheng Zhang	};
413*ac9a37e2SJisheng Zhang
414*ac9a37e2SJisheng Zhang	mmc0_pins: mmc0-0 {
415*ac9a37e2SJisheng Zhang		 rst-pins {
416*ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
417*ac9a37e2SJisheng Zhang					      GPOEN_ENABLE,
418*ac9a37e2SJisheng Zhang					      GPI_NONE)>;
419*ac9a37e2SJisheng Zhang			bias-pull-up;
420*ac9a37e2SJisheng Zhang			drive-strength = <12>;
421*ac9a37e2SJisheng Zhang			input-disable;
422*ac9a37e2SJisheng Zhang			input-schmitt-disable;
423*ac9a37e2SJisheng Zhang			slew-rate = <0>;
424*ac9a37e2SJisheng Zhang		};
425*ac9a37e2SJisheng Zhang
426*ac9a37e2SJisheng Zhang		mmc-pins {
427*ac9a37e2SJisheng Zhang			pinmux = <PINMUX(64, 0)>,
428*ac9a37e2SJisheng Zhang				 <PINMUX(65, 0)>,
429*ac9a37e2SJisheng Zhang				 <PINMUX(66, 0)>,
430*ac9a37e2SJisheng Zhang				 <PINMUX(67, 0)>,
431*ac9a37e2SJisheng Zhang				 <PINMUX(68, 0)>,
432*ac9a37e2SJisheng Zhang				 <PINMUX(69, 0)>,
433*ac9a37e2SJisheng Zhang				 <PINMUX(70, 0)>,
434*ac9a37e2SJisheng Zhang				 <PINMUX(71, 0)>,
435*ac9a37e2SJisheng Zhang				 <PINMUX(72, 0)>,
436*ac9a37e2SJisheng Zhang				 <PINMUX(73, 0)>;
437*ac9a37e2SJisheng Zhang			bias-pull-up;
438*ac9a37e2SJisheng Zhang			drive-strength = <12>;
439*ac9a37e2SJisheng Zhang			input-enable;
440*ac9a37e2SJisheng Zhang		};
441*ac9a37e2SJisheng Zhang	};
442*ac9a37e2SJisheng Zhang
443*ac9a37e2SJisheng Zhang	mmc1_pins: mmc1-0 {
444*ac9a37e2SJisheng Zhang		clk-pins {
445*ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
446*ac9a37e2SJisheng Zhang					      GPOEN_ENABLE,
447*ac9a37e2SJisheng Zhang					      GPI_NONE)>;
448*ac9a37e2SJisheng Zhang			bias-pull-up;
449*ac9a37e2SJisheng Zhang			drive-strength = <12>;
450*ac9a37e2SJisheng Zhang			input-disable;
451*ac9a37e2SJisheng Zhang			input-schmitt-disable;
452*ac9a37e2SJisheng Zhang			slew-rate = <0>;
453*ac9a37e2SJisheng Zhang		};
454*ac9a37e2SJisheng Zhang
455*ac9a37e2SJisheng Zhang		mmc-pins {
456*ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
457*ac9a37e2SJisheng Zhang					     GPOEN_SYS_SDIO1_CMD,
458*ac9a37e2SJisheng Zhang					     GPI_SYS_SDIO1_CMD)>,
459*ac9a37e2SJisheng Zhang				 <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
460*ac9a37e2SJisheng Zhang					      GPOEN_SYS_SDIO1_DATA0,
461*ac9a37e2SJisheng Zhang					      GPI_SYS_SDIO1_DATA0)>,
462*ac9a37e2SJisheng Zhang				 <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
463*ac9a37e2SJisheng Zhang					      GPOEN_SYS_SDIO1_DATA1,
464*ac9a37e2SJisheng Zhang					      GPI_SYS_SDIO1_DATA1)>,
465*ac9a37e2SJisheng Zhang				 <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
466*ac9a37e2SJisheng Zhang					     GPOEN_SYS_SDIO1_DATA2,
467*ac9a37e2SJisheng Zhang					     GPI_SYS_SDIO1_DATA2)>,
468*ac9a37e2SJisheng Zhang				 <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
469*ac9a37e2SJisheng Zhang					     GPOEN_SYS_SDIO1_DATA3,
470*ac9a37e2SJisheng Zhang					     GPI_SYS_SDIO1_DATA3)>;
471*ac9a37e2SJisheng Zhang			bias-pull-up;
472*ac9a37e2SJisheng Zhang			drive-strength = <12>;
473*ac9a37e2SJisheng Zhang			input-enable;
474*ac9a37e2SJisheng Zhang			input-schmitt-enable;
475*ac9a37e2SJisheng Zhang			slew-rate = <0>;
476*ac9a37e2SJisheng Zhang		};
477*ac9a37e2SJisheng Zhang	};
478*ac9a37e2SJisheng Zhang
479*ac9a37e2SJisheng Zhang	pwmdac_pins: pwmdac-0 {
480*ac9a37e2SJisheng Zhang		pwmdac-pins {
481*ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
482*ac9a37e2SJisheng Zhang					      GPOEN_ENABLE,
483*ac9a37e2SJisheng Zhang					      GPI_NONE)>,
484*ac9a37e2SJisheng Zhang				 <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
485*ac9a37e2SJisheng Zhang					      GPOEN_ENABLE,
486*ac9a37e2SJisheng Zhang					      GPI_NONE)>;
487*ac9a37e2SJisheng Zhang			bias-disable;
488*ac9a37e2SJisheng Zhang			drive-strength = <2>;
489*ac9a37e2SJisheng Zhang			input-disable;
490*ac9a37e2SJisheng Zhang			input-schmitt-disable;
491*ac9a37e2SJisheng Zhang			slew-rate = <0>;
492*ac9a37e2SJisheng Zhang		};
493*ac9a37e2SJisheng Zhang	};
494*ac9a37e2SJisheng Zhang
495*ac9a37e2SJisheng Zhang	pwm_pins: pwm-0 {
496*ac9a37e2SJisheng Zhang		pwm-pins {
497*ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
498*ac9a37e2SJisheng Zhang					      GPOEN_SYS_PWM0_CHANNEL0,
499*ac9a37e2SJisheng Zhang					      GPI_NONE)>,
500*ac9a37e2SJisheng Zhang				 <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
501*ac9a37e2SJisheng Zhang					      GPOEN_SYS_PWM0_CHANNEL1,
502*ac9a37e2SJisheng Zhang					      GPI_NONE)>;
503*ac9a37e2SJisheng Zhang			bias-disable;
504*ac9a37e2SJisheng Zhang			drive-strength = <12>;
505*ac9a37e2SJisheng Zhang			input-disable;
506*ac9a37e2SJisheng Zhang			input-schmitt-disable;
507*ac9a37e2SJisheng Zhang			slew-rate = <0>;
508*ac9a37e2SJisheng Zhang		};
509*ac9a37e2SJisheng Zhang	};
510*ac9a37e2SJisheng Zhang
511*ac9a37e2SJisheng Zhang	spi0_pins: spi0-0 {
512*ac9a37e2SJisheng Zhang		mosi-pins {
513*ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
514*ac9a37e2SJisheng Zhang					      GPOEN_ENABLE,
515*ac9a37e2SJisheng Zhang					      GPI_NONE)>;
516*ac9a37e2SJisheng Zhang			bias-disable;
517*ac9a37e2SJisheng Zhang			input-disable;
518*ac9a37e2SJisheng Zhang			input-schmitt-disable;
519*ac9a37e2SJisheng Zhang		};
520*ac9a37e2SJisheng Zhang
521*ac9a37e2SJisheng Zhang		miso-pins {
522*ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(53, GPOUT_LOW,
523*ac9a37e2SJisheng Zhang					      GPOEN_DISABLE,
524*ac9a37e2SJisheng Zhang					      GPI_SYS_SPI0_RXD)>;
525*ac9a37e2SJisheng Zhang			bias-pull-up;
526*ac9a37e2SJisheng Zhang			input-enable;
527*ac9a37e2SJisheng Zhang			input-schmitt-enable;
528*ac9a37e2SJisheng Zhang		};
529*ac9a37e2SJisheng Zhang
530*ac9a37e2SJisheng Zhang		sck-pins {
531*ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
532*ac9a37e2SJisheng Zhang					      GPOEN_ENABLE,
533*ac9a37e2SJisheng Zhang					      GPI_SYS_SPI0_CLK)>;
534*ac9a37e2SJisheng Zhang			bias-disable;
535*ac9a37e2SJisheng Zhang			input-disable;
536*ac9a37e2SJisheng Zhang			input-schmitt-disable;
537*ac9a37e2SJisheng Zhang		};
538*ac9a37e2SJisheng Zhang
539*ac9a37e2SJisheng Zhang		ss-pins {
540*ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
541*ac9a37e2SJisheng Zhang					      GPOEN_ENABLE,
542*ac9a37e2SJisheng Zhang					      GPI_SYS_SPI0_FSS)>;
543*ac9a37e2SJisheng Zhang			bias-disable;
544*ac9a37e2SJisheng Zhang			input-disable;
545*ac9a37e2SJisheng Zhang			input-schmitt-disable;
546*ac9a37e2SJisheng Zhang		};
547*ac9a37e2SJisheng Zhang	};
548*ac9a37e2SJisheng Zhang
549*ac9a37e2SJisheng Zhang	uart0_pins: uart0-0 {
550*ac9a37e2SJisheng Zhang		tx-pins {
551*ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
552*ac9a37e2SJisheng Zhang					     GPOEN_ENABLE,
553*ac9a37e2SJisheng Zhang					     GPI_NONE)>;
554*ac9a37e2SJisheng Zhang			bias-disable;
555*ac9a37e2SJisheng Zhang			drive-strength = <12>;
556*ac9a37e2SJisheng Zhang			input-disable;
557*ac9a37e2SJisheng Zhang			input-schmitt-disable;
558*ac9a37e2SJisheng Zhang			slew-rate = <0>;
559*ac9a37e2SJisheng Zhang		};
560*ac9a37e2SJisheng Zhang
561*ac9a37e2SJisheng Zhang		rx-pins {
562*ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(6, GPOUT_LOW,
563*ac9a37e2SJisheng Zhang					     GPOEN_DISABLE,
564*ac9a37e2SJisheng Zhang					     GPI_SYS_UART0_RX)>;
565*ac9a37e2SJisheng Zhang			bias-disable; /* external pull-up */
566*ac9a37e2SJisheng Zhang			drive-strength = <2>;
567*ac9a37e2SJisheng Zhang			input-enable;
568*ac9a37e2SJisheng Zhang			input-schmitt-enable;
569*ac9a37e2SJisheng Zhang			slew-rate = <0>;
570*ac9a37e2SJisheng Zhang		};
571*ac9a37e2SJisheng Zhang	};
572*ac9a37e2SJisheng Zhang};
573*ac9a37e2SJisheng Zhang
574*ac9a37e2SJisheng Zhang&uart0 {
575*ac9a37e2SJisheng Zhang	pinctrl-names = "default";
576*ac9a37e2SJisheng Zhang	pinctrl-0 = <&uart0_pins>;
577*ac9a37e2SJisheng Zhang	status = "okay";
578*ac9a37e2SJisheng Zhang};
579*ac9a37e2SJisheng Zhang
580*ac9a37e2SJisheng Zhang&usb0 {
581*ac9a37e2SJisheng Zhang	dr_mode = "peripheral";
582*ac9a37e2SJisheng Zhang	status = "okay";
583*ac9a37e2SJisheng Zhang};
584*ac9a37e2SJisheng Zhang
585*ac9a37e2SJisheng Zhang&U74_1 {
586*ac9a37e2SJisheng Zhang	cpu-supply = <&vdd_cpu>;
587*ac9a37e2SJisheng Zhang};
588*ac9a37e2SJisheng Zhang
589*ac9a37e2SJisheng Zhang&U74_2 {
590*ac9a37e2SJisheng Zhang	cpu-supply = <&vdd_cpu>;
591*ac9a37e2SJisheng Zhang};
592*ac9a37e2SJisheng Zhang
593*ac9a37e2SJisheng Zhang&U74_3 {
594*ac9a37e2SJisheng Zhang	cpu-supply = <&vdd_cpu>;
595*ac9a37e2SJisheng Zhang};
596*ac9a37e2SJisheng Zhang
597*ac9a37e2SJisheng Zhang&U74_4 {
598*ac9a37e2SJisheng Zhang	cpu-supply = <&vdd_cpu>;
599*ac9a37e2SJisheng Zhang};
600