xref: /linux/scripts/dtc/include-prefixes/riscv/starfive/jh7110-common.dtsi (revision 3fd6c59042dbba50391e30862beac979491145fe)
1ac9a37e2SJisheng Zhang// SPDX-License-Identifier: GPL-2.0 OR MIT
2ac9a37e2SJisheng Zhang/*
3ac9a37e2SJisheng Zhang * Copyright (C) 2022 StarFive Technology Co., Ltd.
4ac9a37e2SJisheng Zhang * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
5ac9a37e2SJisheng Zhang */
6ac9a37e2SJisheng Zhang
7ac9a37e2SJisheng Zhang/dts-v1/;
8ac9a37e2SJisheng Zhang#include "jh7110.dtsi"
9ac9a37e2SJisheng Zhang#include "jh7110-pinfunc.h"
10ac9a37e2SJisheng Zhang#include <dt-bindings/gpio/gpio.h>
11ac9a37e2SJisheng Zhang
12ac9a37e2SJisheng Zhang/ {
13ac9a37e2SJisheng Zhang	aliases {
14ac9a37e2SJisheng Zhang		ethernet0 = &gmac0;
15ac9a37e2SJisheng Zhang		i2c0 = &i2c0;
16ac9a37e2SJisheng Zhang		i2c2 = &i2c2;
17ac9a37e2SJisheng Zhang		i2c5 = &i2c5;
18ac9a37e2SJisheng Zhang		i2c6 = &i2c6;
19ac9a37e2SJisheng Zhang		mmc0 = &mmc0;
20ac9a37e2SJisheng Zhang		mmc1 = &mmc1;
21ac9a37e2SJisheng Zhang		serial0 = &uart0;
22ac9a37e2SJisheng Zhang	};
23ac9a37e2SJisheng Zhang
24ac9a37e2SJisheng Zhang	chosen {
25ac9a37e2SJisheng Zhang		stdout-path = "serial0:115200n8";
26ac9a37e2SJisheng Zhang	};
27ac9a37e2SJisheng Zhang
28ac9a37e2SJisheng Zhang	memory@40000000 {
29ac9a37e2SJisheng Zhang		device_type = "memory";
30ac9a37e2SJisheng Zhang		reg = <0x0 0x40000000 0x1 0x0>;
31ac9a37e2SJisheng Zhang	};
32ac9a37e2SJisheng Zhang
33ac9a37e2SJisheng Zhang	gpio-restart {
34ac9a37e2SJisheng Zhang		compatible = "gpio-restart";
35ac9a37e2SJisheng Zhang		gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
36ac9a37e2SJisheng Zhang		priority = <224>;
37ac9a37e2SJisheng Zhang	};
38ac9a37e2SJisheng Zhang
39ac9a37e2SJisheng Zhang	pwmdac_codec: audio-codec {
40ac9a37e2SJisheng Zhang		compatible = "linux,spdif-dit";
41ac9a37e2SJisheng Zhang		#sound-dai-cells = <0>;
42ac9a37e2SJisheng Zhang	};
43ac9a37e2SJisheng Zhang
44ac9a37e2SJisheng Zhang	sound {
45ac9a37e2SJisheng Zhang		compatible = "simple-audio-card";
46ac9a37e2SJisheng Zhang		simple-audio-card,name = "StarFive-PWMDAC-Sound-Card";
47ac9a37e2SJisheng Zhang		#address-cells = <1>;
48ac9a37e2SJisheng Zhang		#size-cells = <0>;
49ac9a37e2SJisheng Zhang
50ac9a37e2SJisheng Zhang		simple-audio-card,dai-link@0 {
51ac9a37e2SJisheng Zhang			reg = <0>;
52ac9a37e2SJisheng Zhang			format = "left_j";
53ac9a37e2SJisheng Zhang			bitclock-master = <&sndcpu0>;
54ac9a37e2SJisheng Zhang			frame-master = <&sndcpu0>;
55ac9a37e2SJisheng Zhang
56ac9a37e2SJisheng Zhang			sndcpu0: cpu {
57ac9a37e2SJisheng Zhang				sound-dai = <&pwmdac>;
58ac9a37e2SJisheng Zhang			};
59ac9a37e2SJisheng Zhang
60ac9a37e2SJisheng Zhang			codec {
61ac9a37e2SJisheng Zhang				sound-dai = <&pwmdac_codec>;
62ac9a37e2SJisheng Zhang			};
63ac9a37e2SJisheng Zhang		};
64ac9a37e2SJisheng Zhang	};
65ac9a37e2SJisheng Zhang};
66ac9a37e2SJisheng Zhang
67ac9a37e2SJisheng Zhang&cpus {
68ac9a37e2SJisheng Zhang	timebase-frequency = <4000000>;
69ac9a37e2SJisheng Zhang};
70ac9a37e2SJisheng Zhang
71ac9a37e2SJisheng Zhang&dvp_clk {
72ac9a37e2SJisheng Zhang	clock-frequency = <74250000>;
73ac9a37e2SJisheng Zhang};
74ac9a37e2SJisheng Zhang
75ac9a37e2SJisheng Zhang&gmac0_rgmii_rxin {
76ac9a37e2SJisheng Zhang	clock-frequency = <125000000>;
77ac9a37e2SJisheng Zhang};
78ac9a37e2SJisheng Zhang
79ac9a37e2SJisheng Zhang&gmac0_rmii_refin {
80ac9a37e2SJisheng Zhang	clock-frequency = <50000000>;
81ac9a37e2SJisheng Zhang};
82ac9a37e2SJisheng Zhang
83ac9a37e2SJisheng Zhang&gmac1_rgmii_rxin {
84ac9a37e2SJisheng Zhang	clock-frequency = <125000000>;
85ac9a37e2SJisheng Zhang};
86ac9a37e2SJisheng Zhang
87ac9a37e2SJisheng Zhang&gmac1_rmii_refin {
88ac9a37e2SJisheng Zhang	clock-frequency = <50000000>;
89ac9a37e2SJisheng Zhang};
90ac9a37e2SJisheng Zhang
91ac9a37e2SJisheng Zhang&hdmitx0_pixelclk {
92ac9a37e2SJisheng Zhang	clock-frequency = <297000000>;
93ac9a37e2SJisheng Zhang};
94ac9a37e2SJisheng Zhang
95ac9a37e2SJisheng Zhang&i2srx_bclk_ext {
96ac9a37e2SJisheng Zhang	clock-frequency = <12288000>;
97ac9a37e2SJisheng Zhang};
98ac9a37e2SJisheng Zhang
99ac9a37e2SJisheng Zhang&i2srx_lrck_ext {
100ac9a37e2SJisheng Zhang	clock-frequency = <192000>;
101ac9a37e2SJisheng Zhang};
102ac9a37e2SJisheng Zhang
103ac9a37e2SJisheng Zhang&i2stx_bclk_ext {
104ac9a37e2SJisheng Zhang	clock-frequency = <12288000>;
105ac9a37e2SJisheng Zhang};
106ac9a37e2SJisheng Zhang
107ac9a37e2SJisheng Zhang&i2stx_lrck_ext {
108ac9a37e2SJisheng Zhang	clock-frequency = <192000>;
109ac9a37e2SJisheng Zhang};
110ac9a37e2SJisheng Zhang
111ac9a37e2SJisheng Zhang&mclk_ext {
112ac9a37e2SJisheng Zhang	clock-frequency = <12288000>;
113ac9a37e2SJisheng Zhang};
114ac9a37e2SJisheng Zhang
115ac9a37e2SJisheng Zhang&osc {
116ac9a37e2SJisheng Zhang	clock-frequency = <24000000>;
117ac9a37e2SJisheng Zhang};
118ac9a37e2SJisheng Zhang
119ac9a37e2SJisheng Zhang&rtc_osc {
120ac9a37e2SJisheng Zhang	clock-frequency = <32768>;
121ac9a37e2SJisheng Zhang};
122ac9a37e2SJisheng Zhang
123ac9a37e2SJisheng Zhang&tdm_ext {
124ac9a37e2SJisheng Zhang	clock-frequency = <49152000>;
125ac9a37e2SJisheng Zhang};
126ac9a37e2SJisheng Zhang
127ac9a37e2SJisheng Zhang&camss {
128ac9a37e2SJisheng Zhang	assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
129ac9a37e2SJisheng Zhang			  <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
130ac9a37e2SJisheng Zhang	assigned-clock-rates = <49500000>, <198000000>;
131ac9a37e2SJisheng Zhang
132ac9a37e2SJisheng Zhang	ports {
133ac9a37e2SJisheng Zhang		#address-cells = <1>;
134ac9a37e2SJisheng Zhang		#size-cells = <0>;
135ac9a37e2SJisheng Zhang
136ac9a37e2SJisheng Zhang		port@0 {
137ac9a37e2SJisheng Zhang			reg = <0>;
138ac9a37e2SJisheng Zhang		};
139ac9a37e2SJisheng Zhang
140ac9a37e2SJisheng Zhang		port@1 {
141ac9a37e2SJisheng Zhang			reg = <1>;
142ac9a37e2SJisheng Zhang
143ac9a37e2SJisheng Zhang			camss_from_csi2rx: endpoint {
144ac9a37e2SJisheng Zhang				remote-endpoint = <&csi2rx_to_camss>;
145ac9a37e2SJisheng Zhang			};
146ac9a37e2SJisheng Zhang		};
147ac9a37e2SJisheng Zhang	};
148ac9a37e2SJisheng Zhang};
149ac9a37e2SJisheng Zhang
150ac9a37e2SJisheng Zhang&csi2rx {
151ac9a37e2SJisheng Zhang	assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
152ac9a37e2SJisheng Zhang	assigned-clock-rates = <297000000>;
153ac9a37e2SJisheng Zhang
154ac9a37e2SJisheng Zhang	ports {
155ac9a37e2SJisheng Zhang		#address-cells = <1>;
156ac9a37e2SJisheng Zhang		#size-cells = <0>;
157ac9a37e2SJisheng Zhang
158ac9a37e2SJisheng Zhang		port@0 {
159ac9a37e2SJisheng Zhang			reg = <0>;
160ac9a37e2SJisheng Zhang
161ac9a37e2SJisheng Zhang			/* remote MIPI sensor endpoint */
162ac9a37e2SJisheng Zhang		};
163ac9a37e2SJisheng Zhang
164ac9a37e2SJisheng Zhang		port@1 {
165ac9a37e2SJisheng Zhang			reg = <1>;
166ac9a37e2SJisheng Zhang
167ac9a37e2SJisheng Zhang			csi2rx_to_camss: endpoint {
168ac9a37e2SJisheng Zhang				remote-endpoint = <&camss_from_csi2rx>;
169ac9a37e2SJisheng Zhang			};
170ac9a37e2SJisheng Zhang		};
171ac9a37e2SJisheng Zhang	};
172ac9a37e2SJisheng Zhang};
173ac9a37e2SJisheng Zhang
174ac9a37e2SJisheng Zhang&gmac0 {
175ac9a37e2SJisheng Zhang	phy-handle = <&phy0>;
176ac9a37e2SJisheng Zhang	phy-mode = "rgmii-id";
177ac9a37e2SJisheng Zhang
178ac9a37e2SJisheng Zhang	mdio {
179ac9a37e2SJisheng Zhang		#address-cells = <1>;
180ac9a37e2SJisheng Zhang		#size-cells = <0>;
181ac9a37e2SJisheng Zhang		compatible = "snps,dwmac-mdio";
182ac9a37e2SJisheng Zhang
183ac9a37e2SJisheng Zhang		phy0: ethernet-phy@0 {
184ac9a37e2SJisheng Zhang			reg = <0>;
185ac9a37e2SJisheng Zhang		};
186ac9a37e2SJisheng Zhang	};
187ac9a37e2SJisheng Zhang};
188ac9a37e2SJisheng Zhang
189ac9a37e2SJisheng Zhang&i2c0 {
190ac9a37e2SJisheng Zhang	clock-frequency = <100000>;
191ac9a37e2SJisheng Zhang	i2c-sda-hold-time-ns = <300>;
192ac9a37e2SJisheng Zhang	i2c-sda-falling-time-ns = <510>;
193ac9a37e2SJisheng Zhang	i2c-scl-falling-time-ns = <510>;
194ac9a37e2SJisheng Zhang	pinctrl-names = "default";
195ac9a37e2SJisheng Zhang	pinctrl-0 = <&i2c0_pins>;
196ac9a37e2SJisheng Zhang};
197ac9a37e2SJisheng Zhang
198ac9a37e2SJisheng Zhang&i2c2 {
199ac9a37e2SJisheng Zhang	clock-frequency = <100000>;
200ac9a37e2SJisheng Zhang	i2c-sda-hold-time-ns = <300>;
201ac9a37e2SJisheng Zhang	i2c-sda-falling-time-ns = <510>;
202ac9a37e2SJisheng Zhang	i2c-scl-falling-time-ns = <510>;
203ac9a37e2SJisheng Zhang	pinctrl-names = "default";
204ac9a37e2SJisheng Zhang	pinctrl-0 = <&i2c2_pins>;
205ac9a37e2SJisheng Zhang	status = "okay";
206ac9a37e2SJisheng Zhang};
207ac9a37e2SJisheng Zhang
208ac9a37e2SJisheng Zhang&i2c5 {
209ac9a37e2SJisheng Zhang	clock-frequency = <100000>;
210ac9a37e2SJisheng Zhang	i2c-sda-hold-time-ns = <300>;
211ac9a37e2SJisheng Zhang	i2c-sda-falling-time-ns = <510>;
212ac9a37e2SJisheng Zhang	i2c-scl-falling-time-ns = <510>;
213ac9a37e2SJisheng Zhang	pinctrl-names = "default";
214ac9a37e2SJisheng Zhang	pinctrl-0 = <&i2c5_pins>;
215ac9a37e2SJisheng Zhang	status = "okay";
216ac9a37e2SJisheng Zhang
217ac9a37e2SJisheng Zhang	axp15060: pmic@36 {
218ac9a37e2SJisheng Zhang		compatible = "x-powers,axp15060";
219ac9a37e2SJisheng Zhang		reg = <0x36>;
220ac9a37e2SJisheng Zhang		interrupt-controller;
221ac9a37e2SJisheng Zhang		#interrupt-cells = <1>;
222ac9a37e2SJisheng Zhang
223ac9a37e2SJisheng Zhang		regulators {
224ac9a37e2SJisheng Zhang			vcc_3v3: dcdc1 {
225ac9a37e2SJisheng Zhang				regulator-boot-on;
226ac9a37e2SJisheng Zhang				regulator-always-on;
227ac9a37e2SJisheng Zhang				regulator-min-microvolt = <3300000>;
228ac9a37e2SJisheng Zhang				regulator-max-microvolt = <3300000>;
229ac9a37e2SJisheng Zhang				regulator-name = "vcc_3v3";
230ac9a37e2SJisheng Zhang			};
231ac9a37e2SJisheng Zhang
232ac9a37e2SJisheng Zhang			vdd_cpu: dcdc2 {
233ac9a37e2SJisheng Zhang				regulator-always-on;
234ac9a37e2SJisheng Zhang				regulator-min-microvolt = <500000>;
235ac9a37e2SJisheng Zhang				regulator-max-microvolt = <1540000>;
236ac9a37e2SJisheng Zhang				regulator-name = "vdd-cpu";
237ac9a37e2SJisheng Zhang			};
238ac9a37e2SJisheng Zhang
239ac9a37e2SJisheng Zhang			emmc_vdd: aldo4 {
240ac9a37e2SJisheng Zhang				regulator-boot-on;
241ac9a37e2SJisheng Zhang				regulator-always-on;
242ac9a37e2SJisheng Zhang				regulator-min-microvolt = <1800000>;
243ac9a37e2SJisheng Zhang				regulator-max-microvolt = <3300000>;
244ac9a37e2SJisheng Zhang				regulator-name = "emmc_vdd";
245ac9a37e2SJisheng Zhang			};
246ac9a37e2SJisheng Zhang		};
2473c1f81a1SShengyu Qu	};
248ac9a37e2SJisheng Zhang};
249ac9a37e2SJisheng Zhang
250ac9a37e2SJisheng Zhang&i2c6 {
251ac9a37e2SJisheng Zhang	clock-frequency = <100000>;
252ac9a37e2SJisheng Zhang	i2c-sda-hold-time-ns = <300>;
253ac9a37e2SJisheng Zhang	i2c-sda-falling-time-ns = <510>;
254ac9a37e2SJisheng Zhang	i2c-scl-falling-time-ns = <510>;
255ac9a37e2SJisheng Zhang	pinctrl-names = "default";
256ac9a37e2SJisheng Zhang	pinctrl-0 = <&i2c6_pins>;
257ac9a37e2SJisheng Zhang	status = "okay";
258ac9a37e2SJisheng Zhang};
259ac9a37e2SJisheng Zhang
260ac9a37e2SJisheng Zhang&mmc0 {
261ac9a37e2SJisheng Zhang	max-frequency = <100000000>;
262ac9a37e2SJisheng Zhang	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
263ac9a37e2SJisheng Zhang	assigned-clock-rates = <50000000>;
264ac9a37e2SJisheng Zhang	bus-width = <8>;
265ac9a37e2SJisheng Zhang	cap-mmc-highspeed;
266ac9a37e2SJisheng Zhang	mmc-ddr-1_8v;
267ac9a37e2SJisheng Zhang	mmc-hs200-1_8v;
268ac9a37e2SJisheng Zhang	cap-mmc-hw-reset;
269ac9a37e2SJisheng Zhang	post-power-on-delay-ms = <200>;
270ac9a37e2SJisheng Zhang	pinctrl-names = "default";
271ac9a37e2SJisheng Zhang	pinctrl-0 = <&mmc0_pins>;
272ac9a37e2SJisheng Zhang	vmmc-supply = <&vcc_3v3>;
273ac9a37e2SJisheng Zhang	vqmmc-supply = <&emmc_vdd>;
274ac9a37e2SJisheng Zhang	status = "okay";
275ac9a37e2SJisheng Zhang};
276ac9a37e2SJisheng Zhang
277ac9a37e2SJisheng Zhang&mmc1 {
278ac9a37e2SJisheng Zhang	max-frequency = <100000000>;
279ac9a37e2SJisheng Zhang	assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
280ac9a37e2SJisheng Zhang	assigned-clock-rates = <50000000>;
281ac9a37e2SJisheng Zhang	bus-width = <4>;
282ac9a37e2SJisheng Zhang	no-sdio;
283ac9a37e2SJisheng Zhang	no-mmc;
284ac9a37e2SJisheng Zhang	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
285ac9a37e2SJisheng Zhang	disable-wp;
286ac9a37e2SJisheng Zhang	cap-sd-highspeed;
287ac9a37e2SJisheng Zhang	post-power-on-delay-ms = <200>;
288ac9a37e2SJisheng Zhang	pinctrl-names = "default";
289ac9a37e2SJisheng Zhang	pinctrl-0 = <&mmc1_pins>;
290ac9a37e2SJisheng Zhang	status = "okay";
291ac9a37e2SJisheng Zhang};
292ac9a37e2SJisheng Zhang
293ac9a37e2SJisheng Zhang&pcie0 {
294ac9a37e2SJisheng Zhang	perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
295ac9a37e2SJisheng Zhang	phys = <&pciephy0>;
296ac9a37e2SJisheng Zhang	pinctrl-names = "default";
2972904244aSMinda Chen	pinctrl-0 = <&pcie0_pins>;
2982904244aSMinda Chen};
2992904244aSMinda Chen
3002904244aSMinda Chen&pcie1 {
3012904244aSMinda Chen	perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
3022904244aSMinda Chen	phys = <&pciephy1>;
3032904244aSMinda Chen	pinctrl-names = "default";
3042904244aSMinda Chen	pinctrl-0 = <&pcie1_pins>;
3052904244aSMinda Chen};
3062904244aSMinda Chen
3072904244aSMinda Chen&pwmdac {
3082904244aSMinda Chen	pinctrl-names = "default";
3092904244aSMinda Chen	pinctrl-0 = <&pwmdac_pins>;
3102904244aSMinda Chen};
311ac9a37e2SJisheng Zhang
312ac9a37e2SJisheng Zhang&qspi {
313ac9a37e2SJisheng Zhang	#address-cells = <1>;
314ac9a37e2SJisheng Zhang	#size-cells = <0>;
315ac9a37e2SJisheng Zhang	status = "okay";
316ac9a37e2SJisheng Zhang
317ac9a37e2SJisheng Zhang	nor_flash: flash@0 {
318ac9a37e2SJisheng Zhang		compatible = "jedec,spi-nor";
319ac9a37e2SJisheng Zhang		reg = <0>;
320ac9a37e2SJisheng Zhang		cdns,read-delay = <5>;
321ac9a37e2SJisheng Zhang		spi-max-frequency = <12000000>;
322ac9a37e2SJisheng Zhang		cdns,tshsl-ns = <1>;
323ac9a37e2SJisheng Zhang		cdns,tsd2d-ns = <1>;
324ac9a37e2SJisheng Zhang		cdns,tchsh-ns = <1>;
325ac9a37e2SJisheng Zhang		cdns,tslch-ns = <1>;
326ac9a37e2SJisheng Zhang
327ac9a37e2SJisheng Zhang		partitions {
328ac9a37e2SJisheng Zhang			compatible = "fixed-partitions";
329ac9a37e2SJisheng Zhang			#address-cells = <1>;
330ac9a37e2SJisheng Zhang			#size-cells = <1>;
331ac9a37e2SJisheng Zhang
332ac9a37e2SJisheng Zhang			spl@0 {
333ac9a37e2SJisheng Zhang				reg = <0x0 0xf0000>;
334ac9a37e2SJisheng Zhang			};
335ac9a37e2SJisheng Zhang			uboot-env@f0000 {
336ac9a37e2SJisheng Zhang				reg = <0xf0000 0x10000>;
337ac9a37e2SJisheng Zhang			};
338edbce932SMatthias Brugger			uboot@100000 {
339ac9a37e2SJisheng Zhang				reg = <0x100000 0xf00000>;
340ac9a37e2SJisheng Zhang			};
341ac9a37e2SJisheng Zhang		};
342ac9a37e2SJisheng Zhang	};
343ac9a37e2SJisheng Zhang};
344edbce932SMatthias Brugger
345ac9a37e2SJisheng Zhang&pwm {
346ac9a37e2SJisheng Zhang	pinctrl-names = "default";
347ac9a37e2SJisheng Zhang	pinctrl-0 = <&pwm_pins>;
348ac9a37e2SJisheng Zhang};
349ac9a37e2SJisheng Zhang
350ac9a37e2SJisheng Zhang&spi0 {
351ac9a37e2SJisheng Zhang	pinctrl-names = "default";
352ac9a37e2SJisheng Zhang	pinctrl-0 = <&spi0_pins>;
353ac9a37e2SJisheng Zhang
354ac9a37e2SJisheng Zhang	spi_dev0: spi@0 {
355ac9a37e2SJisheng Zhang		compatible = "rohm,dh2228fv";
356ac9a37e2SJisheng Zhang		reg = <0>;
357ac9a37e2SJisheng Zhang		spi-max-frequency = <10000000>;
358ac9a37e2SJisheng Zhang	};
359ac9a37e2SJisheng Zhang};
360ac9a37e2SJisheng Zhang
361ac9a37e2SJisheng Zhang&syscrg {
362ac9a37e2SJisheng Zhang	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>,
363ac9a37e2SJisheng Zhang			  <&pllclk JH7110_PLLCLK_PLL0_OUT>;
364ac9a37e2SJisheng Zhang	assigned-clock-rates = <500000000>, <1500000000>;
365ac9a37e2SJisheng Zhang};
366ac9a37e2SJisheng Zhang
367ac9a37e2SJisheng Zhang&sysgpio {
368*61f2e8a3SXingyu Wu	i2c0_pins: i2c0-0 {
369*61f2e8a3SXingyu Wu		i2c-pins {
370*61f2e8a3SXingyu Wu			pinmux = <GPIOMUX(57, GPOUT_LOW,
371*61f2e8a3SXingyu Wu					      GPOEN_SYS_I2C0_CLK,
372*61f2e8a3SXingyu Wu					      GPI_SYS_I2C0_CLK)>,
373*61f2e8a3SXingyu Wu				 <GPIOMUX(58, GPOUT_LOW,
374ac9a37e2SJisheng Zhang					      GPOEN_SYS_I2C0_DATA,
375ac9a37e2SJisheng Zhang					      GPI_SYS_I2C0_DATA)>;
376ac9a37e2SJisheng Zhang			bias-disable; /* external pull-up */
377ac9a37e2SJisheng Zhang			input-enable;
378ac9a37e2SJisheng Zhang			input-schmitt-enable;
379ac9a37e2SJisheng Zhang		};
380ac9a37e2SJisheng Zhang	};
381ac9a37e2SJisheng Zhang
382ac9a37e2SJisheng Zhang	i2c2_pins: i2c2-0 {
383ac9a37e2SJisheng Zhang		i2c-pins {
384ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(3, GPOUT_LOW,
385ac9a37e2SJisheng Zhang					     GPOEN_SYS_I2C2_CLK,
386ac9a37e2SJisheng Zhang					     GPI_SYS_I2C2_CLK)>,
387ac9a37e2SJisheng Zhang				 <GPIOMUX(2, GPOUT_LOW,
388ac9a37e2SJisheng Zhang					     GPOEN_SYS_I2C2_DATA,
389ac9a37e2SJisheng Zhang					     GPI_SYS_I2C2_DATA)>;
390ac9a37e2SJisheng Zhang			bias-disable; /* external pull-up */
391ac9a37e2SJisheng Zhang			input-enable;
392ac9a37e2SJisheng Zhang			input-schmitt-enable;
393ac9a37e2SJisheng Zhang		};
394ac9a37e2SJisheng Zhang	};
395ac9a37e2SJisheng Zhang
396ac9a37e2SJisheng Zhang	i2c5_pins: i2c5-0 {
397ac9a37e2SJisheng Zhang		i2c-pins {
398ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(19, GPOUT_LOW,
399ac9a37e2SJisheng Zhang					      GPOEN_SYS_I2C5_CLK,
400ac9a37e2SJisheng Zhang					      GPI_SYS_I2C5_CLK)>,
401ac9a37e2SJisheng Zhang				 <GPIOMUX(20, GPOUT_LOW,
402ac9a37e2SJisheng Zhang					      GPOEN_SYS_I2C5_DATA,
403ac9a37e2SJisheng Zhang					      GPI_SYS_I2C5_DATA)>;
404ac9a37e2SJisheng Zhang			bias-disable; /* external pull-up */
405ac9a37e2SJisheng Zhang			input-enable;
406ac9a37e2SJisheng Zhang			input-schmitt-enable;
407ac9a37e2SJisheng Zhang		};
408ac9a37e2SJisheng Zhang	};
409ac9a37e2SJisheng Zhang
410ac9a37e2SJisheng Zhang	i2c6_pins: i2c6-0 {
411ac9a37e2SJisheng Zhang		i2c-pins {
412ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(16, GPOUT_LOW,
413ac9a37e2SJisheng Zhang					      GPOEN_SYS_I2C6_CLK,
414ac9a37e2SJisheng Zhang					      GPI_SYS_I2C6_CLK)>,
415ac9a37e2SJisheng Zhang				 <GPIOMUX(17, GPOUT_LOW,
416ac9a37e2SJisheng Zhang					      GPOEN_SYS_I2C6_DATA,
417ac9a37e2SJisheng Zhang					      GPI_SYS_I2C6_DATA)>;
418ac9a37e2SJisheng Zhang			bias-disable; /* external pull-up */
419ac9a37e2SJisheng Zhang			input-enable;
420ac9a37e2SJisheng Zhang			input-schmitt-enable;
421ac9a37e2SJisheng Zhang		};
422ac9a37e2SJisheng Zhang	};
423ac9a37e2SJisheng Zhang
424ac9a37e2SJisheng Zhang	mmc0_pins: mmc0-0 {
425ac9a37e2SJisheng Zhang		 rst-pins {
426ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
427ac9a37e2SJisheng Zhang					      GPOEN_ENABLE,
428ac9a37e2SJisheng Zhang					      GPI_NONE)>;
429ac9a37e2SJisheng Zhang			bias-pull-up;
430ac9a37e2SJisheng Zhang			drive-strength = <12>;
431ac9a37e2SJisheng Zhang			input-disable;
432ac9a37e2SJisheng Zhang			input-schmitt-disable;
433ac9a37e2SJisheng Zhang			slew-rate = <0>;
434ac9a37e2SJisheng Zhang		};
435ac9a37e2SJisheng Zhang
436ac9a37e2SJisheng Zhang		mmc-pins {
437ac9a37e2SJisheng Zhang			pinmux = <PINMUX(64, 0)>,
438ac9a37e2SJisheng Zhang				 <PINMUX(65, 0)>,
439ac9a37e2SJisheng Zhang				 <PINMUX(66, 0)>,
440ac9a37e2SJisheng Zhang				 <PINMUX(67, 0)>,
441ac9a37e2SJisheng Zhang				 <PINMUX(68, 0)>,
442ac9a37e2SJisheng Zhang				 <PINMUX(69, 0)>,
443ac9a37e2SJisheng Zhang				 <PINMUX(70, 0)>,
444ac9a37e2SJisheng Zhang				 <PINMUX(71, 0)>,
445ac9a37e2SJisheng Zhang				 <PINMUX(72, 0)>,
446ac9a37e2SJisheng Zhang				 <PINMUX(73, 0)>;
447ac9a37e2SJisheng Zhang			bias-pull-up;
448ac9a37e2SJisheng Zhang			drive-strength = <12>;
449ac9a37e2SJisheng Zhang			input-enable;
450ac9a37e2SJisheng Zhang		};
451ac9a37e2SJisheng Zhang	};
452ac9a37e2SJisheng Zhang
453ac9a37e2SJisheng Zhang	mmc1_pins: mmc1-0 {
454ac9a37e2SJisheng Zhang		clk-pins {
455ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
456ac9a37e2SJisheng Zhang					      GPOEN_ENABLE,
457ac9a37e2SJisheng Zhang					      GPI_NONE)>;
458ac9a37e2SJisheng Zhang			bias-pull-up;
459ac9a37e2SJisheng Zhang			drive-strength = <12>;
460ac9a37e2SJisheng Zhang			input-disable;
461ac9a37e2SJisheng Zhang			input-schmitt-disable;
462ac9a37e2SJisheng Zhang			slew-rate = <0>;
463ac9a37e2SJisheng Zhang		};
464ac9a37e2SJisheng Zhang
465ac9a37e2SJisheng Zhang		mmc-pins {
466ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
467ac9a37e2SJisheng Zhang					     GPOEN_SYS_SDIO1_CMD,
468ac9a37e2SJisheng Zhang					     GPI_SYS_SDIO1_CMD)>,
469ac9a37e2SJisheng Zhang				 <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
470ac9a37e2SJisheng Zhang					      GPOEN_SYS_SDIO1_DATA0,
471ac9a37e2SJisheng Zhang					      GPI_SYS_SDIO1_DATA0)>,
472ac9a37e2SJisheng Zhang				 <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
473ac9a37e2SJisheng Zhang					      GPOEN_SYS_SDIO1_DATA1,
474ac9a37e2SJisheng Zhang					      GPI_SYS_SDIO1_DATA1)>,
475ac9a37e2SJisheng Zhang				 <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
476ac9a37e2SJisheng Zhang					     GPOEN_SYS_SDIO1_DATA2,
477ac9a37e2SJisheng Zhang					     GPI_SYS_SDIO1_DATA2)>,
478ac9a37e2SJisheng Zhang				 <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
479ac9a37e2SJisheng Zhang					     GPOEN_SYS_SDIO1_DATA3,
480ac9a37e2SJisheng Zhang					     GPI_SYS_SDIO1_DATA3)>;
481ac9a37e2SJisheng Zhang			bias-pull-up;
482ac9a37e2SJisheng Zhang			drive-strength = <12>;
483ac9a37e2SJisheng Zhang			input-enable;
484ac9a37e2SJisheng Zhang			input-schmitt-enable;
485ac9a37e2SJisheng Zhang			slew-rate = <0>;
486ac9a37e2SJisheng Zhang		};
487ac9a37e2SJisheng Zhang	};
488ac9a37e2SJisheng Zhang
489ac9a37e2SJisheng Zhang	pcie0_pins: pcie0-0 {
490ac9a37e2SJisheng Zhang		clkreq-pins {
491ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(27, GPOUT_LOW,
492ac9a37e2SJisheng Zhang					      GPOEN_DISABLE,
493ac9a37e2SJisheng Zhang					      GPI_NONE)>;
494ac9a37e2SJisheng Zhang			bias-pull-down;
495ac9a37e2SJisheng Zhang			drive-strength = <2>;
4962904244aSMinda Chen			input-enable;
4972904244aSMinda Chen			input-schmitt-disable;
4982904244aSMinda Chen			slew-rate = <0>;
4992904244aSMinda Chen		};
5002904244aSMinda Chen
5012904244aSMinda Chen		wake-pins {
5022904244aSMinda Chen			pinmux = <GPIOMUX(32, GPOUT_LOW,
5032904244aSMinda Chen					      GPOEN_DISABLE,
5042904244aSMinda Chen					      GPI_NONE)>;
5052904244aSMinda Chen			bias-pull-up;
5062904244aSMinda Chen			drive-strength = <2>;
5072904244aSMinda Chen			input-enable;
5082904244aSMinda Chen			input-schmitt-disable;
5092904244aSMinda Chen			slew-rate = <0>;
5102904244aSMinda Chen		};
5112904244aSMinda Chen	};
5122904244aSMinda Chen
5132904244aSMinda Chen	pcie1_pins: pcie1-0 {
5142904244aSMinda Chen		clkreq-pins {
5152904244aSMinda Chen			pinmux = <GPIOMUX(29, GPOUT_LOW,
5162904244aSMinda Chen					      GPOEN_DISABLE,
5172904244aSMinda Chen					      GPI_NONE)>;
5182904244aSMinda Chen			bias-pull-down;
5192904244aSMinda Chen			drive-strength = <2>;
5202904244aSMinda Chen			input-enable;
5212904244aSMinda Chen			input-schmitt-disable;
5222904244aSMinda Chen			slew-rate = <0>;
5232904244aSMinda Chen		};
5242904244aSMinda Chen
5252904244aSMinda Chen		wake-pins {
5262904244aSMinda Chen			pinmux = <GPIOMUX(21, GPOUT_LOW,
5272904244aSMinda Chen				      GPOEN_DISABLE,
5282904244aSMinda Chen					      GPI_NONE)>;
5292904244aSMinda Chen			bias-pull-up;
5302904244aSMinda Chen			drive-strength = <2>;
5312904244aSMinda Chen			input-enable;
5322904244aSMinda Chen			input-schmitt-disable;
5332904244aSMinda Chen			slew-rate = <0>;
5342904244aSMinda Chen		};
5352904244aSMinda Chen	};
5362904244aSMinda Chen
5372904244aSMinda Chen	pwmdac_pins: pwmdac-0 {
5382904244aSMinda Chen		pwmdac-pins {
5392904244aSMinda Chen			pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,
5402904244aSMinda Chen					      GPOEN_ENABLE,
5412904244aSMinda Chen					      GPI_NONE)>,
5422904244aSMinda Chen				 <GPIOMUX(34, GPOUT_SYS_PWMDAC_RIGHT,
5432904244aSMinda Chen					      GPOEN_ENABLE,
544ac9a37e2SJisheng Zhang					      GPI_NONE)>;
545ac9a37e2SJisheng Zhang			bias-disable;
546ac9a37e2SJisheng Zhang			drive-strength = <2>;
547ac9a37e2SJisheng Zhang			input-disable;
548ac9a37e2SJisheng Zhang			input-schmitt-disable;
549ac9a37e2SJisheng Zhang			slew-rate = <0>;
550ac9a37e2SJisheng Zhang		};
551ac9a37e2SJisheng Zhang	};
552ac9a37e2SJisheng Zhang
553ac9a37e2SJisheng Zhang	pwm_pins: pwm-0 {
554ac9a37e2SJisheng Zhang		pwm-pins {
555ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
556ac9a37e2SJisheng Zhang					      GPOEN_SYS_PWM0_CHANNEL0,
557ac9a37e2SJisheng Zhang					      GPI_NONE)>,
558ac9a37e2SJisheng Zhang				 <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
559ac9a37e2SJisheng Zhang					      GPOEN_SYS_PWM0_CHANNEL1,
560ac9a37e2SJisheng Zhang					      GPI_NONE)>;
561ac9a37e2SJisheng Zhang			bias-disable;
562ac9a37e2SJisheng Zhang			drive-strength = <12>;
563ac9a37e2SJisheng Zhang			input-disable;
564ac9a37e2SJisheng Zhang			input-schmitt-disable;
565ac9a37e2SJisheng Zhang			slew-rate = <0>;
566ac9a37e2SJisheng Zhang		};
567ac9a37e2SJisheng Zhang	};
568ac9a37e2SJisheng Zhang
569ac9a37e2SJisheng Zhang	spi0_pins: spi0-0 {
570ac9a37e2SJisheng Zhang		mosi-pins {
571ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
572ac9a37e2SJisheng Zhang					      GPOEN_ENABLE,
573ac9a37e2SJisheng Zhang					      GPI_NONE)>;
574ac9a37e2SJisheng Zhang			bias-disable;
575ac9a37e2SJisheng Zhang			input-disable;
576ac9a37e2SJisheng Zhang			input-schmitt-disable;
577ac9a37e2SJisheng Zhang		};
578ac9a37e2SJisheng Zhang
579ac9a37e2SJisheng Zhang		miso-pins {
580ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(53, GPOUT_LOW,
581ac9a37e2SJisheng Zhang					      GPOEN_DISABLE,
582ac9a37e2SJisheng Zhang					      GPI_SYS_SPI0_RXD)>;
583ac9a37e2SJisheng Zhang			bias-pull-up;
584ac9a37e2SJisheng Zhang			input-enable;
585ac9a37e2SJisheng Zhang			input-schmitt-enable;
586ac9a37e2SJisheng Zhang		};
587ac9a37e2SJisheng Zhang
588ac9a37e2SJisheng Zhang		sck-pins {
589ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
590ac9a37e2SJisheng Zhang					      GPOEN_ENABLE,
591ac9a37e2SJisheng Zhang					      GPI_SYS_SPI0_CLK)>;
592ac9a37e2SJisheng Zhang			bias-disable;
593ac9a37e2SJisheng Zhang			input-disable;
594ac9a37e2SJisheng Zhang			input-schmitt-disable;
595ac9a37e2SJisheng Zhang		};
596ac9a37e2SJisheng Zhang
597ac9a37e2SJisheng Zhang		ss-pins {
598ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
599ac9a37e2SJisheng Zhang					      GPOEN_ENABLE,
600ac9a37e2SJisheng Zhang					      GPI_SYS_SPI0_FSS)>;
601ac9a37e2SJisheng Zhang			bias-disable;
602ac9a37e2SJisheng Zhang			input-disable;
603ac9a37e2SJisheng Zhang			input-schmitt-disable;
604ac9a37e2SJisheng Zhang		};
605ac9a37e2SJisheng Zhang	};
606ac9a37e2SJisheng Zhang
607ac9a37e2SJisheng Zhang	uart0_pins: uart0-0 {
608ac9a37e2SJisheng Zhang		tx-pins {
609ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
610ac9a37e2SJisheng Zhang					     GPOEN_ENABLE,
611ac9a37e2SJisheng Zhang					     GPI_NONE)>;
612ac9a37e2SJisheng Zhang			bias-disable;
613ac9a37e2SJisheng Zhang			drive-strength = <12>;
614ac9a37e2SJisheng Zhang			input-disable;
615ac9a37e2SJisheng Zhang			input-schmitt-disable;
616ac9a37e2SJisheng Zhang			slew-rate = <0>;
617ac9a37e2SJisheng Zhang		};
618ac9a37e2SJisheng Zhang
619ac9a37e2SJisheng Zhang		rx-pins {
620ac9a37e2SJisheng Zhang			pinmux = <GPIOMUX(6, GPOUT_LOW,
621ac9a37e2SJisheng Zhang					     GPOEN_DISABLE,
622ac9a37e2SJisheng Zhang					     GPI_SYS_UART0_RX)>;
623ac9a37e2SJisheng Zhang			bias-disable; /* external pull-up */
624ac9a37e2SJisheng Zhang			drive-strength = <2>;
625ac9a37e2SJisheng Zhang			input-enable;
626ac9a37e2SJisheng Zhang			input-schmitt-enable;
627ac9a37e2SJisheng Zhang			slew-rate = <0>;
628ac9a37e2SJisheng Zhang		};
629ac9a37e2SJisheng Zhang	};
630ac9a37e2SJisheng Zhang};
631ac9a37e2SJisheng Zhang
632ac9a37e2SJisheng Zhang&uart0 {
633ac9a37e2SJisheng Zhang	pinctrl-names = "default";
634ac9a37e2SJisheng Zhang	pinctrl-0 = <&uart0_pins>;
635ac9a37e2SJisheng Zhang	status = "okay";
636ac9a37e2SJisheng Zhang};
637ac9a37e2SJisheng Zhang
638ac9a37e2SJisheng Zhang&U74_1 {
639ac9a37e2SJisheng Zhang	cpu-supply = <&vdd_cpu>;
640ac9a37e2SJisheng Zhang};
641ac9a37e2SJisheng Zhang
642ac9a37e2SJisheng Zhang&U74_2 {
643ac9a37e2SJisheng Zhang	cpu-supply = <&vdd_cpu>;
644ac9a37e2SJisheng Zhang};
645ac9a37e2SJisheng Zhang
646ac9a37e2SJisheng Zhang&U74_3 {
647ac9a37e2SJisheng Zhang	cpu-supply = <&vdd_cpu>;
648ac9a37e2SJisheng Zhang};
649ac9a37e2SJisheng Zhang
650ac9a37e2SJisheng Zhang&U74_4 {
651ac9a37e2SJisheng Zhang	cpu-supply = <&vdd_cpu>;
652ac9a37e2SJisheng Zhang};
653ac9a37e2SJisheng Zhang