1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020 SiFive, Inc */ 3 4/dts-v1/; 5 6#include <dt-bindings/clock/sifive-fu740-prci.h> 7 8/ { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 compatible = "sifive,fu740-c000", "sifive,fu740"; 12 13 aliases { 14 serial0 = &uart0; 15 serial1 = &uart1; 16 ethernet0 = ð0; 17 }; 18 19 chosen { 20 }; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 cpu0: cpu@0 { 26 compatible = "sifive,bullet0", "riscv"; 27 device_type = "cpu"; 28 i-cache-block-size = <64>; 29 i-cache-sets = <128>; 30 i-cache-size = <16384>; 31 next-level-cache = <&ccache>; 32 reg = <0x0>; 33 riscv,isa = "rv64imac"; 34 status = "disabled"; 35 cpu0_intc: interrupt-controller { 36 #interrupt-cells = <1>; 37 compatible = "riscv,cpu-intc"; 38 interrupt-controller; 39 }; 40 }; 41 cpu1: cpu@1 { 42 compatible = "sifive,bullet0", "riscv"; 43 d-cache-block-size = <64>; 44 d-cache-sets = <64>; 45 d-cache-size = <32768>; 46 d-tlb-sets = <1>; 47 d-tlb-size = <40>; 48 device_type = "cpu"; 49 i-cache-block-size = <64>; 50 i-cache-sets = <128>; 51 i-cache-size = <32768>; 52 i-tlb-sets = <1>; 53 i-tlb-size = <40>; 54 mmu-type = "riscv,sv39"; 55 next-level-cache = <&ccache>; 56 reg = <0x1>; 57 riscv,isa = "rv64imafdc"; 58 tlb-split; 59 cpu1_intc: interrupt-controller { 60 #interrupt-cells = <1>; 61 compatible = "riscv,cpu-intc"; 62 interrupt-controller; 63 }; 64 }; 65 cpu2: cpu@2 { 66 compatible = "sifive,bullet0", "riscv"; 67 d-cache-block-size = <64>; 68 d-cache-sets = <64>; 69 d-cache-size = <32768>; 70 d-tlb-sets = <1>; 71 d-tlb-size = <40>; 72 device_type = "cpu"; 73 i-cache-block-size = <64>; 74 i-cache-sets = <128>; 75 i-cache-size = <32768>; 76 i-tlb-sets = <1>; 77 i-tlb-size = <40>; 78 mmu-type = "riscv,sv39"; 79 next-level-cache = <&ccache>; 80 reg = <0x2>; 81 riscv,isa = "rv64imafdc"; 82 tlb-split; 83 cpu2_intc: interrupt-controller { 84 #interrupt-cells = <1>; 85 compatible = "riscv,cpu-intc"; 86 interrupt-controller; 87 }; 88 }; 89 cpu3: cpu@3 { 90 compatible = "sifive,bullet0", "riscv"; 91 d-cache-block-size = <64>; 92 d-cache-sets = <64>; 93 d-cache-size = <32768>; 94 d-tlb-sets = <1>; 95 d-tlb-size = <40>; 96 device_type = "cpu"; 97 i-cache-block-size = <64>; 98 i-cache-sets = <128>; 99 i-cache-size = <32768>; 100 i-tlb-sets = <1>; 101 i-tlb-size = <40>; 102 mmu-type = "riscv,sv39"; 103 next-level-cache = <&ccache>; 104 reg = <0x3>; 105 riscv,isa = "rv64imafdc"; 106 tlb-split; 107 cpu3_intc: interrupt-controller { 108 #interrupt-cells = <1>; 109 compatible = "riscv,cpu-intc"; 110 interrupt-controller; 111 }; 112 }; 113 cpu4: cpu@4 { 114 compatible = "sifive,bullet0", "riscv"; 115 d-cache-block-size = <64>; 116 d-cache-sets = <64>; 117 d-cache-size = <32768>; 118 d-tlb-sets = <1>; 119 d-tlb-size = <40>; 120 device_type = "cpu"; 121 i-cache-block-size = <64>; 122 i-cache-sets = <128>; 123 i-cache-size = <32768>; 124 i-tlb-sets = <1>; 125 i-tlb-size = <40>; 126 mmu-type = "riscv,sv39"; 127 next-level-cache = <&ccache>; 128 reg = <0x4>; 129 riscv,isa = "rv64imafdc"; 130 tlb-split; 131 cpu4_intc: interrupt-controller { 132 #interrupt-cells = <1>; 133 compatible = "riscv,cpu-intc"; 134 interrupt-controller; 135 }; 136 }; 137 }; 138 soc { 139 #address-cells = <2>; 140 #size-cells = <2>; 141 compatible = "simple-bus"; 142 ranges; 143 plic0: interrupt-controller@c000000 { 144 #interrupt-cells = <1>; 145 #address-cells = <0>; 146 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 147 reg = <0x0 0xc000000 0x0 0x4000000>; 148 riscv,ndev = <69>; 149 interrupt-controller; 150 interrupts-extended = < 151 &cpu0_intc 0xffffffff 152 &cpu1_intc 0xffffffff &cpu1_intc 9 153 &cpu2_intc 0xffffffff &cpu2_intc 9 154 &cpu3_intc 0xffffffff &cpu3_intc 9 155 &cpu4_intc 0xffffffff &cpu4_intc 9>; 156 }; 157 prci: clock-controller@10000000 { 158 compatible = "sifive,fu740-c000-prci"; 159 reg = <0x0 0x10000000 0x0 0x1000>; 160 clocks = <&hfclk>, <&rtcclk>; 161 #clock-cells = <1>; 162 }; 163 uart0: serial@10010000 { 164 compatible = "sifive,fu740-c000-uart", "sifive,uart0"; 165 reg = <0x0 0x10010000 0x0 0x1000>; 166 interrupt-parent = <&plic0>; 167 interrupts = <39>; 168 clocks = <&prci PRCI_CLK_PCLK>; 169 status = "disabled"; 170 }; 171 uart1: serial@10011000 { 172 compatible = "sifive,fu740-c000-uart", "sifive,uart0"; 173 reg = <0x0 0x10011000 0x0 0x1000>; 174 interrupt-parent = <&plic0>; 175 interrupts = <40>; 176 clocks = <&prci PRCI_CLK_PCLK>; 177 status = "disabled"; 178 }; 179 i2c0: i2c@10030000 { 180 compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; 181 reg = <0x0 0x10030000 0x0 0x1000>; 182 interrupt-parent = <&plic0>; 183 interrupts = <52>; 184 clocks = <&prci PRCI_CLK_PCLK>; 185 reg-shift = <2>; 186 reg-io-width = <1>; 187 #address-cells = <1>; 188 #size-cells = <0>; 189 status = "disabled"; 190 }; 191 i2c1: i2c@10031000 { 192 compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; 193 reg = <0x0 0x10031000 0x0 0x1000>; 194 interrupt-parent = <&plic0>; 195 interrupts = <53>; 196 clocks = <&prci PRCI_CLK_PCLK>; 197 reg-shift = <2>; 198 reg-io-width = <1>; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 status = "disabled"; 202 }; 203 qspi0: spi@10040000 { 204 compatible = "sifive,fu740-c000-spi", "sifive,spi0"; 205 reg = <0x0 0x10040000 0x0 0x1000>, 206 <0x0 0x20000000 0x0 0x10000000>; 207 interrupt-parent = <&plic0>; 208 interrupts = <41>; 209 clocks = <&prci PRCI_CLK_PCLK>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 status = "disabled"; 213 }; 214 qspi1: spi@10041000 { 215 compatible = "sifive,fu740-c000-spi", "sifive,spi0"; 216 reg = <0x0 0x10041000 0x0 0x1000>, 217 <0x0 0x30000000 0x0 0x10000000>; 218 interrupt-parent = <&plic0>; 219 interrupts = <42>; 220 clocks = <&prci PRCI_CLK_PCLK>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 status = "disabled"; 224 }; 225 spi0: spi@10050000 { 226 compatible = "sifive,fu740-c000-spi", "sifive,spi0"; 227 reg = <0x0 0x10050000 0x0 0x1000>; 228 interrupt-parent = <&plic0>; 229 interrupts = <43>; 230 clocks = <&prci PRCI_CLK_PCLK>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 status = "disabled"; 234 }; 235 eth0: ethernet@10090000 { 236 compatible = "sifive,fu540-c000-gem"; 237 interrupt-parent = <&plic0>; 238 interrupts = <55>; 239 reg = <0x0 0x10090000 0x0 0x2000>, 240 <0x0 0x100a0000 0x0 0x1000>; 241 local-mac-address = [00 00 00 00 00 00]; 242 clock-names = "pclk", "hclk"; 243 clocks = <&prci PRCI_CLK_GEMGXLPLL>, 244 <&prci PRCI_CLK_GEMGXLPLL>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 status = "disabled"; 248 }; 249 pwm0: pwm@10020000 { 250 compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; 251 reg = <0x0 0x10020000 0x0 0x1000>; 252 interrupt-parent = <&plic0>; 253 interrupts = <44>, <45>, <46>, <47>; 254 clocks = <&prci PRCI_CLK_PCLK>; 255 #pwm-cells = <3>; 256 status = "disabled"; 257 }; 258 pwm1: pwm@10021000 { 259 compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; 260 reg = <0x0 0x10021000 0x0 0x1000>; 261 interrupt-parent = <&plic0>; 262 interrupts = <48>, <49>, <50>, <51>; 263 clocks = <&prci PRCI_CLK_PCLK>; 264 #pwm-cells = <3>; 265 status = "disabled"; 266 }; 267 ccache: cache-controller@2010000 { 268 compatible = "sifive,fu740-c000-ccache", "cache"; 269 cache-block-size = <64>; 270 cache-level = <2>; 271 cache-sets = <2048>; 272 cache-size = <2097152>; 273 cache-unified; 274 interrupt-parent = <&plic0>; 275 interrupts = <19 20 21 22>; 276 reg = <0x0 0x2010000 0x0 0x1000>; 277 }; 278 gpio: gpio@10060000 { 279 compatible = "sifive,fu740-c000-gpio", "sifive,gpio0"; 280 interrupt-parent = <&plic0>; 281 interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, 282 <30>, <31>, <32>, <33>, <34>, <35>, <36>, 283 <37>, <38>; 284 reg = <0x0 0x10060000 0x0 0x1000>; 285 gpio-controller; 286 #gpio-cells = <2>; 287 interrupt-controller; 288 #interrupt-cells = <2>; 289 clocks = <&prci PRCI_CLK_PCLK>; 290 status = "disabled"; 291 }; 292 }; 293}; 294