1*b3e77da0SLad Prabhakar// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*b3e77da0SLad Prabhakar/* 3*b3e77da0SLad Prabhakar * Device Tree Source for the RZ/Five SoC 4*b3e77da0SLad Prabhakar * 5*b3e77da0SLad Prabhakar * Copyright (C) 2022 Renesas Electronics Corp. 6*b3e77da0SLad Prabhakar */ 7*b3e77da0SLad Prabhakar 8*b3e77da0SLad Prabhakar#include <dt-bindings/interrupt-controller/irq.h> 9*b3e77da0SLad Prabhakar 10*b3e77da0SLad Prabhakar#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) 11*b3e77da0SLad Prabhakar 12*b3e77da0SLad Prabhakar#include <arm64/renesas/r9a07g043.dtsi> 13*b3e77da0SLad Prabhakar 14*b3e77da0SLad Prabhakar/ { 15*b3e77da0SLad Prabhakar cpus { 16*b3e77da0SLad Prabhakar #address-cells = <1>; 17*b3e77da0SLad Prabhakar #size-cells = <0>; 18*b3e77da0SLad Prabhakar timebase-frequency = <12000000>; 19*b3e77da0SLad Prabhakar 20*b3e77da0SLad Prabhakar cpu0: cpu@0 { 21*b3e77da0SLad Prabhakar compatible = "andestech,ax45mp", "riscv"; 22*b3e77da0SLad Prabhakar device_type = "cpu"; 23*b3e77da0SLad Prabhakar reg = <0x0>; 24*b3e77da0SLad Prabhakar status = "okay"; 25*b3e77da0SLad Prabhakar riscv,isa = "rv64imafdc"; 26*b3e77da0SLad Prabhakar mmu-type = "riscv,sv39"; 27*b3e77da0SLad Prabhakar i-cache-size = <0x8000>; 28*b3e77da0SLad Prabhakar i-cache-line-size = <0x40>; 29*b3e77da0SLad Prabhakar d-cache-size = <0x8000>; 30*b3e77da0SLad Prabhakar d-cache-line-size = <0x40>; 31*b3e77da0SLad Prabhakar clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 32*b3e77da0SLad Prabhakar 33*b3e77da0SLad Prabhakar cpu0_intc: interrupt-controller { 34*b3e77da0SLad Prabhakar #interrupt-cells = <1>; 35*b3e77da0SLad Prabhakar compatible = "riscv,cpu-intc"; 36*b3e77da0SLad Prabhakar interrupt-controller; 37*b3e77da0SLad Prabhakar }; 38*b3e77da0SLad Prabhakar }; 39*b3e77da0SLad Prabhakar }; 40*b3e77da0SLad Prabhakar}; 41*b3e77da0SLad Prabhakar 42*b3e77da0SLad Prabhakar&soc { 43*b3e77da0SLad Prabhakar interrupt-parent = <&plic>; 44*b3e77da0SLad Prabhakar 45*b3e77da0SLad Prabhakar plic: interrupt-controller@12c00000 { 46*b3e77da0SLad Prabhakar compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; 47*b3e77da0SLad Prabhakar #interrupt-cells = <2>; 48*b3e77da0SLad Prabhakar #address-cells = <0>; 49*b3e77da0SLad Prabhakar riscv,ndev = <511>; 50*b3e77da0SLad Prabhakar interrupt-controller; 51*b3e77da0SLad Prabhakar reg = <0x0 0x12c00000 0 0x400000>; 52*b3e77da0SLad Prabhakar clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; 53*b3e77da0SLad Prabhakar power-domains = <&cpg>; 54*b3e77da0SLad Prabhakar resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; 55*b3e77da0SLad Prabhakar interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; 56*b3e77da0SLad Prabhakar }; 57*b3e77da0SLad Prabhakar}; 58