1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Source for the PIC64GX SoCs 4 * 5 * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> 8 * 9 * PIC64GX is a series RISC-V multicore SoCs: 10 * https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64gx 11 */ 12 13/dts-v1/; 14#include "dt-bindings/clock/microchip,mpfs-clock.h" 15 16/ { 17 #address-cells = <2>; 18 #size-cells = <2>; 19 model = "Microchip PIC64GX SoC"; 20 compatible = "microchip,pic64gx"; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu0: cpu@0 { 27 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 28 device_type = "cpu"; 29 i-cache-block-size = <64>; 30 i-cache-sets = <128>; 31 i-cache-size = <16384>; 32 reg = <0>; 33 riscv,isa = "rv64imac"; 34 riscv,isa-base = "rv64i"; 35 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", 36 "zifencei", "zihpm"; 37 clocks = <&clkcfg CLK_CPU>; 38 status = "disabled"; 39 40 cpu0_intc: interrupt-controller { 41 #interrupt-cells = <1>; 42 compatible = "riscv,cpu-intc"; 43 interrupt-controller; 44 }; 45 }; 46 47 cpu1: cpu@1 { 48 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 49 d-cache-block-size = <64>; 50 d-cache-sets = <64>; 51 d-cache-size = <32768>; 52 d-tlb-sets = <1>; 53 d-tlb-size = <32>; 54 device_type = "cpu"; 55 i-cache-block-size = <64>; 56 i-cache-sets = <64>; 57 i-cache-size = <32768>; 58 i-tlb-sets = <1>; 59 i-tlb-size = <32>; 60 mmu-type = "riscv,sv39"; 61 reg = <1>; 62 riscv,isa = "rv64imafdc"; 63 riscv,isa-base = "rv64i"; 64 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", 65 "zicsr", "zifencei", "zihpm"; 66 clocks = <&clkcfg CLK_CPU>; 67 tlb-split; 68 next-level-cache = <&cctrllr>; 69 status = "okay"; 70 71 cpu1_intc: interrupt-controller { 72 #interrupt-cells = <1>; 73 compatible = "riscv,cpu-intc"; 74 interrupt-controller; 75 }; 76 }; 77 78 cpu2: cpu@2 { 79 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 80 d-cache-block-size = <64>; 81 d-cache-sets = <64>; 82 d-cache-size = <32768>; 83 d-tlb-sets = <1>; 84 d-tlb-size = <32>; 85 device_type = "cpu"; 86 i-cache-block-size = <64>; 87 i-cache-sets = <64>; 88 i-cache-size = <32768>; 89 i-tlb-sets = <1>; 90 i-tlb-size = <32>; 91 mmu-type = "riscv,sv39"; 92 reg = <2>; 93 riscv,isa = "rv64imafdc"; 94 riscv,isa-base = "rv64i"; 95 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", 96 "zicsr", "zifencei", "zihpm"; 97 clocks = <&clkcfg CLK_CPU>; 98 tlb-split; 99 next-level-cache = <&cctrllr>; 100 status = "okay"; 101 102 cpu2_intc: interrupt-controller { 103 #interrupt-cells = <1>; 104 compatible = "riscv,cpu-intc"; 105 interrupt-controller; 106 }; 107 }; 108 109 cpu3: cpu@3 { 110 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 111 d-cache-block-size = <64>; 112 d-cache-sets = <64>; 113 d-cache-size = <32768>; 114 d-tlb-sets = <1>; 115 d-tlb-size = <32>; 116 device_type = "cpu"; 117 i-cache-block-size = <64>; 118 i-cache-sets = <64>; 119 i-cache-size = <32768>; 120 i-tlb-sets = <1>; 121 i-tlb-size = <32>; 122 mmu-type = "riscv,sv39"; 123 reg = <3>; 124 riscv,isa = "rv64imafdc"; 125 riscv,isa-base = "rv64i"; 126 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", 127 "zicsr", "zifencei", "zihpm"; 128 clocks = <&clkcfg CLK_CPU>; 129 tlb-split; 130 next-level-cache = <&cctrllr>; 131 status = "okay"; 132 133 cpu3_intc: interrupt-controller { 134 #interrupt-cells = <1>; 135 compatible = "riscv,cpu-intc"; 136 interrupt-controller; 137 }; 138 }; 139 140 cpu4: cpu@4 { 141 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 142 d-cache-block-size = <64>; 143 d-cache-sets = <64>; 144 d-cache-size = <32768>; 145 d-tlb-sets = <1>; 146 d-tlb-size = <32>; 147 device_type = "cpu"; 148 i-cache-block-size = <64>; 149 i-cache-sets = <64>; 150 i-cache-size = <32768>; 151 i-tlb-sets = <1>; 152 i-tlb-size = <32>; 153 mmu-type = "riscv,sv39"; 154 reg = <4>; 155 riscv,isa = "rv64imafdc"; 156 riscv,isa-base = "rv64i"; 157 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", 158 "zicsr", "zifencei", "zihpm"; 159 clocks = <&clkcfg CLK_CPU>; 160 tlb-split; 161 next-level-cache = <&cctrllr>; 162 status = "okay"; 163 cpu4_intc: interrupt-controller { 164 #interrupt-cells = <1>; 165 compatible = "riscv,cpu-intc"; 166 interrupt-controller; 167 }; 168 }; 169 170 cpu-map { 171 cluster0 { 172 core0 { 173 cpu = <&cpu0>; 174 }; 175 176 core1 { 177 cpu = <&cpu1>; 178 }; 179 180 core2 { 181 cpu = <&cpu2>; 182 }; 183 184 core3 { 185 cpu = <&cpu3>; 186 }; 187 188 core4 { 189 cpu = <&cpu4>; 190 }; 191 }; 192 }; 193 }; 194 195 scbclk: clock-80000000 { 196 compatible = "fixed-clock"; 197 #clock-cells = <0>; 198 clock-frequency = <80000000>; 199 }; 200 201 refclk: mssrefclk { 202 compatible = "fixed-clock"; 203 #clock-cells = <0>; 204 }; 205 206 axiclk: axi-aclk0 { 207 compatible = "fixed-clock"; 208 #clock-cells = <0>; 209 clock-frequency = <125000000>; 210 }; 211 212 videoclk: video-aclk0 { 213 compatible = "fixed-clock"; 214 #clock-cells = <0>; 215 clock-frequency = <125000000>; 216 }; 217 218 syscontroller: syscontroller { 219 compatible = "microchip,pic64gx-sys-controller"; 220 mboxes = <&mbox 0>; 221 }; 222 223 soc { 224 #address-cells = <2>; 225 #size-cells = <2>; 226 compatible = "simple-bus"; 227 ranges; 228 229 clint: clint@2000000 { 230 compatible = "microchip,pic64gx-clint", "sifive,clint0"; 231 reg = <0x0 0x2000000 0x0 0xC000>; 232 interrupts-extended = <&cpu0_intc 0xffffffff>, <&cpu0_intc 0xffffffff>, 233 <&cpu1_intc 3>, <&cpu1_intc 7>, 234 <&cpu2_intc 3>, <&cpu2_intc 7>, 235 <&cpu3_intc 3>, <&cpu3_intc 7>, 236 <&cpu4_intc 3>, <&cpu4_intc 7>; 237 }; 238 239 cctrllr: cache-controller@2010000 { 240 compatible = "microchip,pic64gx-ccache", "microchip,mpfs-ccache", 241 "sifive,fu540-c000-ccache", "cache"; 242 reg = <0x0 0x2010000 0x0 0x1000>; 243 cache-block-size = <64>; 244 cache-level = <2>; 245 cache-sets = <1024>; 246 cache-size = <2097152>; 247 cache-unified; 248 interrupt-parent = <&plic>; 249 interrupts = <1>, <3>, <4>, <2>; 250 }; 251 252 pdma: dma-controller@3000000 { 253 compatible = "microchip,pic64gx-pdma", "microchip,mpfs-pdma", 254 "sifive,pdma0"; 255 reg = <0x0 0x3000000 0x0 0x8000>; 256 interrupt-parent = <&plic>; 257 interrupts = <5 6>, <7 8>, <9 10>, <11 12>; 258 #dma-cells = <1>; 259 }; 260 261 plic: interrupt-controller@c000000 { 262 compatible = "microchip,pic64gx-plic", "sifive,plic-1.0.0"; 263 reg = <0x0 0xc000000 0x0 0x4000000>; 264 #address-cells = <0>; 265 #interrupt-cells = <1>; 266 interrupt-controller; 267 interrupts-extended = <&cpu0_intc 0xffffffff>, 268 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, 269 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, 270 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, 271 <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; 272 riscv,ndev = <186>; 273 }; 274 275 mmuart0: serial@20000000 { 276 compatible = "ns16550a"; 277 reg = <0x0 0x20000000 0x0 0x400>; 278 reg-io-width = <4>; 279 reg-shift = <2>; 280 interrupt-parent = <&plic>; 281 interrupts = <90>; 282 current-speed = <115200>; 283 clocks = <&clkcfg CLK_MMUART0>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&uart0_mssio>; 286 status = "disabled"; /* Reserved for the HSS */ 287 }; 288 289 mss_top_sysreg: syscon@20002000 { 290 compatible = "microchip,pic64gx-mss-top-sysreg", 291 "microchip,mpfs-mss-top-sysreg", 292 "syscon", "simple-mfd"; 293 reg = <0x0 0x20002000 0x0 0x1000>; 294 #address-cells = <1>; 295 #size-cells = <1>; 296 #reset-cells = <1>; 297 298 iomux0: pinctrl@200 { 299 compatible = "microchip,pic64gx-pinctrl-iomux0", 300 "microchip,mpfs-pinctrl-iomux0"; 301 reg = <0x200 0x4>; 302 pinctrl-use-default; 303 }; 304 305 mssio: pinctrl@204 { 306 compatible = "microchip,pic64gx-pinctrl-mssio", 307 "microchip,mpfs-pinctrl-mssio"; 308 reg = <0x204 0x7c>; 309 /* on icicle ref design at least */ 310 pinctrl-use-default; 311 }; 312 }; 313 314 sysreg_scb: syscon@20003000 { 315 compatible = "microchip,pic64gx-sysreg-scb", 316 "microchip,mpfs-sysreg-scb", 317 "syscon"; 318 reg = <0x0 0x20003000 0x0 0x1000>; 319 }; 320 321 /* Common node entry for emmc/sd */ 322 mmc: mmc@20008000 { 323 compatible = "microchip,pic64gx-sd4hc", "cdns,sd4hc"; 324 reg = <0x0 0x20008000 0x0 0x1000>; 325 interrupt-parent = <&plic>; 326 interrupts = <88>; 327 clocks = <&clkcfg CLK_MMC>; 328 max-frequency = <200000000>; 329 status = "disabled"; 330 }; 331 332 mmuart1: serial@20100000 { 333 compatible = "ns16550a"; 334 reg = <0x0 0x20100000 0x0 0x400>; 335 reg-io-width = <4>; 336 reg-shift = <2>; 337 interrupt-parent = <&plic>; 338 interrupts = <91>; 339 current-speed = <115200>; 340 clocks = <&clkcfg CLK_MMUART1>; 341 status = "disabled"; 342 }; 343 344 mmuart2: serial@20102000 { 345 compatible = "ns16550a"; 346 reg = <0x0 0x20102000 0x0 0x400>; 347 reg-io-width = <4>; 348 reg-shift = <2>; 349 interrupt-parent = <&plic>; 350 interrupts = <92>; 351 current-speed = <115200>; 352 clocks = <&clkcfg CLK_MMUART2>; 353 status = "disabled"; 354 }; 355 356 mmuart3: serial@20104000 { 357 compatible = "ns16550a"; 358 reg = <0x0 0x20104000 0x0 0x400>; 359 reg-io-width = <4>; 360 reg-shift = <2>; 361 interrupt-parent = <&plic>; 362 interrupts = <93>; 363 current-speed = <115200>; 364 clocks = <&clkcfg CLK_MMUART3>; 365 status = "disabled"; 366 }; 367 368 mmuart4: serial@20106000 { 369 compatible = "ns16550a"; 370 reg = <0x0 0x20106000 0x0 0x400>; 371 reg-io-width = <4>; 372 reg-shift = <2>; 373 interrupt-parent = <&plic>; 374 interrupts = <94>; 375 clocks = <&clkcfg CLK_MMUART4>; 376 current-speed = <115200>; 377 status = "disabled"; 378 }; 379 380 spi0: spi@20108000 { 381 compatible = "microchip,pic64gx-spi", "microchip,mpfs-spi"; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 reg = <0x0 0x20108000 0x0 0x1000>; 385 interrupt-parent = <&plic>; 386 interrupts = <54>; 387 clocks = <&clkcfg CLK_SPI0>; 388 status = "disabled"; 389 }; 390 391 spi1: spi@20109000 { 392 compatible = "microchip,pic64gx-spi", "microchip,mpfs-spi"; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 reg = <0x0 0x20109000 0x0 0x1000>; 396 interrupt-parent = <&plic>; 397 interrupts = <55>; 398 clocks = <&clkcfg CLK_SPI1>; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&spi1_mssio>; 401 status = "disabled"; 402 }; 403 404 i2c0: i2c@2010a000 { 405 compatible = "microchip,pic64gx-i2c", "microchip,corei2c-rtl-v7"; 406 reg = <0x0 0x2010a000 0x0 0x1000>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 interrupt-parent = <&plic>; 410 interrupts = <58>; 411 clocks = <&clkcfg CLK_I2C0>; 412 clock-frequency = <100000>; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&i2c0_mssio>; 415 status = "disabled"; 416 }; 417 418 i2c1: i2c@2010b000 { 419 compatible = "microchip,pic64gx-i2c", "microchip,corei2c-rtl-v7"; 420 reg = <0x0 0x2010b000 0x0 0x1000>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 interrupt-parent = <&plic>; 424 interrupts = <61>; 425 clocks = <&clkcfg CLK_I2C1>; 426 clock-frequency = <100000>; 427 pinctrl-names = "default"; 428 pinctrl-0 = <&i2c1_mssio>; 429 status = "disabled"; 430 }; 431 432 can0: can@2010c000 { 433 compatible = "microchip,pic64gx-can", "microchip,mpfs-can"; 434 reg = <0x0 0x2010c000 0x0 0x1000>; 435 clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>; 436 interrupt-parent = <&plic>; 437 interrupts = <56>; 438 resets = <&mss_top_sysreg CLK_CAN0>; 439 status = "disabled"; 440 }; 441 442 can1: can@2010d000 { 443 compatible = "microchip,pic64gx-can", "microchip,mpfs-can"; 444 reg = <0x0 0x2010d000 0x0 0x1000>; 445 clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>; 446 interrupt-parent = <&plic>; 447 interrupts = <57>; 448 resets = <&mss_top_sysreg CLK_CAN1>; 449 status = "disabled"; 450 }; 451 452 mac0: ethernet@20110000 { 453 compatible = "microchip,pic64gx-macb", "microchip,mpfs-macb", 454 "cdns,macb"; 455 reg = <0x0 0x20110000 0x0 0x2000>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 interrupt-parent = <&plic>; 459 interrupts = <64>, <65>, <66>, <67>, <68>, <69>; 460 /* Filled in by a bootloader */ 461 local-mac-address = [00 00 00 00 00 00]; 462 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; 463 clock-names = "pclk", "hclk"; 464 resets = <&mss_top_sysreg CLK_MAC0>; 465 status = "disabled"; 466 }; 467 468 mac1: ethernet@20112000 { 469 compatible = "microchip,pic64gx-macb", "microchip,mpfs-macb", 470 "cdns,macb"; 471 reg = <0x0 0x20112000 0x0 0x2000>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 interrupt-parent = <&plic>; 475 interrupts = <70>, <71>, <72>, <73>, <74>, <75>; 476 /* Filled in by a bootloader */ 477 local-mac-address = [00 00 00 00 00 00]; 478 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; 479 clock-names = "pclk", "hclk"; 480 resets = <&mss_top_sysreg CLK_MAC1>; 481 status = "disabled"; 482 }; 483 484 gpio0: gpio@20120000 { 485 compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; 486 reg = <0x0 0x20120000 0x0 0x1000>; 487 interrupt-parent = <&plic>; 488 interrupt-controller; 489 #interrupt-cells = <1>; 490 clocks = <&clkcfg CLK_GPIO0>; 491 gpio-controller; 492 #gpio-cells = <2>; 493 ngpios = <14>; 494 status = "disabled"; 495 }; 496 497 gpio1: gpio@20121000 { 498 compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; 499 reg = <0x0 0x20121000 0x0 0x1000>; 500 interrupt-parent = <&plic>; 501 interrupt-controller; 502 #interrupt-cells = <1>; 503 clocks = <&clkcfg CLK_GPIO1>; 504 gpio-controller; 505 #gpio-cells = <2>; 506 ngpios = <24>; 507 status = "disabled"; 508 }; 509 510 gpio2: gpio@20122000 { 511 compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; 512 reg = <0x0 0x20122000 0x0 0x1000>; 513 interrupt-parent = <&plic>; 514 interrupt-controller; 515 #interrupt-cells = <1>; 516 clocks = <&clkcfg CLK_GPIO2>; 517 gpio-controller; 518 #gpio-cells = <2>; 519 ngpios = <32>; 520 status = "disabled"; 521 }; 522 523 rtc: rtc@20124000 { 524 compatible = "microchip,pic64gx-rtc", "microchip,mpfs-rtc"; 525 reg = <0x0 0x20124000 0x0 0x1000>; 526 interrupt-parent = <&plic>; 527 interrupts = <80>, <81>; 528 clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; 529 clock-names = "rtc", "rtcref"; 530 status = "disabled"; 531 }; 532 533 usb: usb@20201000 { 534 compatible = "microchip,pic64gx-musb", "microchip,mpfs-musb"; 535 reg = <0x0 0x20201000 0x0 0x1000>; 536 interrupt-parent = <&plic>; 537 interrupts = <86>, <87>; 538 clocks = <&clkcfg CLK_USB>; 539 interrupt-names = "dma", "mc"; 540 status = "disabled"; 541 }; 542 543 qspi: spi@21000000 { 544 compatible = "microchip,pic64gx-qspi", "microchip,coreqspi-rtl-v2"; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 reg = <0x0 0x21000000 0x0 0x1000>; 548 interrupt-parent = <&plic>; 549 interrupts = <85>; 550 clocks = <&clkcfg CLK_QSPI>; 551 status = "disabled"; 552 }; 553 554 control_scb: syscon@37020000 { 555 compatible = "microchip,pic64gx-control-scb", 556 "microchip,mpfs-control-scb", 557 "syscon"; 558 reg = <0x0 0x37020000 0x0 0x100>; 559 }; 560 561 syscontroller_qspi: spi@37020100 { 562 compatible = "microchip,pic64gx-qspi", "microchip,coreqspi-rtl-v2"; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 reg = <0x0 0x37020100 0x0 0x100>; 566 interrupt-parent = <&plic>; 567 interrupts = <110>; 568 clocks = <&scbclk>; 569 status = "disabled"; 570 }; 571 572 mbox: mailbox@37020800 { 573 compatible = "microchip,pic64gx-mailbox", "microchip,mpfs-mailbox"; 574 reg = <0x0 0x37020800 0x0 0x100>; 575 interrupt-parent = <&plic>; 576 interrupts = <96>; 577 #mbox-cells = <1>; 578 status = "disabled"; 579 }; 580 581 ccc_se: clock-controller@38010000 { 582 compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; 583 reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, 584 <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>; 585 #clock-cells = <1>; 586 status = "disabled"; 587 }; 588 589 ccc_ne: clock-controller@38040000 { 590 compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; 591 reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>, 592 <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>; 593 #clock-cells = <1>; 594 status = "disabled"; 595 }; 596 597 ccc_nw: clock-controller@38100000 { 598 compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; 599 reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>, 600 <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>; 601 #clock-cells = <1>; 602 status = "disabled"; 603 }; 604 605 ccc_sw: clock-controller@38400000 { 606 compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; 607 reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>, 608 <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>; 609 #clock-cells = <1>; 610 status = "disabled"; 611 }; 612 613 clkcfg: clkcfg@3e001000 { 614 compatible = "microchip,pic64gx-clkcfg", "microchip,mpfs-clkcfg"; 615 reg = <0x0 0x3e001000 0x0 0x1000>; 616 clocks = <&refclk>; 617 #clock-cells = <1>; 618 }; 619 620 gpio2_pinctrl: pinctrl@41000000 { 621 compatible = "microchip,pic64gx-pinctrl-gpio2"; 622 reg = <0x0 0x41000000 0x0 0x4>; 623 pinctrl-use-default; 624 pinctrl-names = "default"; 625 pinctrl-0 = <&mdio0_fio>, <&mdio1_fio>, <&spi0_fio>, <&qspi_fio>, 626 <&uart3_fio>, <&uart4_fio>, <&can1_fio>, <&can0_fio>, 627 <&uart2_fio>; 628 }; 629 }; 630}; 631