1*7219d20fSPierre-Henry Moussay// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*7219d20fSPierre-Henry Moussay/* 3*7219d20fSPierre-Henry Moussay * Device Tree Source for the PIC64GX SoCs 4*7219d20fSPierre-Henry Moussay * 5*7219d20fSPierre-Henry Moussay * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries 6*7219d20fSPierre-Henry Moussay * 7*7219d20fSPierre-Henry Moussay * Author: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> 8*7219d20fSPierre-Henry Moussay * 9*7219d20fSPierre-Henry Moussay * PIC64GX is a series RISC-V multicore SoCs: 10*7219d20fSPierre-Henry Moussay * https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64gx 11*7219d20fSPierre-Henry Moussay */ 12*7219d20fSPierre-Henry Moussay 13*7219d20fSPierre-Henry Moussay/dts-v1/; 14*7219d20fSPierre-Henry Moussay#include "dt-bindings/clock/microchip,mpfs-clock.h" 15*7219d20fSPierre-Henry Moussay 16*7219d20fSPierre-Henry Moussay/ { 17*7219d20fSPierre-Henry Moussay #address-cells = <2>; 18*7219d20fSPierre-Henry Moussay #size-cells = <2>; 19*7219d20fSPierre-Henry Moussay model = "Microchip PIC64GX SoC"; 20*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx"; 21*7219d20fSPierre-Henry Moussay 22*7219d20fSPierre-Henry Moussay cpus { 23*7219d20fSPierre-Henry Moussay #address-cells = <1>; 24*7219d20fSPierre-Henry Moussay #size-cells = <0>; 25*7219d20fSPierre-Henry Moussay 26*7219d20fSPierre-Henry Moussay cpu0: cpu@0 { 27*7219d20fSPierre-Henry Moussay compatible = "sifive,e51", "sifive,rocket0", "riscv"; 28*7219d20fSPierre-Henry Moussay device_type = "cpu"; 29*7219d20fSPierre-Henry Moussay i-cache-block-size = <64>; 30*7219d20fSPierre-Henry Moussay i-cache-sets = <128>; 31*7219d20fSPierre-Henry Moussay i-cache-size = <16384>; 32*7219d20fSPierre-Henry Moussay reg = <0>; 33*7219d20fSPierre-Henry Moussay riscv,isa = "rv64imac"; 34*7219d20fSPierre-Henry Moussay riscv,isa-base = "rv64i"; 35*7219d20fSPierre-Henry Moussay riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", 36*7219d20fSPierre-Henry Moussay "zifencei", "zihpm"; 37*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_CPU>; 38*7219d20fSPierre-Henry Moussay status = "disabled"; 39*7219d20fSPierre-Henry Moussay 40*7219d20fSPierre-Henry Moussay cpu0_intc: interrupt-controller { 41*7219d20fSPierre-Henry Moussay #interrupt-cells = <1>; 42*7219d20fSPierre-Henry Moussay compatible = "riscv,cpu-intc"; 43*7219d20fSPierre-Henry Moussay interrupt-controller; 44*7219d20fSPierre-Henry Moussay }; 45*7219d20fSPierre-Henry Moussay }; 46*7219d20fSPierre-Henry Moussay 47*7219d20fSPierre-Henry Moussay cpu1: cpu@1 { 48*7219d20fSPierre-Henry Moussay compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 49*7219d20fSPierre-Henry Moussay d-cache-block-size = <64>; 50*7219d20fSPierre-Henry Moussay d-cache-sets = <64>; 51*7219d20fSPierre-Henry Moussay d-cache-size = <32768>; 52*7219d20fSPierre-Henry Moussay d-tlb-sets = <1>; 53*7219d20fSPierre-Henry Moussay d-tlb-size = <32>; 54*7219d20fSPierre-Henry Moussay device_type = "cpu"; 55*7219d20fSPierre-Henry Moussay i-cache-block-size = <64>; 56*7219d20fSPierre-Henry Moussay i-cache-sets = <64>; 57*7219d20fSPierre-Henry Moussay i-cache-size = <32768>; 58*7219d20fSPierre-Henry Moussay i-tlb-sets = <1>; 59*7219d20fSPierre-Henry Moussay i-tlb-size = <32>; 60*7219d20fSPierre-Henry Moussay mmu-type = "riscv,sv39"; 61*7219d20fSPierre-Henry Moussay reg = <1>; 62*7219d20fSPierre-Henry Moussay riscv,isa = "rv64imafdc"; 63*7219d20fSPierre-Henry Moussay riscv,isa-base = "rv64i"; 64*7219d20fSPierre-Henry Moussay riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", 65*7219d20fSPierre-Henry Moussay "zicsr", "zifencei", "zihpm"; 66*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_CPU>; 67*7219d20fSPierre-Henry Moussay tlb-split; 68*7219d20fSPierre-Henry Moussay next-level-cache = <&cctrllr>; 69*7219d20fSPierre-Henry Moussay status = "okay"; 70*7219d20fSPierre-Henry Moussay 71*7219d20fSPierre-Henry Moussay cpu1_intc: interrupt-controller { 72*7219d20fSPierre-Henry Moussay #interrupt-cells = <1>; 73*7219d20fSPierre-Henry Moussay compatible = "riscv,cpu-intc"; 74*7219d20fSPierre-Henry Moussay interrupt-controller; 75*7219d20fSPierre-Henry Moussay }; 76*7219d20fSPierre-Henry Moussay }; 77*7219d20fSPierre-Henry Moussay 78*7219d20fSPierre-Henry Moussay cpu2: cpu@2 { 79*7219d20fSPierre-Henry Moussay compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 80*7219d20fSPierre-Henry Moussay d-cache-block-size = <64>; 81*7219d20fSPierre-Henry Moussay d-cache-sets = <64>; 82*7219d20fSPierre-Henry Moussay d-cache-size = <32768>; 83*7219d20fSPierre-Henry Moussay d-tlb-sets = <1>; 84*7219d20fSPierre-Henry Moussay d-tlb-size = <32>; 85*7219d20fSPierre-Henry Moussay device_type = "cpu"; 86*7219d20fSPierre-Henry Moussay i-cache-block-size = <64>; 87*7219d20fSPierre-Henry Moussay i-cache-sets = <64>; 88*7219d20fSPierre-Henry Moussay i-cache-size = <32768>; 89*7219d20fSPierre-Henry Moussay i-tlb-sets = <1>; 90*7219d20fSPierre-Henry Moussay i-tlb-size = <32>; 91*7219d20fSPierre-Henry Moussay mmu-type = "riscv,sv39"; 92*7219d20fSPierre-Henry Moussay reg = <2>; 93*7219d20fSPierre-Henry Moussay riscv,isa = "rv64imafdc"; 94*7219d20fSPierre-Henry Moussay riscv,isa-base = "rv64i"; 95*7219d20fSPierre-Henry Moussay riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", 96*7219d20fSPierre-Henry Moussay "zicsr", "zifencei", "zihpm"; 97*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_CPU>; 98*7219d20fSPierre-Henry Moussay tlb-split; 99*7219d20fSPierre-Henry Moussay next-level-cache = <&cctrllr>; 100*7219d20fSPierre-Henry Moussay status = "okay"; 101*7219d20fSPierre-Henry Moussay 102*7219d20fSPierre-Henry Moussay cpu2_intc: interrupt-controller { 103*7219d20fSPierre-Henry Moussay #interrupt-cells = <1>; 104*7219d20fSPierre-Henry Moussay compatible = "riscv,cpu-intc"; 105*7219d20fSPierre-Henry Moussay interrupt-controller; 106*7219d20fSPierre-Henry Moussay }; 107*7219d20fSPierre-Henry Moussay }; 108*7219d20fSPierre-Henry Moussay 109*7219d20fSPierre-Henry Moussay cpu3: cpu@3 { 110*7219d20fSPierre-Henry Moussay compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 111*7219d20fSPierre-Henry Moussay d-cache-block-size = <64>; 112*7219d20fSPierre-Henry Moussay d-cache-sets = <64>; 113*7219d20fSPierre-Henry Moussay d-cache-size = <32768>; 114*7219d20fSPierre-Henry Moussay d-tlb-sets = <1>; 115*7219d20fSPierre-Henry Moussay d-tlb-size = <32>; 116*7219d20fSPierre-Henry Moussay device_type = "cpu"; 117*7219d20fSPierre-Henry Moussay i-cache-block-size = <64>; 118*7219d20fSPierre-Henry Moussay i-cache-sets = <64>; 119*7219d20fSPierre-Henry Moussay i-cache-size = <32768>; 120*7219d20fSPierre-Henry Moussay i-tlb-sets = <1>; 121*7219d20fSPierre-Henry Moussay i-tlb-size = <32>; 122*7219d20fSPierre-Henry Moussay mmu-type = "riscv,sv39"; 123*7219d20fSPierre-Henry Moussay reg = <3>; 124*7219d20fSPierre-Henry Moussay riscv,isa = "rv64imafdc"; 125*7219d20fSPierre-Henry Moussay riscv,isa-base = "rv64i"; 126*7219d20fSPierre-Henry Moussay riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", 127*7219d20fSPierre-Henry Moussay "zicsr", "zifencei", "zihpm"; 128*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_CPU>; 129*7219d20fSPierre-Henry Moussay tlb-split; 130*7219d20fSPierre-Henry Moussay next-level-cache = <&cctrllr>; 131*7219d20fSPierre-Henry Moussay status = "okay"; 132*7219d20fSPierre-Henry Moussay 133*7219d20fSPierre-Henry Moussay cpu3_intc: interrupt-controller { 134*7219d20fSPierre-Henry Moussay #interrupt-cells = <1>; 135*7219d20fSPierre-Henry Moussay compatible = "riscv,cpu-intc"; 136*7219d20fSPierre-Henry Moussay interrupt-controller; 137*7219d20fSPierre-Henry Moussay }; 138*7219d20fSPierre-Henry Moussay }; 139*7219d20fSPierre-Henry Moussay 140*7219d20fSPierre-Henry Moussay cpu4: cpu@4 { 141*7219d20fSPierre-Henry Moussay compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 142*7219d20fSPierre-Henry Moussay d-cache-block-size = <64>; 143*7219d20fSPierre-Henry Moussay d-cache-sets = <64>; 144*7219d20fSPierre-Henry Moussay d-cache-size = <32768>; 145*7219d20fSPierre-Henry Moussay d-tlb-sets = <1>; 146*7219d20fSPierre-Henry Moussay d-tlb-size = <32>; 147*7219d20fSPierre-Henry Moussay device_type = "cpu"; 148*7219d20fSPierre-Henry Moussay i-cache-block-size = <64>; 149*7219d20fSPierre-Henry Moussay i-cache-sets = <64>; 150*7219d20fSPierre-Henry Moussay i-cache-size = <32768>; 151*7219d20fSPierre-Henry Moussay i-tlb-sets = <1>; 152*7219d20fSPierre-Henry Moussay i-tlb-size = <32>; 153*7219d20fSPierre-Henry Moussay mmu-type = "riscv,sv39"; 154*7219d20fSPierre-Henry Moussay reg = <4>; 155*7219d20fSPierre-Henry Moussay riscv,isa = "rv64imafdc"; 156*7219d20fSPierre-Henry Moussay riscv,isa-base = "rv64i"; 157*7219d20fSPierre-Henry Moussay riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", 158*7219d20fSPierre-Henry Moussay "zicsr", "zifencei", "zihpm"; 159*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_CPU>; 160*7219d20fSPierre-Henry Moussay tlb-split; 161*7219d20fSPierre-Henry Moussay next-level-cache = <&cctrllr>; 162*7219d20fSPierre-Henry Moussay status = "okay"; 163*7219d20fSPierre-Henry Moussay cpu4_intc: interrupt-controller { 164*7219d20fSPierre-Henry Moussay #interrupt-cells = <1>; 165*7219d20fSPierre-Henry Moussay compatible = "riscv,cpu-intc"; 166*7219d20fSPierre-Henry Moussay interrupt-controller; 167*7219d20fSPierre-Henry Moussay }; 168*7219d20fSPierre-Henry Moussay }; 169*7219d20fSPierre-Henry Moussay 170*7219d20fSPierre-Henry Moussay cpu-map { 171*7219d20fSPierre-Henry Moussay cluster0 { 172*7219d20fSPierre-Henry Moussay core0 { 173*7219d20fSPierre-Henry Moussay cpu = <&cpu0>; 174*7219d20fSPierre-Henry Moussay }; 175*7219d20fSPierre-Henry Moussay 176*7219d20fSPierre-Henry Moussay core1 { 177*7219d20fSPierre-Henry Moussay cpu = <&cpu1>; 178*7219d20fSPierre-Henry Moussay }; 179*7219d20fSPierre-Henry Moussay 180*7219d20fSPierre-Henry Moussay core2 { 181*7219d20fSPierre-Henry Moussay cpu = <&cpu2>; 182*7219d20fSPierre-Henry Moussay }; 183*7219d20fSPierre-Henry Moussay 184*7219d20fSPierre-Henry Moussay core3 { 185*7219d20fSPierre-Henry Moussay cpu = <&cpu3>; 186*7219d20fSPierre-Henry Moussay }; 187*7219d20fSPierre-Henry Moussay 188*7219d20fSPierre-Henry Moussay core4 { 189*7219d20fSPierre-Henry Moussay cpu = <&cpu4>; 190*7219d20fSPierre-Henry Moussay }; 191*7219d20fSPierre-Henry Moussay }; 192*7219d20fSPierre-Henry Moussay }; 193*7219d20fSPierre-Henry Moussay }; 194*7219d20fSPierre-Henry Moussay 195*7219d20fSPierre-Henry Moussay scbclk: clock-80000000 { 196*7219d20fSPierre-Henry Moussay compatible = "fixed-clock"; 197*7219d20fSPierre-Henry Moussay #clock-cells = <0>; 198*7219d20fSPierre-Henry Moussay clock-frequency = <80000000>; 199*7219d20fSPierre-Henry Moussay }; 200*7219d20fSPierre-Henry Moussay 201*7219d20fSPierre-Henry Moussay refclk: mssrefclk { 202*7219d20fSPierre-Henry Moussay compatible = "fixed-clock"; 203*7219d20fSPierre-Henry Moussay #clock-cells = <0>; 204*7219d20fSPierre-Henry Moussay }; 205*7219d20fSPierre-Henry Moussay 206*7219d20fSPierre-Henry Moussay axiclk: axi-aclk0 { 207*7219d20fSPierre-Henry Moussay compatible = "fixed-clock"; 208*7219d20fSPierre-Henry Moussay #clock-cells = <0>; 209*7219d20fSPierre-Henry Moussay clock-frequency = <125000000>; 210*7219d20fSPierre-Henry Moussay }; 211*7219d20fSPierre-Henry Moussay 212*7219d20fSPierre-Henry Moussay videoclk: video-aclk0 { 213*7219d20fSPierre-Henry Moussay compatible = "fixed-clock"; 214*7219d20fSPierre-Henry Moussay #clock-cells = <0>; 215*7219d20fSPierre-Henry Moussay clock-frequency = <125000000>; 216*7219d20fSPierre-Henry Moussay }; 217*7219d20fSPierre-Henry Moussay 218*7219d20fSPierre-Henry Moussay syscontroller: syscontroller { 219*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-sys-controller"; 220*7219d20fSPierre-Henry Moussay mboxes = <&mbox 0>; 221*7219d20fSPierre-Henry Moussay }; 222*7219d20fSPierre-Henry Moussay 223*7219d20fSPierre-Henry Moussay soc { 224*7219d20fSPierre-Henry Moussay #address-cells = <2>; 225*7219d20fSPierre-Henry Moussay #size-cells = <2>; 226*7219d20fSPierre-Henry Moussay compatible = "simple-bus"; 227*7219d20fSPierre-Henry Moussay ranges; 228*7219d20fSPierre-Henry Moussay 229*7219d20fSPierre-Henry Moussay clint: clint@2000000 { 230*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-clint", "sifive,clint0"; 231*7219d20fSPierre-Henry Moussay reg = <0x0 0x2000000 0x0 0xC000>; 232*7219d20fSPierre-Henry Moussay interrupts-extended = <&cpu0_intc 0xffffffff>, <&cpu0_intc 0xffffffff>, 233*7219d20fSPierre-Henry Moussay <&cpu1_intc 3>, <&cpu1_intc 7>, 234*7219d20fSPierre-Henry Moussay <&cpu2_intc 3>, <&cpu2_intc 7>, 235*7219d20fSPierre-Henry Moussay <&cpu3_intc 3>, <&cpu3_intc 7>, 236*7219d20fSPierre-Henry Moussay <&cpu4_intc 3>, <&cpu4_intc 7>; 237*7219d20fSPierre-Henry Moussay }; 238*7219d20fSPierre-Henry Moussay 239*7219d20fSPierre-Henry Moussay cctrllr: cache-controller@2010000 { 240*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-ccache", "microchip,mpfs-ccache", 241*7219d20fSPierre-Henry Moussay "sifive,fu540-c000-ccache", "cache"; 242*7219d20fSPierre-Henry Moussay reg = <0x0 0x2010000 0x0 0x1000>; 243*7219d20fSPierre-Henry Moussay cache-block-size = <64>; 244*7219d20fSPierre-Henry Moussay cache-level = <2>; 245*7219d20fSPierre-Henry Moussay cache-sets = <1024>; 246*7219d20fSPierre-Henry Moussay cache-size = <2097152>; 247*7219d20fSPierre-Henry Moussay cache-unified; 248*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 249*7219d20fSPierre-Henry Moussay interrupts = <1>, <3>, <4>, <2>; 250*7219d20fSPierre-Henry Moussay }; 251*7219d20fSPierre-Henry Moussay 252*7219d20fSPierre-Henry Moussay pdma: dma-controller@3000000 { 253*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-pdma", "microchip,mpfs-pdma", 254*7219d20fSPierre-Henry Moussay "sifive,pdma0"; 255*7219d20fSPierre-Henry Moussay reg = <0x0 0x3000000 0x0 0x8000>; 256*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 257*7219d20fSPierre-Henry Moussay interrupts = <5 6>, <7 8>, <9 10>, <11 12>; 258*7219d20fSPierre-Henry Moussay #dma-cells = <1>; 259*7219d20fSPierre-Henry Moussay }; 260*7219d20fSPierre-Henry Moussay 261*7219d20fSPierre-Henry Moussay plic: interrupt-controller@c000000 { 262*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-plic", "sifive,plic-1.0.0"; 263*7219d20fSPierre-Henry Moussay reg = <0x0 0xc000000 0x0 0x4000000>; 264*7219d20fSPierre-Henry Moussay #address-cells = <0>; 265*7219d20fSPierre-Henry Moussay #interrupt-cells = <1>; 266*7219d20fSPierre-Henry Moussay interrupt-controller; 267*7219d20fSPierre-Henry Moussay interrupts-extended = <&cpu0_intc 0xffffffff>, 268*7219d20fSPierre-Henry Moussay <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, 269*7219d20fSPierre-Henry Moussay <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, 270*7219d20fSPierre-Henry Moussay <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, 271*7219d20fSPierre-Henry Moussay <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; 272*7219d20fSPierre-Henry Moussay riscv,ndev = <186>; 273*7219d20fSPierre-Henry Moussay }; 274*7219d20fSPierre-Henry Moussay 275*7219d20fSPierre-Henry Moussay mmuart0: serial@20000000 { 276*7219d20fSPierre-Henry Moussay compatible = "ns16550a"; 277*7219d20fSPierre-Henry Moussay reg = <0x0 0x20000000 0x0 0x400>; 278*7219d20fSPierre-Henry Moussay reg-io-width = <4>; 279*7219d20fSPierre-Henry Moussay reg-shift = <2>; 280*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 281*7219d20fSPierre-Henry Moussay interrupts = <90>; 282*7219d20fSPierre-Henry Moussay current-speed = <115200>; 283*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_MMUART0>; 284*7219d20fSPierre-Henry Moussay pinctrl-names = "default"; 285*7219d20fSPierre-Henry Moussay pinctrl-0 = <&uart0_mssio>; 286*7219d20fSPierre-Henry Moussay status = "disabled"; /* Reserved for the HSS */ 287*7219d20fSPierre-Henry Moussay }; 288*7219d20fSPierre-Henry Moussay 289*7219d20fSPierre-Henry Moussay mss_top_sysreg: syscon@20002000 { 290*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-mss-top-sysreg", 291*7219d20fSPierre-Henry Moussay "microchip,mpfs-mss-top-sysreg", 292*7219d20fSPierre-Henry Moussay "syscon", "simple-mfd"; 293*7219d20fSPierre-Henry Moussay reg = <0x0 0x20002000 0x0 0x1000>; 294*7219d20fSPierre-Henry Moussay #address-cells = <1>; 295*7219d20fSPierre-Henry Moussay #size-cells = <1>; 296*7219d20fSPierre-Henry Moussay #reset-cells = <1>; 297*7219d20fSPierre-Henry Moussay 298*7219d20fSPierre-Henry Moussay iomux0: pinctrl@200 { 299*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-pinctrl-iomux0", 300*7219d20fSPierre-Henry Moussay "microchip,mpfs-pinctrl-iomux0"; 301*7219d20fSPierre-Henry Moussay reg = <0x200 0x4>; 302*7219d20fSPierre-Henry Moussay pinctrl-use-default; 303*7219d20fSPierre-Henry Moussay }; 304*7219d20fSPierre-Henry Moussay 305*7219d20fSPierre-Henry Moussay mssio: pinctrl@204 { 306*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-pinctrl-mssio", 307*7219d20fSPierre-Henry Moussay "microchip,mpfs-pinctrl-mssio"; 308*7219d20fSPierre-Henry Moussay reg = <0x204 0x7c>; 309*7219d20fSPierre-Henry Moussay /* on icicle ref design at least */ 310*7219d20fSPierre-Henry Moussay pinctrl-use-default; 311*7219d20fSPierre-Henry Moussay }; 312*7219d20fSPierre-Henry Moussay }; 313*7219d20fSPierre-Henry Moussay 314*7219d20fSPierre-Henry Moussay sysreg_scb: syscon@20003000 { 315*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-sysreg-scb", 316*7219d20fSPierre-Henry Moussay "microchip,mpfs-sysreg-scb", 317*7219d20fSPierre-Henry Moussay "syscon"; 318*7219d20fSPierre-Henry Moussay reg = <0x0 0x20003000 0x0 0x1000>; 319*7219d20fSPierre-Henry Moussay }; 320*7219d20fSPierre-Henry Moussay 321*7219d20fSPierre-Henry Moussay /* Common node entry for emmc/sd */ 322*7219d20fSPierre-Henry Moussay mmc: mmc@20008000 { 323*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-sd4hc", "cdns,sd4hc"; 324*7219d20fSPierre-Henry Moussay reg = <0x0 0x20008000 0x0 0x1000>; 325*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 326*7219d20fSPierre-Henry Moussay interrupts = <88>; 327*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_MMC>; 328*7219d20fSPierre-Henry Moussay max-frequency = <200000000>; 329*7219d20fSPierre-Henry Moussay status = "disabled"; 330*7219d20fSPierre-Henry Moussay }; 331*7219d20fSPierre-Henry Moussay 332*7219d20fSPierre-Henry Moussay mmuart1: serial@20100000 { 333*7219d20fSPierre-Henry Moussay compatible = "ns16550a"; 334*7219d20fSPierre-Henry Moussay reg = <0x0 0x20100000 0x0 0x400>; 335*7219d20fSPierre-Henry Moussay reg-io-width = <4>; 336*7219d20fSPierre-Henry Moussay reg-shift = <2>; 337*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 338*7219d20fSPierre-Henry Moussay interrupts = <91>; 339*7219d20fSPierre-Henry Moussay current-speed = <115200>; 340*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_MMUART1>; 341*7219d20fSPierre-Henry Moussay status = "disabled"; 342*7219d20fSPierre-Henry Moussay }; 343*7219d20fSPierre-Henry Moussay 344*7219d20fSPierre-Henry Moussay mmuart2: serial@20102000 { 345*7219d20fSPierre-Henry Moussay compatible = "ns16550a"; 346*7219d20fSPierre-Henry Moussay reg = <0x0 0x20102000 0x0 0x400>; 347*7219d20fSPierre-Henry Moussay reg-io-width = <4>; 348*7219d20fSPierre-Henry Moussay reg-shift = <2>; 349*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 350*7219d20fSPierre-Henry Moussay interrupts = <92>; 351*7219d20fSPierre-Henry Moussay current-speed = <115200>; 352*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_MMUART2>; 353*7219d20fSPierre-Henry Moussay status = "disabled"; 354*7219d20fSPierre-Henry Moussay }; 355*7219d20fSPierre-Henry Moussay 356*7219d20fSPierre-Henry Moussay mmuart3: serial@20104000 { 357*7219d20fSPierre-Henry Moussay compatible = "ns16550a"; 358*7219d20fSPierre-Henry Moussay reg = <0x0 0x20104000 0x0 0x400>; 359*7219d20fSPierre-Henry Moussay reg-io-width = <4>; 360*7219d20fSPierre-Henry Moussay reg-shift = <2>; 361*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 362*7219d20fSPierre-Henry Moussay interrupts = <93>; 363*7219d20fSPierre-Henry Moussay current-speed = <115200>; 364*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_MMUART3>; 365*7219d20fSPierre-Henry Moussay status = "disabled"; 366*7219d20fSPierre-Henry Moussay }; 367*7219d20fSPierre-Henry Moussay 368*7219d20fSPierre-Henry Moussay mmuart4: serial@20106000 { 369*7219d20fSPierre-Henry Moussay compatible = "ns16550a"; 370*7219d20fSPierre-Henry Moussay reg = <0x0 0x20106000 0x0 0x400>; 371*7219d20fSPierre-Henry Moussay reg-io-width = <4>; 372*7219d20fSPierre-Henry Moussay reg-shift = <2>; 373*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 374*7219d20fSPierre-Henry Moussay interrupts = <94>; 375*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_MMUART4>; 376*7219d20fSPierre-Henry Moussay current-speed = <115200>; 377*7219d20fSPierre-Henry Moussay status = "disabled"; 378*7219d20fSPierre-Henry Moussay }; 379*7219d20fSPierre-Henry Moussay 380*7219d20fSPierre-Henry Moussay spi0: spi@20108000 { 381*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-spi", "microchip,mpfs-spi"; 382*7219d20fSPierre-Henry Moussay #address-cells = <1>; 383*7219d20fSPierre-Henry Moussay #size-cells = <0>; 384*7219d20fSPierre-Henry Moussay reg = <0x0 0x20108000 0x0 0x1000>; 385*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 386*7219d20fSPierre-Henry Moussay interrupts = <54>; 387*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_SPI0>; 388*7219d20fSPierre-Henry Moussay status = "disabled"; 389*7219d20fSPierre-Henry Moussay }; 390*7219d20fSPierre-Henry Moussay 391*7219d20fSPierre-Henry Moussay spi1: spi@20109000 { 392*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-spi", "microchip,mpfs-spi"; 393*7219d20fSPierre-Henry Moussay #address-cells = <1>; 394*7219d20fSPierre-Henry Moussay #size-cells = <0>; 395*7219d20fSPierre-Henry Moussay reg = <0x0 0x20109000 0x0 0x1000>; 396*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 397*7219d20fSPierre-Henry Moussay interrupts = <55>; 398*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_SPI1>; 399*7219d20fSPierre-Henry Moussay pinctrl-names = "default"; 400*7219d20fSPierre-Henry Moussay pinctrl-0 = <&spi1_mssio>; 401*7219d20fSPierre-Henry Moussay status = "disabled"; 402*7219d20fSPierre-Henry Moussay }; 403*7219d20fSPierre-Henry Moussay 404*7219d20fSPierre-Henry Moussay i2c0: i2c@2010a000 { 405*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-i2c", "microchip,corei2c-rtl-v7"; 406*7219d20fSPierre-Henry Moussay reg = <0x0 0x2010a000 0x0 0x1000>; 407*7219d20fSPierre-Henry Moussay #address-cells = <1>; 408*7219d20fSPierre-Henry Moussay #size-cells = <0>; 409*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 410*7219d20fSPierre-Henry Moussay interrupts = <58>; 411*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_I2C0>; 412*7219d20fSPierre-Henry Moussay clock-frequency = <100000>; 413*7219d20fSPierre-Henry Moussay pinctrl-names = "default"; 414*7219d20fSPierre-Henry Moussay pinctrl-0 = <&i2c0_mssio>; 415*7219d20fSPierre-Henry Moussay status = "disabled"; 416*7219d20fSPierre-Henry Moussay }; 417*7219d20fSPierre-Henry Moussay 418*7219d20fSPierre-Henry Moussay i2c1: i2c@2010b000 { 419*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-i2c", "microchip,corei2c-rtl-v7"; 420*7219d20fSPierre-Henry Moussay reg = <0x0 0x2010b000 0x0 0x1000>; 421*7219d20fSPierre-Henry Moussay #address-cells = <1>; 422*7219d20fSPierre-Henry Moussay #size-cells = <0>; 423*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 424*7219d20fSPierre-Henry Moussay interrupts = <61>; 425*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_I2C1>; 426*7219d20fSPierre-Henry Moussay clock-frequency = <100000>; 427*7219d20fSPierre-Henry Moussay pinctrl-names = "default"; 428*7219d20fSPierre-Henry Moussay pinctrl-0 = <&i2c1_mssio>; 429*7219d20fSPierre-Henry Moussay status = "disabled"; 430*7219d20fSPierre-Henry Moussay }; 431*7219d20fSPierre-Henry Moussay 432*7219d20fSPierre-Henry Moussay can0: can@2010c000 { 433*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-can", "microchip,mpfs-can"; 434*7219d20fSPierre-Henry Moussay reg = <0x0 0x2010c000 0x0 0x1000>; 435*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>; 436*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 437*7219d20fSPierre-Henry Moussay interrupts = <56>; 438*7219d20fSPierre-Henry Moussay resets = <&mss_top_sysreg CLK_CAN0>; 439*7219d20fSPierre-Henry Moussay status = "disabled"; 440*7219d20fSPierre-Henry Moussay }; 441*7219d20fSPierre-Henry Moussay 442*7219d20fSPierre-Henry Moussay can1: can@2010d000 { 443*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-can", "microchip,mpfs-can"; 444*7219d20fSPierre-Henry Moussay reg = <0x0 0x2010d000 0x0 0x1000>; 445*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>; 446*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 447*7219d20fSPierre-Henry Moussay interrupts = <57>; 448*7219d20fSPierre-Henry Moussay resets = <&mss_top_sysreg CLK_CAN1>; 449*7219d20fSPierre-Henry Moussay status = "disabled"; 450*7219d20fSPierre-Henry Moussay }; 451*7219d20fSPierre-Henry Moussay 452*7219d20fSPierre-Henry Moussay mac0: ethernet@20110000 { 453*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-macb", "microchip,mpfs-macb", 454*7219d20fSPierre-Henry Moussay "cdns,macb"; 455*7219d20fSPierre-Henry Moussay reg = <0x0 0x20110000 0x0 0x2000>; 456*7219d20fSPierre-Henry Moussay #address-cells = <1>; 457*7219d20fSPierre-Henry Moussay #size-cells = <0>; 458*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 459*7219d20fSPierre-Henry Moussay interrupts = <64>, <65>, <66>, <67>, <68>, <69>; 460*7219d20fSPierre-Henry Moussay /* Filled in by a bootloader */ 461*7219d20fSPierre-Henry Moussay local-mac-address = [00 00 00 00 00 00]; 462*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; 463*7219d20fSPierre-Henry Moussay clock-names = "pclk", "hclk"; 464*7219d20fSPierre-Henry Moussay resets = <&mss_top_sysreg CLK_MAC0>; 465*7219d20fSPierre-Henry Moussay status = "disabled"; 466*7219d20fSPierre-Henry Moussay }; 467*7219d20fSPierre-Henry Moussay 468*7219d20fSPierre-Henry Moussay mac1: ethernet@20112000 { 469*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-macb", "microchip,mpfs-macb", 470*7219d20fSPierre-Henry Moussay "cdns,macb"; 471*7219d20fSPierre-Henry Moussay reg = <0x0 0x20112000 0x0 0x2000>; 472*7219d20fSPierre-Henry Moussay #address-cells = <1>; 473*7219d20fSPierre-Henry Moussay #size-cells = <0>; 474*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 475*7219d20fSPierre-Henry Moussay interrupts = <70>, <71>, <72>, <73>, <74>, <75>; 476*7219d20fSPierre-Henry Moussay /* Filled in by a bootloader */ 477*7219d20fSPierre-Henry Moussay local-mac-address = [00 00 00 00 00 00]; 478*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; 479*7219d20fSPierre-Henry Moussay clock-names = "pclk", "hclk"; 480*7219d20fSPierre-Henry Moussay resets = <&mss_top_sysreg CLK_MAC1>; 481*7219d20fSPierre-Henry Moussay status = "disabled"; 482*7219d20fSPierre-Henry Moussay }; 483*7219d20fSPierre-Henry Moussay 484*7219d20fSPierre-Henry Moussay gpio0: gpio@20120000 { 485*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; 486*7219d20fSPierre-Henry Moussay reg = <0x0 0x20120000 0x0 0x1000>; 487*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 488*7219d20fSPierre-Henry Moussay interrupt-controller; 489*7219d20fSPierre-Henry Moussay #interrupt-cells = <1>; 490*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_GPIO0>; 491*7219d20fSPierre-Henry Moussay gpio-controller; 492*7219d20fSPierre-Henry Moussay #gpio-cells = <2>; 493*7219d20fSPierre-Henry Moussay ngpios = <14>; 494*7219d20fSPierre-Henry Moussay status = "disabled"; 495*7219d20fSPierre-Henry Moussay }; 496*7219d20fSPierre-Henry Moussay 497*7219d20fSPierre-Henry Moussay gpio1: gpio@20121000 { 498*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; 499*7219d20fSPierre-Henry Moussay reg = <0x0 0x20121000 0x0 0x1000>; 500*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 501*7219d20fSPierre-Henry Moussay interrupt-controller; 502*7219d20fSPierre-Henry Moussay #interrupt-cells = <1>; 503*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_GPIO1>; 504*7219d20fSPierre-Henry Moussay gpio-controller; 505*7219d20fSPierre-Henry Moussay #gpio-cells = <2>; 506*7219d20fSPierre-Henry Moussay ngpios = <24>; 507*7219d20fSPierre-Henry Moussay status = "disabled"; 508*7219d20fSPierre-Henry Moussay }; 509*7219d20fSPierre-Henry Moussay 510*7219d20fSPierre-Henry Moussay gpio2: gpio@20122000 { 511*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio"; 512*7219d20fSPierre-Henry Moussay reg = <0x0 0x20122000 0x0 0x1000>; 513*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 514*7219d20fSPierre-Henry Moussay interrupt-controller; 515*7219d20fSPierre-Henry Moussay #interrupt-cells = <1>; 516*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_GPIO2>; 517*7219d20fSPierre-Henry Moussay gpio-controller; 518*7219d20fSPierre-Henry Moussay #gpio-cells = <2>; 519*7219d20fSPierre-Henry Moussay ngpios = <32>; 520*7219d20fSPierre-Henry Moussay status = "disabled"; 521*7219d20fSPierre-Henry Moussay }; 522*7219d20fSPierre-Henry Moussay 523*7219d20fSPierre-Henry Moussay rtc: rtc@20124000 { 524*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-rtc", "microchip,mpfs-rtc"; 525*7219d20fSPierre-Henry Moussay reg = <0x0 0x20124000 0x0 0x1000>; 526*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 527*7219d20fSPierre-Henry Moussay interrupts = <80>, <81>; 528*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; 529*7219d20fSPierre-Henry Moussay clock-names = "rtc", "rtcref"; 530*7219d20fSPierre-Henry Moussay status = "disabled"; 531*7219d20fSPierre-Henry Moussay }; 532*7219d20fSPierre-Henry Moussay 533*7219d20fSPierre-Henry Moussay usb: usb@20201000 { 534*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-musb", "microchip,mpfs-musb"; 535*7219d20fSPierre-Henry Moussay reg = <0x0 0x20201000 0x0 0x1000>; 536*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 537*7219d20fSPierre-Henry Moussay interrupts = <86>, <87>; 538*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_USB>; 539*7219d20fSPierre-Henry Moussay interrupt-names = "dma", "mc"; 540*7219d20fSPierre-Henry Moussay status = "disabled"; 541*7219d20fSPierre-Henry Moussay }; 542*7219d20fSPierre-Henry Moussay 543*7219d20fSPierre-Henry Moussay qspi: spi@21000000 { 544*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-qspi", "microchip,coreqspi-rtl-v2"; 545*7219d20fSPierre-Henry Moussay #address-cells = <1>; 546*7219d20fSPierre-Henry Moussay #size-cells = <0>; 547*7219d20fSPierre-Henry Moussay reg = <0x0 0x21000000 0x0 0x1000>; 548*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 549*7219d20fSPierre-Henry Moussay interrupts = <85>; 550*7219d20fSPierre-Henry Moussay clocks = <&clkcfg CLK_QSPI>; 551*7219d20fSPierre-Henry Moussay status = "disabled"; 552*7219d20fSPierre-Henry Moussay }; 553*7219d20fSPierre-Henry Moussay 554*7219d20fSPierre-Henry Moussay control_scb: syscon@37020000 { 555*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-control-scb", 556*7219d20fSPierre-Henry Moussay "microchip,mpfs-control-scb", 557*7219d20fSPierre-Henry Moussay "syscon"; 558*7219d20fSPierre-Henry Moussay reg = <0x0 0x37020000 0x0 0x100>; 559*7219d20fSPierre-Henry Moussay }; 560*7219d20fSPierre-Henry Moussay 561*7219d20fSPierre-Henry Moussay syscontroller_qspi: spi@37020100 { 562*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-qspi", "microchip,coreqspi-rtl-v2"; 563*7219d20fSPierre-Henry Moussay #address-cells = <1>; 564*7219d20fSPierre-Henry Moussay #size-cells = <0>; 565*7219d20fSPierre-Henry Moussay reg = <0x0 0x37020100 0x0 0x100>; 566*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 567*7219d20fSPierre-Henry Moussay interrupts = <110>; 568*7219d20fSPierre-Henry Moussay clocks = <&scbclk>; 569*7219d20fSPierre-Henry Moussay status = "disabled"; 570*7219d20fSPierre-Henry Moussay }; 571*7219d20fSPierre-Henry Moussay 572*7219d20fSPierre-Henry Moussay mbox: mailbox@37020800 { 573*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-mailbox", "microchip,mpfs-mailbox"; 574*7219d20fSPierre-Henry Moussay reg = <0x0 0x37020800 0x0 0x100>; 575*7219d20fSPierre-Henry Moussay interrupt-parent = <&plic>; 576*7219d20fSPierre-Henry Moussay interrupts = <96>; 577*7219d20fSPierre-Henry Moussay #mbox-cells = <1>; 578*7219d20fSPierre-Henry Moussay status = "disabled"; 579*7219d20fSPierre-Henry Moussay }; 580*7219d20fSPierre-Henry Moussay 581*7219d20fSPierre-Henry Moussay ccc_se: clock-controller@38010000 { 582*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; 583*7219d20fSPierre-Henry Moussay reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, 584*7219d20fSPierre-Henry Moussay <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>; 585*7219d20fSPierre-Henry Moussay #clock-cells = <1>; 586*7219d20fSPierre-Henry Moussay status = "disabled"; 587*7219d20fSPierre-Henry Moussay }; 588*7219d20fSPierre-Henry Moussay 589*7219d20fSPierre-Henry Moussay ccc_ne: clock-controller@38040000 { 590*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; 591*7219d20fSPierre-Henry Moussay reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>, 592*7219d20fSPierre-Henry Moussay <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>; 593*7219d20fSPierre-Henry Moussay #clock-cells = <1>; 594*7219d20fSPierre-Henry Moussay status = "disabled"; 595*7219d20fSPierre-Henry Moussay }; 596*7219d20fSPierre-Henry Moussay 597*7219d20fSPierre-Henry Moussay ccc_nw: clock-controller@38100000 { 598*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; 599*7219d20fSPierre-Henry Moussay reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>, 600*7219d20fSPierre-Henry Moussay <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>; 601*7219d20fSPierre-Henry Moussay #clock-cells = <1>; 602*7219d20fSPierre-Henry Moussay status = "disabled"; 603*7219d20fSPierre-Henry Moussay }; 604*7219d20fSPierre-Henry Moussay 605*7219d20fSPierre-Henry Moussay ccc_sw: clock-controller@38400000 { 606*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-ccc", "microchip,mpfs-ccc"; 607*7219d20fSPierre-Henry Moussay reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>, 608*7219d20fSPierre-Henry Moussay <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>; 609*7219d20fSPierre-Henry Moussay #clock-cells = <1>; 610*7219d20fSPierre-Henry Moussay status = "disabled"; 611*7219d20fSPierre-Henry Moussay }; 612*7219d20fSPierre-Henry Moussay 613*7219d20fSPierre-Henry Moussay clkcfg: clkcfg@3e001000 { 614*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-clkcfg", "microchip,mpfs-clkcfg"; 615*7219d20fSPierre-Henry Moussay reg = <0x0 0x3e001000 0x0 0x1000>; 616*7219d20fSPierre-Henry Moussay clocks = <&refclk>; 617*7219d20fSPierre-Henry Moussay #clock-cells = <1>; 618*7219d20fSPierre-Henry Moussay }; 619*7219d20fSPierre-Henry Moussay 620*7219d20fSPierre-Henry Moussay gpio2_pinctrl: pinctrl@41000000 { 621*7219d20fSPierre-Henry Moussay compatible = "microchip,pic64gx-pinctrl-gpio2"; 622*7219d20fSPierre-Henry Moussay reg = <0x0 0x41000000 0x0 0x4>; 623*7219d20fSPierre-Henry Moussay pinctrl-use-default; 624*7219d20fSPierre-Henry Moussay pinctrl-names = "default"; 625*7219d20fSPierre-Henry Moussay pinctrl-0 = <&mdio0_fio>, <&mdio1_fio>, <&spi0_fio>, <&qspi_fio>, 626*7219d20fSPierre-Henry Moussay <&uart3_fio>, <&uart4_fio>, <&can1_fio>, <&can0_fio>, 627*7219d20fSPierre-Henry Moussay <&uart2_fio>; 628*7219d20fSPierre-Henry Moussay }; 629*7219d20fSPierre-Henry Moussay }; 630*7219d20fSPierre-Henry Moussay}; 631