1// SPDX-License-Identifier: (GPL-2.0+ or MIT) 2// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> 3 4#include <dt-bindings/clock/sun6i-rtc.h> 5#include <dt-bindings/clock/sun8i-de2.h> 6#include <dt-bindings/clock/sun8i-tcon-top.h> 7#include <dt-bindings/clock/sun20i-d1-ccu.h> 8#include <dt-bindings/clock/sun20i-d1-r-ccu.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/reset/sun8i-de2.h> 11#include <dt-bindings/reset/sun20i-d1-ccu.h> 12#include <dt-bindings/reset/sun20i-d1-r-ccu.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 dcxo: dcxo-clk { 19 compatible = "fixed-clock"; 20 clock-output-names = "dcxo"; 21 #clock-cells = <0>; 22 }; 23 24 de: display-engine { 25 compatible = "allwinner,sun20i-d1-display-engine"; 26 allwinner,pipelines = <&mixer0>, <&mixer1>; 27 status = "disabled"; 28 }; 29 30 soc { 31 compatible = "simple-bus"; 32 ranges; 33 dma-noncoherent; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 pio: pinctrl@2000000 { 38 compatible = "allwinner,sun20i-d1-pinctrl"; 39 reg = <0x2000000 0x800>; 40 interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>, 41 <SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>, 42 <SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>, 43 <SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>, 44 <SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>, 45 <SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>; 46 clocks = <&ccu CLK_APB0>, 47 <&dcxo>, 48 <&rtc CLK_OSC32K>; 49 clock-names = "apb", "hosc", "losc"; 50 gpio-controller; 51 interrupt-controller; 52 #gpio-cells = <3>; 53 #interrupt-cells = <3>; 54 55 /omit-if-no-ref/ 56 clk_pg11_pin: clk-pg11-pin { 57 pins = "PG11"; 58 function = "clk"; 59 }; 60 61 /omit-if-no-ref/ 62 dsi_4lane_pins: dsi-4lane-pins { 63 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 64 "PD6", "PD7", "PD8", "PD9"; 65 drive-strength = <30>; 66 function = "dsi"; 67 }; 68 69 /omit-if-no-ref/ 70 lcd_rgb666_pins: lcd-rgb666-pins { 71 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 72 "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", 73 "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", 74 "PD18", "PD19", "PD20", "PD21"; 75 function = "lcd0"; 76 }; 77 78 /omit-if-no-ref/ 79 mmc0_pins: mmc0-pins { 80 pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; 81 function = "mmc0"; 82 }; 83 84 /omit-if-no-ref/ 85 mmc1_pins: mmc1-pins { 86 pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; 87 function = "mmc1"; 88 }; 89 90 /omit-if-no-ref/ 91 mmc2_pins: mmc2-pins { 92 pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; 93 function = "mmc2"; 94 }; 95 96 /omit-if-no-ref/ 97 rgmii_pe_pins: rgmii-pe-pins { 98 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 99 "PE5", "PE6", "PE7", "PE8", "PE9", 100 "PE11", "PE12", "PE13", "PE14", "PE15"; 101 function = "emac"; 102 }; 103 104 /omit-if-no-ref/ 105 rmii_pe_pins: rmii-pe-pins { 106 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 107 "PE5", "PE6", "PE7", "PE8", "PE9"; 108 function = "emac"; 109 }; 110 111 /omit-if-no-ref/ 112 spi0_pins: spi0-pins { 113 pins = "PC2", "PC3", "PC4", "PC5"; 114 function = "spi0"; 115 }; 116 117 /omit-if-no-ref/ 118 uart1_pg6_pins: uart1-pg6-pins { 119 pins = "PG6", "PG7"; 120 function = "uart1"; 121 }; 122 123 /omit-if-no-ref/ 124 uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { 125 pins = "PG8", "PG9"; 126 function = "uart1"; 127 }; 128 129 /omit-if-no-ref/ 130 uart3_pb_pins: uart3-pb-pins { 131 pins = "PB6", "PB7"; 132 function = "uart3"; 133 }; 134 135 /omit-if-no-ref/ 136 can0_pins: can0-pins { 137 pins = "PB2", "PB3"; 138 function = "can0"; 139 }; 140 141 /omit-if-no-ref/ 142 can1_pins: can1-pins { 143 pins = "PB4", "PB5"; 144 function = "can1"; 145 }; 146 }; 147 148 ccu: clock-controller@2001000 { 149 compatible = "allwinner,sun20i-d1-ccu"; 150 reg = <0x2001000 0x1000>; 151 clocks = <&dcxo>, 152 <&rtc CLK_OSC32K>, 153 <&rtc CLK_IOSC>; 154 clock-names = "hosc", "losc", "iosc"; 155 #clock-cells = <1>; 156 #reset-cells = <1>; 157 }; 158 159 dmic: dmic@2031000 { 160 compatible = "allwinner,sun20i-d1-dmic", 161 "allwinner,sun50i-h6-dmic"; 162 reg = <0x2031000 0x400>; 163 interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>; 164 clocks = <&ccu CLK_BUS_DMIC>, 165 <&ccu CLK_DMIC>; 166 clock-names = "bus", "mod"; 167 resets = <&ccu RST_BUS_DMIC>; 168 dmas = <&dma 8>; 169 dma-names = "rx"; 170 status = "disabled"; 171 #sound-dai-cells = <0>; 172 }; 173 174 i2s1: i2s@2033000 { 175 compatible = "allwinner,sun20i-d1-i2s", 176 "allwinner,sun50i-r329-i2s"; 177 reg = <0x2033000 0x1000>; 178 interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&ccu CLK_BUS_I2S1>, 180 <&ccu CLK_I2S1>; 181 clock-names = "apb", "mod"; 182 resets = <&ccu RST_BUS_I2S1>; 183 dmas = <&dma 4>, <&dma 4>; 184 dma-names = "rx", "tx"; 185 status = "disabled"; 186 #sound-dai-cells = <0>; 187 }; 188 189 i2s2: i2s@2034000 { 190 compatible = "allwinner,sun20i-d1-i2s", 191 "allwinner,sun50i-r329-i2s"; 192 reg = <0x2034000 0x1000>; 193 interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&ccu CLK_BUS_I2S2>, 195 <&ccu CLK_I2S2>; 196 clock-names = "apb", "mod"; 197 resets = <&ccu RST_BUS_I2S2>; 198 dmas = <&dma 5>, <&dma 5>; 199 dma-names = "rx", "tx"; 200 status = "disabled"; 201 #sound-dai-cells = <0>; 202 }; 203 204 timer: timer@2050000 { 205 compatible = "allwinner,sun20i-d1-timer", 206 "allwinner,sun8i-a23-timer"; 207 reg = <0x2050000 0xa0>; 208 interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>, 209 <SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&dcxo>; 211 }; 212 213 wdt: watchdog@20500a0 { 214 compatible = "allwinner,sun20i-d1-wdt-reset", 215 "allwinner,sun20i-d1-wdt"; 216 reg = <0x20500a0 0x20>; 217 interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&dcxo>, <&rtc CLK_OSC32K>; 219 clock-names = "hosc", "losc"; 220 status = "reserved"; 221 }; 222 223 uart0: serial@2500000 { 224 compatible = "snps,dw-apb-uart"; 225 reg = <0x2500000 0x400>; 226 reg-io-width = <4>; 227 reg-shift = <2>; 228 interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&ccu CLK_BUS_UART0>; 230 resets = <&ccu RST_BUS_UART0>; 231 dmas = <&dma 14>, <&dma 14>; 232 dma-names = "tx", "rx"; 233 status = "disabled"; 234 }; 235 236 uart1: serial@2500400 { 237 compatible = "snps,dw-apb-uart"; 238 reg = <0x2500400 0x400>; 239 reg-io-width = <4>; 240 reg-shift = <2>; 241 interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&ccu CLK_BUS_UART1>; 243 resets = <&ccu RST_BUS_UART1>; 244 dmas = <&dma 15>, <&dma 15>; 245 dma-names = "tx", "rx"; 246 status = "disabled"; 247 }; 248 249 uart2: serial@2500800 { 250 compatible = "snps,dw-apb-uart"; 251 reg = <0x2500800 0x400>; 252 reg-io-width = <4>; 253 reg-shift = <2>; 254 interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&ccu CLK_BUS_UART2>; 256 resets = <&ccu RST_BUS_UART2>; 257 dmas = <&dma 16>, <&dma 16>; 258 dma-names = "tx", "rx"; 259 status = "disabled"; 260 }; 261 262 uart3: serial@2500c00 { 263 compatible = "snps,dw-apb-uart"; 264 reg = <0x2500c00 0x400>; 265 reg-io-width = <4>; 266 reg-shift = <2>; 267 interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&ccu CLK_BUS_UART3>; 269 resets = <&ccu RST_BUS_UART3>; 270 dmas = <&dma 17>, <&dma 17>; 271 dma-names = "tx", "rx"; 272 status = "disabled"; 273 }; 274 275 uart4: serial@2501000 { 276 compatible = "snps,dw-apb-uart"; 277 reg = <0x2501000 0x400>; 278 reg-io-width = <4>; 279 reg-shift = <2>; 280 interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&ccu CLK_BUS_UART4>; 282 resets = <&ccu RST_BUS_UART4>; 283 dmas = <&dma 18>, <&dma 18>; 284 dma-names = "tx", "rx"; 285 status = "disabled"; 286 }; 287 288 uart5: serial@2501400 { 289 compatible = "snps,dw-apb-uart"; 290 reg = <0x2501400 0x400>; 291 reg-io-width = <4>; 292 reg-shift = <2>; 293 interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&ccu CLK_BUS_UART5>; 295 resets = <&ccu RST_BUS_UART5>; 296 dmas = <&dma 19>, <&dma 19>; 297 dma-names = "tx", "rx"; 298 status = "disabled"; 299 }; 300 301 i2c0: i2c@2502000 { 302 compatible = "allwinner,sun20i-d1-i2c", 303 "allwinner,sun8i-v536-i2c", 304 "allwinner,sun6i-a31-i2c"; 305 reg = <0x2502000 0x400>; 306 interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&ccu CLK_BUS_I2C0>; 308 resets = <&ccu RST_BUS_I2C0>; 309 dmas = <&dma 43>, <&dma 43>; 310 dma-names = "rx", "tx"; 311 status = "disabled"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 }; 315 316 i2c1: i2c@2502400 { 317 compatible = "allwinner,sun20i-d1-i2c", 318 "allwinner,sun8i-v536-i2c", 319 "allwinner,sun6i-a31-i2c"; 320 reg = <0x2502400 0x400>; 321 interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&ccu CLK_BUS_I2C1>; 323 resets = <&ccu RST_BUS_I2C1>; 324 dmas = <&dma 44>, <&dma 44>; 325 dma-names = "rx", "tx"; 326 status = "disabled"; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 }; 330 331 i2c2: i2c@2502800 { 332 compatible = "allwinner,sun20i-d1-i2c", 333 "allwinner,sun8i-v536-i2c", 334 "allwinner,sun6i-a31-i2c"; 335 reg = <0x2502800 0x400>; 336 interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&ccu CLK_BUS_I2C2>; 338 resets = <&ccu RST_BUS_I2C2>; 339 dmas = <&dma 45>, <&dma 45>; 340 dma-names = "rx", "tx"; 341 status = "disabled"; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 }; 345 346 i2c3: i2c@2502c00 { 347 compatible = "allwinner,sun20i-d1-i2c", 348 "allwinner,sun8i-v536-i2c", 349 "allwinner,sun6i-a31-i2c"; 350 reg = <0x2502c00 0x400>; 351 interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&ccu CLK_BUS_I2C3>; 353 resets = <&ccu RST_BUS_I2C3>; 354 dmas = <&dma 46>, <&dma 46>; 355 dma-names = "rx", "tx"; 356 status = "disabled"; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 }; 360 361 syscon: syscon@3000000 { 362 compatible = "allwinner,sun20i-d1-system-control"; 363 reg = <0x3000000 0x1000>; 364 ranges; 365 #address-cells = <1>; 366 #size-cells = <1>; 367 }; 368 369 dma: dma-controller@3002000 { 370 compatible = "allwinner,sun20i-d1-dma"; 371 reg = <0x3002000 0x1000>; 372 interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 374 clock-names = "bus", "mbus"; 375 resets = <&ccu RST_BUS_DMA>; 376 dma-channels = <16>; 377 dma-requests = <48>; 378 #dma-cells = <1>; 379 }; 380 381 sid: efuse@3006000 { 382 compatible = "allwinner,sun20i-d1-sid"; 383 reg = <0x3006000 0x1000>; 384 #address-cells = <1>; 385 #size-cells = <1>; 386 }; 387 388 crypto: crypto@3040000 { 389 compatible = "allwinner,sun20i-d1-crypto"; 390 reg = <0x3040000 0x800>; 391 interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&ccu CLK_BUS_CE>, 393 <&ccu CLK_CE>, 394 <&ccu CLK_MBUS_CE>, 395 <&rtc CLK_IOSC>; 396 clock-names = "bus", "mod", "ram", "trng"; 397 resets = <&ccu RST_BUS_CE>; 398 }; 399 400 mbus: dram-controller@3102000 { 401 compatible = "allwinner,sun20i-d1-mbus"; 402 reg = <0x3102000 0x1000>, 403 <0x3103000 0x1000>; 404 reg-names = "mbus", "dram"; 405 interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&ccu CLK_MBUS>, 407 <&ccu CLK_DRAM>, 408 <&ccu CLK_BUS_DRAM>; 409 clock-names = "mbus", "dram", "bus"; 410 dma-ranges = <0 0x40000000 0x80000000>; 411 #address-cells = <1>; 412 #size-cells = <1>; 413 #interconnect-cells = <1>; 414 }; 415 416 mmc0: mmc@4020000 { 417 compatible = "allwinner,sun20i-d1-mmc"; 418 reg = <0x4020000 0x1000>; 419 interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 421 clock-names = "ahb", "mmc"; 422 resets = <&ccu RST_BUS_MMC0>; 423 reset-names = "ahb"; 424 cap-sd-highspeed; 425 max-frequency = <150000000>; 426 no-mmc; 427 status = "disabled"; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 }; 431 432 mmc1: mmc@4021000 { 433 compatible = "allwinner,sun20i-d1-mmc"; 434 reg = <0x4021000 0x1000>; 435 interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 437 clock-names = "ahb", "mmc"; 438 resets = <&ccu RST_BUS_MMC1>; 439 reset-names = "ahb"; 440 cap-sd-highspeed; 441 max-frequency = <150000000>; 442 no-mmc; 443 status = "disabled"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 }; 447 448 mmc2: mmc@4022000 { 449 compatible = "allwinner,sun20i-d1-emmc", 450 "allwinner,sun50i-a100-emmc"; 451 reg = <0x4022000 0x1000>; 452 interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 454 clock-names = "ahb", "mmc"; 455 resets = <&ccu RST_BUS_MMC2>; 456 reset-names = "ahb"; 457 cap-mmc-highspeed; 458 max-frequency = <150000000>; 459 mmc-ddr-1_8v; 460 mmc-ddr-3_3v; 461 no-sd; 462 no-sdio; 463 status = "disabled"; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 }; 467 468 spi0: spi@4025000 { 469 compatible = "allwinner,sun20i-d1-spi", 470 "allwinner,sun50i-r329-spi"; 471 reg = <0x04025000 0x1000>; 472 interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 474 clock-names = "ahb", "mod"; 475 dmas = <&dma 22>, <&dma 22>; 476 dma-names = "rx", "tx"; 477 resets = <&ccu RST_BUS_SPI0>; 478 status = "disabled"; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 }; 482 483 spi1: spi@4026000 { 484 compatible = "allwinner,sun20i-d1-spi-dbi", 485 "allwinner,sun50i-r329-spi-dbi", 486 "allwinner,sun50i-r329-spi"; 487 reg = <0x04026000 0x1000>; 488 interrupts = <SOC_PERIPHERAL_IRQ(16) IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 490 clock-names = "ahb", "mod"; 491 dmas = <&dma 23>, <&dma 23>; 492 dma-names = "rx", "tx"; 493 resets = <&ccu RST_BUS_SPI1>; 494 status = "disabled"; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 }; 498 499 usb_otg: usb@4100000 { 500 compatible = "allwinner,sun20i-d1-musb", 501 "allwinner,sun8i-a33-musb"; 502 reg = <0x4100000 0x400>; 503 interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>; 504 interrupt-names = "mc"; 505 clocks = <&ccu CLK_BUS_OTG>; 506 resets = <&ccu RST_BUS_OTG>; 507 extcon = <&usbphy 0>; 508 phys = <&usbphy 0>; 509 phy-names = "usb"; 510 status = "disabled"; 511 }; 512 513 usbphy: phy@4100400 { 514 compatible = "allwinner,sun20i-d1-usb-phy"; 515 reg = <0x4100400 0x100>, 516 <0x4101800 0x100>, 517 <0x4200800 0x100>; 518 reg-names = "phy_ctrl", 519 "pmu0", 520 "pmu1"; 521 clocks = <&dcxo>, 522 <&dcxo>; 523 clock-names = "usb0_phy", 524 "usb1_phy"; 525 resets = <&ccu RST_USB_PHY0>, 526 <&ccu RST_USB_PHY1>; 527 reset-names = "usb0_reset", 528 "usb1_reset"; 529 status = "disabled"; 530 #phy-cells = <1>; 531 }; 532 533 ehci0: usb@4101000 { 534 compatible = "allwinner,sun20i-d1-ehci", 535 "generic-ehci"; 536 reg = <0x4101000 0x100>; 537 interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&ccu CLK_BUS_OHCI0>, 539 <&ccu CLK_BUS_EHCI0>, 540 <&ccu CLK_USB_OHCI0>; 541 resets = <&ccu RST_BUS_OHCI0>, 542 <&ccu RST_BUS_EHCI0>; 543 phys = <&usbphy 0>; 544 phy-names = "usb"; 545 status = "disabled"; 546 }; 547 548 ohci0: usb@4101400 { 549 compatible = "allwinner,sun20i-d1-ohci", 550 "generic-ohci"; 551 reg = <0x4101400 0x100>; 552 interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&ccu CLK_BUS_OHCI0>, 554 <&ccu CLK_USB_OHCI0>; 555 resets = <&ccu RST_BUS_OHCI0>; 556 phys = <&usbphy 0>; 557 phy-names = "usb"; 558 status = "disabled"; 559 }; 560 561 ehci1: usb@4200000 { 562 compatible = "allwinner,sun20i-d1-ehci", 563 "generic-ehci"; 564 reg = <0x4200000 0x100>; 565 interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&ccu CLK_BUS_OHCI1>, 567 <&ccu CLK_BUS_EHCI1>, 568 <&ccu CLK_USB_OHCI1>; 569 resets = <&ccu RST_BUS_OHCI1>, 570 <&ccu RST_BUS_EHCI1>; 571 phys = <&usbphy 1>; 572 phy-names = "usb"; 573 status = "disabled"; 574 }; 575 576 ohci1: usb@4200400 { 577 compatible = "allwinner,sun20i-d1-ohci", 578 "generic-ohci"; 579 reg = <0x4200400 0x100>; 580 interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&ccu CLK_BUS_OHCI1>, 582 <&ccu CLK_USB_OHCI1>; 583 resets = <&ccu RST_BUS_OHCI1>; 584 phys = <&usbphy 1>; 585 phy-names = "usb"; 586 status = "disabled"; 587 }; 588 589 emac: ethernet@4500000 { 590 compatible = "allwinner,sun20i-d1-emac", 591 "allwinner,sun50i-a64-emac"; 592 reg = <0x4500000 0x10000>; 593 interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>; 594 interrupt-names = "macirq"; 595 clocks = <&ccu CLK_BUS_EMAC>; 596 clock-names = "stmmaceth"; 597 resets = <&ccu RST_BUS_EMAC>; 598 reset-names = "stmmaceth"; 599 syscon = <&syscon>; 600 status = "disabled"; 601 602 mdio: mdio { 603 compatible = "snps,dwmac-mdio"; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 }; 607 }; 608 609 display_clocks: clock-controller@5000000 { 610 compatible = "allwinner,sun20i-d1-de2-clk", 611 "allwinner,sun50i-h5-de2-clk"; 612 reg = <0x5000000 0x10000>; 613 clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; 614 clock-names = "bus", "mod"; 615 resets = <&ccu RST_BUS_DE>; 616 #clock-cells = <1>; 617 #reset-cells = <1>; 618 }; 619 620 mixer0: mixer@5100000 { 621 compatible = "allwinner,sun20i-d1-de2-mixer-0"; 622 reg = <0x5100000 0x100000>; 623 clocks = <&display_clocks CLK_BUS_MIXER0>, 624 <&display_clocks CLK_MIXER0>; 625 clock-names = "bus", "mod"; 626 resets = <&display_clocks RST_MIXER0>; 627 628 ports { 629 #address-cells = <1>; 630 #size-cells = <0>; 631 632 mixer0_out: port@1 { 633 reg = <1>; 634 635 mixer0_out_tcon_top_mixer0: endpoint { 636 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 637 }; 638 }; 639 }; 640 }; 641 642 mixer1: mixer@5200000 { 643 compatible = "allwinner,sun20i-d1-de2-mixer-1"; 644 reg = <0x5200000 0x100000>; 645 clocks = <&display_clocks CLK_BUS_MIXER1>, 646 <&display_clocks CLK_MIXER1>; 647 clock-names = "bus", "mod"; 648 resets = <&display_clocks RST_MIXER1>; 649 650 ports { 651 #address-cells = <1>; 652 #size-cells = <0>; 653 654 mixer1_out: port@1 { 655 reg = <1>; 656 657 mixer1_out_tcon_top_mixer1: endpoint { 658 remote-endpoint = <&tcon_top_mixer1_in_mixer1>; 659 }; 660 }; 661 }; 662 }; 663 664 dsi: dsi@5450000 { 665 compatible = "allwinner,sun20i-d1-mipi-dsi", 666 "allwinner,sun50i-a100-mipi-dsi"; 667 reg = <0x5450000 0x1000>; 668 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&ccu CLK_BUS_MIPI_DSI>, 670 <&tcon_top CLK_TCON_TOP_DSI>; 671 clock-names = "bus", "mod"; 672 resets = <&ccu RST_BUS_MIPI_DSI>; 673 phys = <&dphy>; 674 phy-names = "dphy"; 675 status = "disabled"; 676 677 port { 678 dsi_in_tcon_lcd0: endpoint { 679 remote-endpoint = <&tcon_lcd0_out_dsi>; 680 }; 681 }; 682 }; 683 684 dphy: phy@5451000 { 685 compatible = "allwinner,sun20i-d1-mipi-dphy", 686 "allwinner,sun50i-a100-mipi-dphy"; 687 reg = <0x5451000 0x1000>; 688 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&ccu CLK_BUS_MIPI_DSI>, 690 <&ccu CLK_MIPI_DSI>; 691 clock-names = "bus", "mod"; 692 resets = <&ccu RST_BUS_MIPI_DSI>; 693 #phy-cells = <0>; 694 }; 695 696 tcon_top: tcon-top@5460000 { 697 compatible = "allwinner,sun20i-d1-tcon-top"; 698 reg = <0x5460000 0x1000>; 699 clocks = <&ccu CLK_BUS_DPSS_TOP>, 700 <&ccu CLK_TCON_TV>, 701 <&ccu CLK_TVE>, 702 <&ccu CLK_TCON_LCD0>; 703 clock-names = "bus", "tcon-tv0", "tve0", "dsi"; 704 clock-output-names = "tcon-top-tv0", "tcon-top-dsi"; 705 resets = <&ccu RST_BUS_DPSS_TOP>; 706 #clock-cells = <1>; 707 708 ports { 709 #address-cells = <1>; 710 #size-cells = <0>; 711 712 tcon_top_mixer0_in: port@0 { 713 reg = <0>; 714 715 tcon_top_mixer0_in_mixer0: endpoint { 716 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 717 }; 718 }; 719 720 tcon_top_mixer0_out: port@1 { 721 reg = <1>; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 725 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { 726 reg = <0>; 727 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; 728 }; 729 730 tcon_top_mixer0_out_tcon_tv0: endpoint@2 { 731 reg = <2>; 732 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; 733 }; 734 }; 735 736 tcon_top_mixer1_in: port@2 { 737 reg = <2>; 738 #address-cells = <1>; 739 #size-cells = <0>; 740 741 tcon_top_mixer1_in_mixer1: endpoint@1 { 742 reg = <1>; 743 remote-endpoint = <&mixer1_out_tcon_top_mixer1>; 744 }; 745 }; 746 747 tcon_top_mixer1_out: port@3 { 748 reg = <3>; 749 #address-cells = <1>; 750 #size-cells = <0>; 751 752 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { 753 reg = <0>; 754 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>; 755 }; 756 757 tcon_top_mixer1_out_tcon_tv0: endpoint@2 { 758 reg = <2>; 759 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; 760 }; 761 }; 762 763 tcon_top_hdmi_in: port@4 { 764 reg = <4>; 765 766 tcon_top_hdmi_in_tcon_tv0: endpoint { 767 remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>; 768 }; 769 }; 770 771 tcon_top_hdmi_out: port@5 { 772 reg = <5>; 773 }; 774 }; 775 }; 776 777 tcon_lcd0: lcd-controller@5461000 { 778 compatible = "allwinner,sun20i-d1-tcon-lcd"; 779 reg = <0x5461000 0x1000>; 780 interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&ccu CLK_BUS_TCON_LCD0>, 782 <&ccu CLK_TCON_LCD0>; 783 clock-names = "ahb", "tcon-ch0"; 784 clock-output-names = "tcon-pixel-clock"; 785 resets = <&ccu RST_BUS_TCON_LCD0>, 786 <&ccu RST_BUS_LVDS0>; 787 reset-names = "lcd", "lvds"; 788 #clock-cells = <0>; 789 790 ports { 791 #address-cells = <1>; 792 #size-cells = <0>; 793 794 tcon_lcd0_in: port@0 { 795 reg = <0>; 796 #address-cells = <1>; 797 #size-cells = <0>; 798 799 tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { 800 reg = <0>; 801 remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; 802 }; 803 804 tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { 805 reg = <1>; 806 remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>; 807 }; 808 }; 809 810 tcon_lcd0_out: port@1 { 811 reg = <1>; 812 #address-cells = <1>; 813 #size-cells = <0>; 814 815 tcon_lcd0_out_dsi: endpoint@1 { 816 reg = <1>; 817 remote-endpoint = <&dsi_in_tcon_lcd0>; 818 }; 819 }; 820 }; 821 }; 822 823 tcon_tv0: lcd-controller@5470000 { 824 compatible = "allwinner,sun20i-d1-tcon-tv"; 825 reg = <0x5470000 0x1000>; 826 interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&ccu CLK_BUS_TCON_TV>, 828 <&tcon_top CLK_TCON_TOP_TV0>; 829 clock-names = "ahb", "tcon-ch1"; 830 resets = <&ccu RST_BUS_TCON_TV>; 831 reset-names = "lcd"; 832 833 ports { 834 #address-cells = <1>; 835 #size-cells = <0>; 836 837 tcon_tv0_in: port@0 { 838 reg = <0>; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 842 tcon_tv0_in_tcon_top_mixer0: endpoint@0 { 843 reg = <0>; 844 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; 845 }; 846 847 tcon_tv0_in_tcon_top_mixer1: endpoint@1 { 848 reg = <1>; 849 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; 850 }; 851 }; 852 853 tcon_tv0_out: port@1 { 854 reg = <1>; 855 856 tcon_tv0_out_tcon_top_hdmi: endpoint { 857 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; 858 }; 859 }; 860 }; 861 }; 862 863 ppu: power-controller@7001000 { 864 compatible = "allwinner,sun20i-d1-ppu"; 865 reg = <0x7001000 0x1000>; 866 clocks = <&r_ccu CLK_BUS_R_PPU>; 867 resets = <&r_ccu RST_BUS_R_PPU>; 868 #power-domain-cells = <1>; 869 }; 870 871 r_ccu: clock-controller@7010000 { 872 compatible = "allwinner,sun20i-d1-r-ccu"; 873 reg = <0x7010000 0x400>; 874 clocks = <&dcxo>, 875 <&rtc CLK_OSC32K>, 876 <&rtc CLK_IOSC>, 877 <&ccu CLK_PLL_PERIPH0_DIV3>; 878 clock-names = "hosc", "losc", "iosc", "pll-periph"; 879 #clock-cells = <1>; 880 #reset-cells = <1>; 881 }; 882 883 rtc: rtc@7090000 { 884 compatible = "allwinner,sun20i-d1-rtc", 885 "allwinner,sun50i-r329-rtc"; 886 reg = <0x7090000 0x400>; 887 interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&r_ccu CLK_BUS_R_RTC>, 889 <&dcxo>, 890 <&r_ccu CLK_R_AHB>; 891 clock-names = "bus", "hosc", "ahb"; 892 #clock-cells = <1>; 893 }; 894 895 can0: can@2504000 { 896 compatible = "allwinner,sun20i-d1-can"; 897 reg = <0x02504000 0x400>; 898 interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&ccu CLK_BUS_CAN0>; 900 resets = <&ccu RST_BUS_CAN0>; 901 status = "disabled"; 902 }; 903 904 can1: can@2504400 { 905 compatible = "allwinner,sun20i-d1-can"; 906 reg = <0x02504400 0x400>; 907 interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&ccu CLK_BUS_CAN1>; 909 resets = <&ccu RST_BUS_CAN1>; 910 status = "disabled"; 911 }; 912 }; 913}; 914