1// SPDX-License-Identifier: (GPL-2.0+ or MIT) 2// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> 3 4#include <dt-bindings/clock/sun6i-rtc.h> 5#include <dt-bindings/clock/sun8i-de2.h> 6#include <dt-bindings/clock/sun8i-tcon-top.h> 7#include <dt-bindings/clock/sun20i-d1-ccu.h> 8#include <dt-bindings/clock/sun20i-d1-r-ccu.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/reset/sun8i-de2.h> 11#include <dt-bindings/reset/sun20i-d1-ccu.h> 12#include <dt-bindings/reset/sun20i-d1-r-ccu.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 dcxo: dcxo-clk { 19 compatible = "fixed-clock"; 20 clock-output-names = "dcxo"; 21 #clock-cells = <0>; 22 }; 23 24 de: display-engine { 25 compatible = "allwinner,sun20i-d1-display-engine"; 26 allwinner,pipelines = <&mixer0>, <&mixer1>; 27 status = "disabled"; 28 }; 29 30 soc { 31 compatible = "simple-bus"; 32 ranges; 33 dma-noncoherent; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 pio: pinctrl@2000000 { 38 compatible = "allwinner,sun20i-d1-pinctrl"; 39 reg = <0x2000000 0x800>; 40 interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>, 41 <SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>, 42 <SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>, 43 <SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>, 44 <SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>, 45 <SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>; 46 clocks = <&ccu CLK_APB0>, 47 <&dcxo>, 48 <&rtc CLK_OSC32K>; 49 clock-names = "apb", "hosc", "losc"; 50 gpio-controller; 51 interrupt-controller; 52 #gpio-cells = <3>; 53 #interrupt-cells = <3>; 54 55 /omit-if-no-ref/ 56 clk_pg11_pin: clk-pg11-pin { 57 pins = "PG11"; 58 function = "clk"; 59 }; 60 61 /omit-if-no-ref/ 62 dsi_4lane_pins: dsi-4lane-pins { 63 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 64 "PD6", "PD7", "PD8", "PD9"; 65 drive-strength = <30>; 66 function = "dsi"; 67 }; 68 69 /omit-if-no-ref/ 70 lcd_rgb666_pins: lcd-rgb666-pins { 71 pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", 72 "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", 73 "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", 74 "PD18", "PD19", "PD20", "PD21"; 75 function = "lcd0"; 76 }; 77 78 /omit-if-no-ref/ 79 mmc0_pins: mmc0-pins { 80 pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; 81 function = "mmc0"; 82 }; 83 84 /omit-if-no-ref/ 85 mmc1_pins: mmc1-pins { 86 pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; 87 function = "mmc1"; 88 }; 89 90 /omit-if-no-ref/ 91 mmc2_pins: mmc2-pins { 92 pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; 93 function = "mmc2"; 94 }; 95 96 /omit-if-no-ref/ 97 rgmii_pe_pins: rgmii-pe-pins { 98 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 99 "PE5", "PE6", "PE7", "PE8", "PE9", 100 "PE11", "PE12", "PE13", "PE14", "PE15"; 101 function = "emac"; 102 }; 103 104 /omit-if-no-ref/ 105 rmii_pe_pins: rmii-pe-pins { 106 pins = "PE0", "PE1", "PE2", "PE3", "PE4", 107 "PE5", "PE6", "PE7", "PE8", "PE9"; 108 function = "emac"; 109 }; 110 111 /omit-if-no-ref/ 112 spi0_pins: spi0-pins { 113 pins = "PC2", "PC3", "PC4", "PC5"; 114 function = "spi0"; 115 }; 116 117 /omit-if-no-ref/ 118 uart1_pg6_pins: uart1-pg6-pins { 119 pins = "PG6", "PG7"; 120 function = "uart1"; 121 }; 122 123 /omit-if-no-ref/ 124 uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { 125 pins = "PG8", "PG9"; 126 function = "uart1"; 127 }; 128 129 /omit-if-no-ref/ 130 uart3_pb_pins: uart3-pb-pins { 131 pins = "PB6", "PB7"; 132 function = "uart3"; 133 }; 134 }; 135 136 ccu: clock-controller@2001000 { 137 compatible = "allwinner,sun20i-d1-ccu"; 138 reg = <0x2001000 0x1000>; 139 clocks = <&dcxo>, 140 <&rtc CLK_OSC32K>, 141 <&rtc CLK_IOSC>; 142 clock-names = "hosc", "losc", "iosc"; 143 #clock-cells = <1>; 144 #reset-cells = <1>; 145 }; 146 147 gpadc: adc@2009000 { 148 compatible = "allwinner,sun20i-d1-gpadc"; 149 reg = <0x2009000 0x400>; 150 clocks = <&ccu CLK_BUS_GPADC>; 151 resets = <&ccu RST_BUS_GPADC>; 152 interrupts = <SOC_PERIPHERAL_IRQ(57) IRQ_TYPE_LEVEL_HIGH>; 153 status = "disabled"; 154 #io-channel-cells = <1>; 155 }; 156 157 dmic: dmic@2031000 { 158 compatible = "allwinner,sun20i-d1-dmic", 159 "allwinner,sun50i-h6-dmic"; 160 reg = <0x2031000 0x400>; 161 interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&ccu CLK_BUS_DMIC>, 163 <&ccu CLK_DMIC>; 164 clock-names = "bus", "mod"; 165 resets = <&ccu RST_BUS_DMIC>; 166 dmas = <&dma 8>; 167 dma-names = "rx"; 168 status = "disabled"; 169 #sound-dai-cells = <0>; 170 }; 171 172 i2s1: i2s@2033000 { 173 compatible = "allwinner,sun20i-d1-i2s", 174 "allwinner,sun50i-r329-i2s"; 175 reg = <0x2033000 0x1000>; 176 interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&ccu CLK_BUS_I2S1>, 178 <&ccu CLK_I2S1>; 179 clock-names = "apb", "mod"; 180 resets = <&ccu RST_BUS_I2S1>; 181 dmas = <&dma 4>, <&dma 4>; 182 dma-names = "rx", "tx"; 183 status = "disabled"; 184 #sound-dai-cells = <0>; 185 }; 186 187 i2s2: i2s@2034000 { 188 compatible = "allwinner,sun20i-d1-i2s", 189 "allwinner,sun50i-r329-i2s"; 190 reg = <0x2034000 0x1000>; 191 interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>; 192 clocks = <&ccu CLK_BUS_I2S2>, 193 <&ccu CLK_I2S2>; 194 clock-names = "apb", "mod"; 195 resets = <&ccu RST_BUS_I2S2>; 196 dmas = <&dma 5>, <&dma 5>; 197 dma-names = "rx", "tx"; 198 status = "disabled"; 199 #sound-dai-cells = <0>; 200 }; 201 202 timer: timer@2050000 { 203 compatible = "allwinner,sun20i-d1-timer", 204 "allwinner,sun8i-a23-timer"; 205 reg = <0x2050000 0xa0>; 206 interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>, 207 <SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&dcxo>; 209 }; 210 211 wdt: watchdog@20500a0 { 212 compatible = "allwinner,sun20i-d1-wdt-reset", 213 "allwinner,sun20i-d1-wdt"; 214 reg = <0x20500a0 0x20>; 215 interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&dcxo>, <&rtc CLK_OSC32K>; 217 clock-names = "hosc", "losc"; 218 status = "reserved"; 219 }; 220 221 uart0: serial@2500000 { 222 compatible = "snps,dw-apb-uart"; 223 reg = <0x2500000 0x400>; 224 reg-io-width = <4>; 225 reg-shift = <2>; 226 interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&ccu CLK_BUS_UART0>; 228 resets = <&ccu RST_BUS_UART0>; 229 dmas = <&dma 14>, <&dma 14>; 230 dma-names = "tx", "rx"; 231 status = "disabled"; 232 }; 233 234 uart1: serial@2500400 { 235 compatible = "snps,dw-apb-uart"; 236 reg = <0x2500400 0x400>; 237 reg-io-width = <4>; 238 reg-shift = <2>; 239 interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&ccu CLK_BUS_UART1>; 241 resets = <&ccu RST_BUS_UART1>; 242 dmas = <&dma 15>, <&dma 15>; 243 dma-names = "tx", "rx"; 244 status = "disabled"; 245 }; 246 247 uart2: serial@2500800 { 248 compatible = "snps,dw-apb-uart"; 249 reg = <0x2500800 0x400>; 250 reg-io-width = <4>; 251 reg-shift = <2>; 252 interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&ccu CLK_BUS_UART2>; 254 resets = <&ccu RST_BUS_UART2>; 255 dmas = <&dma 16>, <&dma 16>; 256 dma-names = "tx", "rx"; 257 status = "disabled"; 258 }; 259 260 uart3: serial@2500c00 { 261 compatible = "snps,dw-apb-uart"; 262 reg = <0x2500c00 0x400>; 263 reg-io-width = <4>; 264 reg-shift = <2>; 265 interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&ccu CLK_BUS_UART3>; 267 resets = <&ccu RST_BUS_UART3>; 268 dmas = <&dma 17>, <&dma 17>; 269 dma-names = "tx", "rx"; 270 status = "disabled"; 271 }; 272 273 uart4: serial@2501000 { 274 compatible = "snps,dw-apb-uart"; 275 reg = <0x2501000 0x400>; 276 reg-io-width = <4>; 277 reg-shift = <2>; 278 interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&ccu CLK_BUS_UART4>; 280 resets = <&ccu RST_BUS_UART4>; 281 dmas = <&dma 18>, <&dma 18>; 282 dma-names = "tx", "rx"; 283 status = "disabled"; 284 }; 285 286 uart5: serial@2501400 { 287 compatible = "snps,dw-apb-uart"; 288 reg = <0x2501400 0x400>; 289 reg-io-width = <4>; 290 reg-shift = <2>; 291 interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&ccu CLK_BUS_UART5>; 293 resets = <&ccu RST_BUS_UART5>; 294 dmas = <&dma 19>, <&dma 19>; 295 dma-names = "tx", "rx"; 296 status = "disabled"; 297 }; 298 299 i2c0: i2c@2502000 { 300 compatible = "allwinner,sun20i-d1-i2c", 301 "allwinner,sun8i-v536-i2c", 302 "allwinner,sun6i-a31-i2c"; 303 reg = <0x2502000 0x400>; 304 interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&ccu CLK_BUS_I2C0>; 306 resets = <&ccu RST_BUS_I2C0>; 307 dmas = <&dma 43>, <&dma 43>; 308 dma-names = "rx", "tx"; 309 status = "disabled"; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 }; 313 314 i2c1: i2c@2502400 { 315 compatible = "allwinner,sun20i-d1-i2c", 316 "allwinner,sun8i-v536-i2c", 317 "allwinner,sun6i-a31-i2c"; 318 reg = <0x2502400 0x400>; 319 interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&ccu CLK_BUS_I2C1>; 321 resets = <&ccu RST_BUS_I2C1>; 322 dmas = <&dma 44>, <&dma 44>; 323 dma-names = "rx", "tx"; 324 status = "disabled"; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 }; 328 329 i2c2: i2c@2502800 { 330 compatible = "allwinner,sun20i-d1-i2c", 331 "allwinner,sun8i-v536-i2c", 332 "allwinner,sun6i-a31-i2c"; 333 reg = <0x2502800 0x400>; 334 interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&ccu CLK_BUS_I2C2>; 336 resets = <&ccu RST_BUS_I2C2>; 337 dmas = <&dma 45>, <&dma 45>; 338 dma-names = "rx", "tx"; 339 status = "disabled"; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 }; 343 344 i2c3: i2c@2502c00 { 345 compatible = "allwinner,sun20i-d1-i2c", 346 "allwinner,sun8i-v536-i2c", 347 "allwinner,sun6i-a31-i2c"; 348 reg = <0x2502c00 0x400>; 349 interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&ccu CLK_BUS_I2C3>; 351 resets = <&ccu RST_BUS_I2C3>; 352 dmas = <&dma 46>, <&dma 46>; 353 dma-names = "rx", "tx"; 354 status = "disabled"; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 }; 358 359 syscon: syscon@3000000 { 360 compatible = "allwinner,sun20i-d1-system-control"; 361 reg = <0x3000000 0x1000>; 362 ranges; 363 #address-cells = <1>; 364 #size-cells = <1>; 365 }; 366 367 dma: dma-controller@3002000 { 368 compatible = "allwinner,sun20i-d1-dma"; 369 reg = <0x3002000 0x1000>; 370 interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 372 clock-names = "bus", "mbus"; 373 resets = <&ccu RST_BUS_DMA>; 374 dma-channels = <16>; 375 dma-requests = <48>; 376 #dma-cells = <1>; 377 }; 378 379 sid: efuse@3006000 { 380 compatible = "allwinner,sun20i-d1-sid"; 381 reg = <0x3006000 0x1000>; 382 #address-cells = <1>; 383 #size-cells = <1>; 384 }; 385 386 crypto: crypto@3040000 { 387 compatible = "allwinner,sun20i-d1-crypto"; 388 reg = <0x3040000 0x800>; 389 interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&ccu CLK_BUS_CE>, 391 <&ccu CLK_CE>, 392 <&ccu CLK_MBUS_CE>, 393 <&rtc CLK_IOSC>; 394 clock-names = "bus", "mod", "ram", "trng"; 395 resets = <&ccu RST_BUS_CE>; 396 }; 397 398 mbus: dram-controller@3102000 { 399 compatible = "allwinner,sun20i-d1-mbus"; 400 reg = <0x3102000 0x1000>, 401 <0x3103000 0x1000>; 402 reg-names = "mbus", "dram"; 403 interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&ccu CLK_MBUS>, 405 <&ccu CLK_DRAM>, 406 <&ccu CLK_BUS_DRAM>; 407 clock-names = "mbus", "dram", "bus"; 408 dma-ranges = <0 0x40000000 0x80000000>; 409 #address-cells = <1>; 410 #size-cells = <1>; 411 #interconnect-cells = <1>; 412 }; 413 414 mmc0: mmc@4020000 { 415 compatible = "allwinner,sun20i-d1-mmc"; 416 reg = <0x4020000 0x1000>; 417 interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 419 clock-names = "ahb", "mmc"; 420 resets = <&ccu RST_BUS_MMC0>; 421 reset-names = "ahb"; 422 cap-sd-highspeed; 423 max-frequency = <150000000>; 424 no-mmc; 425 status = "disabled"; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 }; 429 430 mmc1: mmc@4021000 { 431 compatible = "allwinner,sun20i-d1-mmc"; 432 reg = <0x4021000 0x1000>; 433 interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 435 clock-names = "ahb", "mmc"; 436 resets = <&ccu RST_BUS_MMC1>; 437 reset-names = "ahb"; 438 cap-sd-highspeed; 439 max-frequency = <150000000>; 440 no-mmc; 441 status = "disabled"; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 }; 445 446 mmc2: mmc@4022000 { 447 compatible = "allwinner,sun20i-d1-emmc", 448 "allwinner,sun50i-a100-emmc"; 449 reg = <0x4022000 0x1000>; 450 interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 452 clock-names = "ahb", "mmc"; 453 resets = <&ccu RST_BUS_MMC2>; 454 reset-names = "ahb"; 455 cap-mmc-highspeed; 456 max-frequency = <150000000>; 457 mmc-ddr-1_8v; 458 mmc-ddr-3_3v; 459 no-sd; 460 no-sdio; 461 status = "disabled"; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 }; 465 466 spi0: spi@4025000 { 467 compatible = "allwinner,sun20i-d1-spi", 468 "allwinner,sun50i-r329-spi"; 469 reg = <0x04025000 0x1000>; 470 interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 472 clock-names = "ahb", "mod"; 473 dmas = <&dma 22>, <&dma 22>; 474 dma-names = "rx", "tx"; 475 resets = <&ccu RST_BUS_SPI0>; 476 status = "disabled"; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 }; 480 481 spi1: spi@4026000 { 482 compatible = "allwinner,sun20i-d1-spi-dbi", 483 "allwinner,sun50i-r329-spi-dbi", 484 "allwinner,sun50i-r329-spi"; 485 reg = <0x04026000 0x1000>; 486 interrupts = <SOC_PERIPHERAL_IRQ(16) IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 488 clock-names = "ahb", "mod"; 489 dmas = <&dma 23>, <&dma 23>; 490 dma-names = "rx", "tx"; 491 resets = <&ccu RST_BUS_SPI1>; 492 status = "disabled"; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 }; 496 497 usb_otg: usb@4100000 { 498 compatible = "allwinner,sun20i-d1-musb", 499 "allwinner,sun8i-a33-musb"; 500 reg = <0x4100000 0x400>; 501 interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>; 502 interrupt-names = "mc"; 503 clocks = <&ccu CLK_BUS_OTG>; 504 resets = <&ccu RST_BUS_OTG>; 505 extcon = <&usbphy 0>; 506 phys = <&usbphy 0>; 507 phy-names = "usb"; 508 status = "disabled"; 509 }; 510 511 usbphy: phy@4100400 { 512 compatible = "allwinner,sun20i-d1-usb-phy"; 513 reg = <0x4100400 0x100>, 514 <0x4101800 0x100>, 515 <0x4200800 0x100>; 516 reg-names = "phy_ctrl", 517 "pmu0", 518 "pmu1"; 519 clocks = <&dcxo>, 520 <&dcxo>; 521 clock-names = "usb0_phy", 522 "usb1_phy"; 523 resets = <&ccu RST_USB_PHY0>, 524 <&ccu RST_USB_PHY1>; 525 reset-names = "usb0_reset", 526 "usb1_reset"; 527 status = "disabled"; 528 #phy-cells = <1>; 529 }; 530 531 ehci0: usb@4101000 { 532 compatible = "allwinner,sun20i-d1-ehci", 533 "generic-ehci"; 534 reg = <0x4101000 0x100>; 535 interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&ccu CLK_BUS_OHCI0>, 537 <&ccu CLK_BUS_EHCI0>, 538 <&ccu CLK_USB_OHCI0>; 539 resets = <&ccu RST_BUS_OHCI0>, 540 <&ccu RST_BUS_EHCI0>; 541 phys = <&usbphy 0>; 542 phy-names = "usb"; 543 status = "disabled"; 544 }; 545 546 ohci0: usb@4101400 { 547 compatible = "allwinner,sun20i-d1-ohci", 548 "generic-ohci"; 549 reg = <0x4101400 0x100>; 550 interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&ccu CLK_BUS_OHCI0>, 552 <&ccu CLK_USB_OHCI0>; 553 resets = <&ccu RST_BUS_OHCI0>; 554 phys = <&usbphy 0>; 555 phy-names = "usb"; 556 status = "disabled"; 557 }; 558 559 ehci1: usb@4200000 { 560 compatible = "allwinner,sun20i-d1-ehci", 561 "generic-ehci"; 562 reg = <0x4200000 0x100>; 563 interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&ccu CLK_BUS_OHCI1>, 565 <&ccu CLK_BUS_EHCI1>, 566 <&ccu CLK_USB_OHCI1>; 567 resets = <&ccu RST_BUS_OHCI1>, 568 <&ccu RST_BUS_EHCI1>; 569 phys = <&usbphy 1>; 570 phy-names = "usb"; 571 status = "disabled"; 572 }; 573 574 ohci1: usb@4200400 { 575 compatible = "allwinner,sun20i-d1-ohci", 576 "generic-ohci"; 577 reg = <0x4200400 0x100>; 578 interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&ccu CLK_BUS_OHCI1>, 580 <&ccu CLK_USB_OHCI1>; 581 resets = <&ccu RST_BUS_OHCI1>; 582 phys = <&usbphy 1>; 583 phy-names = "usb"; 584 status = "disabled"; 585 }; 586 587 emac: ethernet@4500000 { 588 compatible = "allwinner,sun20i-d1-emac", 589 "allwinner,sun50i-a64-emac"; 590 reg = <0x4500000 0x10000>; 591 interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>; 592 interrupt-names = "macirq"; 593 clocks = <&ccu CLK_BUS_EMAC>; 594 clock-names = "stmmaceth"; 595 resets = <&ccu RST_BUS_EMAC>; 596 reset-names = "stmmaceth"; 597 syscon = <&syscon>; 598 status = "disabled"; 599 600 mdio: mdio { 601 compatible = "snps,dwmac-mdio"; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 }; 605 }; 606 607 display_clocks: clock-controller@5000000 { 608 compatible = "allwinner,sun20i-d1-de2-clk", 609 "allwinner,sun50i-h5-de2-clk"; 610 reg = <0x5000000 0x10000>; 611 clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; 612 clock-names = "bus", "mod"; 613 resets = <&ccu RST_BUS_DE>; 614 #clock-cells = <1>; 615 #reset-cells = <1>; 616 }; 617 618 mixer0: mixer@5100000 { 619 compatible = "allwinner,sun20i-d1-de2-mixer-0"; 620 reg = <0x5100000 0x100000>; 621 clocks = <&display_clocks CLK_BUS_MIXER0>, 622 <&display_clocks CLK_MIXER0>; 623 clock-names = "bus", "mod"; 624 resets = <&display_clocks RST_MIXER0>; 625 626 ports { 627 #address-cells = <1>; 628 #size-cells = <0>; 629 630 mixer0_out: port@1 { 631 reg = <1>; 632 633 mixer0_out_tcon_top_mixer0: endpoint { 634 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 635 }; 636 }; 637 }; 638 }; 639 640 mixer1: mixer@5200000 { 641 compatible = "allwinner,sun20i-d1-de2-mixer-1"; 642 reg = <0x5200000 0x100000>; 643 clocks = <&display_clocks CLK_BUS_MIXER1>, 644 <&display_clocks CLK_MIXER1>; 645 clock-names = "bus", "mod"; 646 resets = <&display_clocks RST_MIXER1>; 647 648 ports { 649 #address-cells = <1>; 650 #size-cells = <0>; 651 652 mixer1_out: port@1 { 653 reg = <1>; 654 655 mixer1_out_tcon_top_mixer1: endpoint { 656 remote-endpoint = <&tcon_top_mixer1_in_mixer1>; 657 }; 658 }; 659 }; 660 }; 661 662 dsi: dsi@5450000 { 663 compatible = "allwinner,sun20i-d1-mipi-dsi", 664 "allwinner,sun50i-a100-mipi-dsi"; 665 reg = <0x5450000 0x1000>; 666 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&ccu CLK_BUS_MIPI_DSI>, 668 <&tcon_top CLK_TCON_TOP_DSI>; 669 clock-names = "bus", "mod"; 670 resets = <&ccu RST_BUS_MIPI_DSI>; 671 phys = <&dphy>; 672 phy-names = "dphy"; 673 status = "disabled"; 674 675 port { 676 dsi_in_tcon_lcd0: endpoint { 677 remote-endpoint = <&tcon_lcd0_out_dsi>; 678 }; 679 }; 680 }; 681 682 dphy: phy@5451000 { 683 compatible = "allwinner,sun20i-d1-mipi-dphy", 684 "allwinner,sun50i-a100-mipi-dphy"; 685 reg = <0x5451000 0x1000>; 686 interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&ccu CLK_BUS_MIPI_DSI>, 688 <&ccu CLK_MIPI_DSI>; 689 clock-names = "bus", "mod"; 690 resets = <&ccu RST_BUS_MIPI_DSI>; 691 #phy-cells = <0>; 692 }; 693 694 tcon_top: tcon-top@5460000 { 695 compatible = "allwinner,sun20i-d1-tcon-top"; 696 reg = <0x5460000 0x1000>; 697 clocks = <&ccu CLK_BUS_DPSS_TOP>, 698 <&ccu CLK_TCON_TV>, 699 <&ccu CLK_TVE>, 700 <&ccu CLK_TCON_LCD0>; 701 clock-names = "bus", "tcon-tv0", "tve0", "dsi"; 702 clock-output-names = "tcon-top-tv0", "tcon-top-dsi"; 703 resets = <&ccu RST_BUS_DPSS_TOP>; 704 #clock-cells = <1>; 705 706 ports { 707 #address-cells = <1>; 708 #size-cells = <0>; 709 710 tcon_top_mixer0_in: port@0 { 711 reg = <0>; 712 713 tcon_top_mixer0_in_mixer0: endpoint { 714 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 715 }; 716 }; 717 718 tcon_top_mixer0_out: port@1 { 719 reg = <1>; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 723 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { 724 reg = <0>; 725 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; 726 }; 727 728 tcon_top_mixer0_out_tcon_tv0: endpoint@2 { 729 reg = <2>; 730 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; 731 }; 732 }; 733 734 tcon_top_mixer1_in: port@2 { 735 reg = <2>; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 739 tcon_top_mixer1_in_mixer1: endpoint@1 { 740 reg = <1>; 741 remote-endpoint = <&mixer1_out_tcon_top_mixer1>; 742 }; 743 }; 744 745 tcon_top_mixer1_out: port@3 { 746 reg = <3>; 747 #address-cells = <1>; 748 #size-cells = <0>; 749 750 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { 751 reg = <0>; 752 remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>; 753 }; 754 755 tcon_top_mixer1_out_tcon_tv0: endpoint@2 { 756 reg = <2>; 757 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; 758 }; 759 }; 760 761 tcon_top_hdmi_in: port@4 { 762 reg = <4>; 763 764 tcon_top_hdmi_in_tcon_tv0: endpoint { 765 remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>; 766 }; 767 }; 768 769 tcon_top_hdmi_out: port@5 { 770 reg = <5>; 771 }; 772 }; 773 }; 774 775 tcon_lcd0: lcd-controller@5461000 { 776 compatible = "allwinner,sun20i-d1-tcon-lcd"; 777 reg = <0x5461000 0x1000>; 778 interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&ccu CLK_BUS_TCON_LCD0>, 780 <&ccu CLK_TCON_LCD0>; 781 clock-names = "ahb", "tcon-ch0"; 782 clock-output-names = "tcon-pixel-clock"; 783 resets = <&ccu RST_BUS_TCON_LCD0>, 784 <&ccu RST_BUS_LVDS0>; 785 reset-names = "lcd", "lvds"; 786 #clock-cells = <0>; 787 788 ports { 789 #address-cells = <1>; 790 #size-cells = <0>; 791 792 tcon_lcd0_in: port@0 { 793 reg = <0>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 797 tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { 798 reg = <0>; 799 remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; 800 }; 801 802 tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { 803 reg = <1>; 804 remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>; 805 }; 806 }; 807 808 tcon_lcd0_out: port@1 { 809 reg = <1>; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 813 tcon_lcd0_out_dsi: endpoint@1 { 814 reg = <1>; 815 remote-endpoint = <&dsi_in_tcon_lcd0>; 816 }; 817 }; 818 }; 819 }; 820 821 tcon_tv0: lcd-controller@5470000 { 822 compatible = "allwinner,sun20i-d1-tcon-tv"; 823 reg = <0x5470000 0x1000>; 824 interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&ccu CLK_BUS_TCON_TV>, 826 <&tcon_top CLK_TCON_TOP_TV0>; 827 clock-names = "ahb", "tcon-ch1"; 828 resets = <&ccu RST_BUS_TCON_TV>; 829 reset-names = "lcd"; 830 831 ports { 832 #address-cells = <1>; 833 #size-cells = <0>; 834 835 tcon_tv0_in: port@0 { 836 reg = <0>; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 840 tcon_tv0_in_tcon_top_mixer0: endpoint@0 { 841 reg = <0>; 842 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; 843 }; 844 845 tcon_tv0_in_tcon_top_mixer1: endpoint@1 { 846 reg = <1>; 847 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; 848 }; 849 }; 850 851 tcon_tv0_out: port@1 { 852 reg = <1>; 853 854 tcon_tv0_out_tcon_top_hdmi: endpoint { 855 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; 856 }; 857 }; 858 }; 859 }; 860 861 ppu: power-controller@7001000 { 862 compatible = "allwinner,sun20i-d1-ppu"; 863 reg = <0x7001000 0x1000>; 864 clocks = <&r_ccu CLK_BUS_R_PPU>; 865 resets = <&r_ccu RST_BUS_R_PPU>; 866 #power-domain-cells = <1>; 867 }; 868 869 r_ccu: clock-controller@7010000 { 870 compatible = "allwinner,sun20i-d1-r-ccu"; 871 reg = <0x7010000 0x400>; 872 clocks = <&dcxo>, 873 <&rtc CLK_OSC32K>, 874 <&rtc CLK_IOSC>, 875 <&ccu CLK_PLL_PERIPH0_DIV3>; 876 clock-names = "hosc", "losc", "iosc", "pll-periph"; 877 #clock-cells = <1>; 878 #reset-cells = <1>; 879 }; 880 881 rtc: rtc@7090000 { 882 compatible = "allwinner,sun20i-d1-rtc", 883 "allwinner,sun50i-r329-rtc"; 884 reg = <0x7090000 0x400>; 885 interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&r_ccu CLK_BUS_R_RTC>, 887 <&dcxo>, 888 <&r_ccu CLK_R_AHB>; 889 clock-names = "bus", "hosc", "ahb"; 890 #clock-cells = <1>; 891 }; 892 }; 893}; 894