1*062b9b66SKrzysztof Kozlowski// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2077e5f4fSSamuel Holland// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> 3077e5f4fSSamuel Holland 4077e5f4fSSamuel Holland#define SOC_PERIPHERAL_IRQ(nr) (nr + 16) 5077e5f4fSSamuel Holland 6077e5f4fSSamuel Holland#include "sunxi-d1s-t113.dtsi" 7077e5f4fSSamuel Holland 8077e5f4fSSamuel Holland/ { 9077e5f4fSSamuel Holland cpus { 10077e5f4fSSamuel Holland timebase-frequency = <24000000>; 11077e5f4fSSamuel Holland #address-cells = <1>; 12077e5f4fSSamuel Holland #size-cells = <0>; 13077e5f4fSSamuel Holland 14077e5f4fSSamuel Holland cpu0: cpu@0 { 15077e5f4fSSamuel Holland compatible = "thead,c906", "riscv"; 16077e5f4fSSamuel Holland device_type = "cpu"; 17077e5f4fSSamuel Holland reg = <0>; 18077e5f4fSSamuel Holland clocks = <&ccu CLK_RISCV>; 19077e5f4fSSamuel Holland d-cache-block-size = <64>; 20077e5f4fSSamuel Holland d-cache-sets = <256>; 21077e5f4fSSamuel Holland d-cache-size = <32768>; 22077e5f4fSSamuel Holland i-cache-block-size = <64>; 23077e5f4fSSamuel Holland i-cache-sets = <128>; 24077e5f4fSSamuel Holland i-cache-size = <32768>; 25077e5f4fSSamuel Holland mmu-type = "riscv,sv39"; 26077e5f4fSSamuel Holland operating-points-v2 = <&opp_table_cpu>; 27077e5f4fSSamuel Holland riscv,isa = "rv64imafdc"; 28077e5f4fSSamuel Holland #cooling-cells = <2>; 29077e5f4fSSamuel Holland 30077e5f4fSSamuel Holland cpu0_intc: interrupt-controller { 31077e5f4fSSamuel Holland compatible = "riscv,cpu-intc"; 32077e5f4fSSamuel Holland interrupt-controller; 33077e5f4fSSamuel Holland #address-cells = <0>; 34077e5f4fSSamuel Holland #interrupt-cells = <1>; 35077e5f4fSSamuel Holland }; 36077e5f4fSSamuel Holland }; 37077e5f4fSSamuel Holland }; 38077e5f4fSSamuel Holland 39077e5f4fSSamuel Holland opp_table_cpu: opp-table-cpu { 40077e5f4fSSamuel Holland compatible = "operating-points-v2"; 41077e5f4fSSamuel Holland 42077e5f4fSSamuel Holland opp-408000000 { 43077e5f4fSSamuel Holland opp-hz = /bits/ 64 <408000000>; 44077e5f4fSSamuel Holland opp-microvolt = <900000 900000 1100000>; 45077e5f4fSSamuel Holland }; 46077e5f4fSSamuel Holland 47077e5f4fSSamuel Holland opp-1080000000 { 48077e5f4fSSamuel Holland opp-hz = /bits/ 64 <1008000000>; 49077e5f4fSSamuel Holland opp-microvolt = <900000 900000 1100000>; 50077e5f4fSSamuel Holland }; 51077e5f4fSSamuel Holland }; 52077e5f4fSSamuel Holland 53077e5f4fSSamuel Holland soc { 54077e5f4fSSamuel Holland interrupt-parent = <&plic>; 55077e5f4fSSamuel Holland 56077e5f4fSSamuel Holland riscv_wdt: watchdog@6011000 { 57077e5f4fSSamuel Holland compatible = "allwinner,sun20i-d1-wdt"; 58077e5f4fSSamuel Holland reg = <0x6011000 0x20>; 59077e5f4fSSamuel Holland interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>; 60077e5f4fSSamuel Holland clocks = <&dcxo>, <&rtc CLK_OSC32K>; 61077e5f4fSSamuel Holland clock-names = "hosc", "losc"; 62077e5f4fSSamuel Holland }; 63077e5f4fSSamuel Holland 64077e5f4fSSamuel Holland plic: interrupt-controller@10000000 { 65077e5f4fSSamuel Holland compatible = "allwinner,sun20i-d1-plic", 66077e5f4fSSamuel Holland "thead,c900-plic"; 67077e5f4fSSamuel Holland reg = <0x10000000 0x4000000>; 68077e5f4fSSamuel Holland interrupts-extended = <&cpu0_intc 11>, 69077e5f4fSSamuel Holland <&cpu0_intc 9>; 70077e5f4fSSamuel Holland interrupt-controller; 71077e5f4fSSamuel Holland riscv,ndev = <175>; 72077e5f4fSSamuel Holland #address-cells = <0>; 73077e5f4fSSamuel Holland #interrupt-cells = <2>; 74077e5f4fSSamuel Holland }; 75077e5f4fSSamuel Holland }; 76077e5f4fSSamuel Holland}; 77