1*077e5f4fSSamuel Holland// SPDX-License-Identifier: (GPL-2.0+ or MIT) 2*077e5f4fSSamuel Holland// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> 3*077e5f4fSSamuel Holland 4*077e5f4fSSamuel Holland#include "sun20i-d1s.dtsi" 5*077e5f4fSSamuel Holland#include "sunxi-d1-t113.dtsi" 6*077e5f4fSSamuel Holland 7*077e5f4fSSamuel Holland/ { 8*077e5f4fSSamuel Holland soc { 9*077e5f4fSSamuel Holland lradc: keys@2009800 { 10*077e5f4fSSamuel Holland compatible = "allwinner,sun20i-d1-lradc", 11*077e5f4fSSamuel Holland "allwinner,sun50i-r329-lradc"; 12*077e5f4fSSamuel Holland reg = <0x2009800 0x400>; 13*077e5f4fSSamuel Holland interrupts = <SOC_PERIPHERAL_IRQ(61) IRQ_TYPE_LEVEL_HIGH>; 14*077e5f4fSSamuel Holland clocks = <&ccu CLK_BUS_LRADC>; 15*077e5f4fSSamuel Holland resets = <&ccu RST_BUS_LRADC>; 16*077e5f4fSSamuel Holland status = "disabled"; 17*077e5f4fSSamuel Holland }; 18*077e5f4fSSamuel Holland 19*077e5f4fSSamuel Holland i2s0: i2s@2032000 { 20*077e5f4fSSamuel Holland compatible = "allwinner,sun20i-d1-i2s", 21*077e5f4fSSamuel Holland "allwinner,sun50i-r329-i2s"; 22*077e5f4fSSamuel Holland reg = <0x2032000 0x1000>; 23*077e5f4fSSamuel Holland interrupts = <SOC_PERIPHERAL_IRQ(26) IRQ_TYPE_LEVEL_HIGH>; 24*077e5f4fSSamuel Holland clocks = <&ccu CLK_BUS_I2S0>, 25*077e5f4fSSamuel Holland <&ccu CLK_I2S0>; 26*077e5f4fSSamuel Holland clock-names = "apb", "mod"; 27*077e5f4fSSamuel Holland resets = <&ccu RST_BUS_I2S0>; 28*077e5f4fSSamuel Holland dmas = <&dma 3>, <&dma 3>; 29*077e5f4fSSamuel Holland dma-names = "rx", "tx"; 30*077e5f4fSSamuel Holland status = "disabled"; 31*077e5f4fSSamuel Holland #sound-dai-cells = <0>; 32*077e5f4fSSamuel Holland }; 33*077e5f4fSSamuel Holland }; 34*077e5f4fSSamuel Holland}; 35*077e5f4fSSamuel Holland 36*077e5f4fSSamuel Holland&pio { 37*077e5f4fSSamuel Holland /omit-if-no-ref/ 38*077e5f4fSSamuel Holland dmic_pb11_d0_pin: dmic-pb11-d0-pin { 39*077e5f4fSSamuel Holland pins = "PB11"; 40*077e5f4fSSamuel Holland function = "dmic"; 41*077e5f4fSSamuel Holland }; 42*077e5f4fSSamuel Holland 43*077e5f4fSSamuel Holland /omit-if-no-ref/ 44*077e5f4fSSamuel Holland dmic_pe17_clk_pin: dmic-pe17-clk-pin { 45*077e5f4fSSamuel Holland pins = "PE17"; 46*077e5f4fSSamuel Holland function = "dmic"; 47*077e5f4fSSamuel Holland }; 48*077e5f4fSSamuel Holland 49*077e5f4fSSamuel Holland /omit-if-no-ref/ 50*077e5f4fSSamuel Holland i2c0_pb10_pins: i2c0-pb10-pins { 51*077e5f4fSSamuel Holland pins = "PB10", "PB11"; 52*077e5f4fSSamuel Holland function = "i2c0"; 53*077e5f4fSSamuel Holland }; 54*077e5f4fSSamuel Holland 55*077e5f4fSSamuel Holland /omit-if-no-ref/ 56*077e5f4fSSamuel Holland i2c2_pb0_pins: i2c2-pb0-pins { 57*077e5f4fSSamuel Holland pins = "PB0", "PB1"; 58*077e5f4fSSamuel Holland function = "i2c2"; 59*077e5f4fSSamuel Holland }; 60*077e5f4fSSamuel Holland 61*077e5f4fSSamuel Holland /omit-if-no-ref/ 62*077e5f4fSSamuel Holland uart0_pb8_pins: uart0-pb8-pins { 63*077e5f4fSSamuel Holland pins = "PB8", "PB9"; 64*077e5f4fSSamuel Holland function = "uart0"; 65*077e5f4fSSamuel Holland }; 66*077e5f4fSSamuel Holland}; 67