1*02b8a3d1SWolfgang Grandegger/* 2*02b8a3d1SWolfgang Grandegger * TQM8548 Device Tree Source 3*02b8a3d1SWolfgang Grandegger * 4*02b8a3d1SWolfgang Grandegger * Copyright 2006 Freescale Semiconductor Inc. 5*02b8a3d1SWolfgang Grandegger * Copyright 2008 Wolfgang Grandegger <wg@denx.de> 6*02b8a3d1SWolfgang Grandegger * 7*02b8a3d1SWolfgang Grandegger * This program is free software; you can redistribute it and/or modify it 8*02b8a3d1SWolfgang Grandegger * under the terms of the GNU General Public License as published by the 9*02b8a3d1SWolfgang Grandegger * Free Software Foundation; either version 2 of the License, or (at your 10*02b8a3d1SWolfgang Grandegger * option) any later version. 11*02b8a3d1SWolfgang Grandegger */ 12*02b8a3d1SWolfgang Grandegger 13*02b8a3d1SWolfgang Grandegger/dts-v1/; 14*02b8a3d1SWolfgang Grandegger 15*02b8a3d1SWolfgang Grandegger/ { 16*02b8a3d1SWolfgang Grandegger model = "tqc,tqm8548"; 17*02b8a3d1SWolfgang Grandegger compatible = "tqc,tqm8548"; 18*02b8a3d1SWolfgang Grandegger #address-cells = <1>; 19*02b8a3d1SWolfgang Grandegger #size-cells = <1>; 20*02b8a3d1SWolfgang Grandegger 21*02b8a3d1SWolfgang Grandegger aliases { 22*02b8a3d1SWolfgang Grandegger ethernet0 = &enet0; 23*02b8a3d1SWolfgang Grandegger ethernet1 = &enet1; 24*02b8a3d1SWolfgang Grandegger ethernet2 = &enet2; 25*02b8a3d1SWolfgang Grandegger ethernet3 = &enet3; 26*02b8a3d1SWolfgang Grandegger 27*02b8a3d1SWolfgang Grandegger serial0 = &serial0; 28*02b8a3d1SWolfgang Grandegger serial1 = &serial1; 29*02b8a3d1SWolfgang Grandegger pci0 = &pci0; 30*02b8a3d1SWolfgang Grandegger pci1 = &pci1; 31*02b8a3d1SWolfgang Grandegger }; 32*02b8a3d1SWolfgang Grandegger 33*02b8a3d1SWolfgang Grandegger cpus { 34*02b8a3d1SWolfgang Grandegger #address-cells = <1>; 35*02b8a3d1SWolfgang Grandegger #size-cells = <0>; 36*02b8a3d1SWolfgang Grandegger 37*02b8a3d1SWolfgang Grandegger PowerPC,8548@0 { 38*02b8a3d1SWolfgang Grandegger device_type = "cpu"; 39*02b8a3d1SWolfgang Grandegger reg = <0>; 40*02b8a3d1SWolfgang Grandegger d-cache-line-size = <32>; // 32 bytes 41*02b8a3d1SWolfgang Grandegger i-cache-line-size = <32>; // 32 bytes 42*02b8a3d1SWolfgang Grandegger d-cache-size = <0x8000>; // L1, 32K 43*02b8a3d1SWolfgang Grandegger i-cache-size = <0x8000>; // L1, 32K 44*02b8a3d1SWolfgang Grandegger next-level-cache = <&L2>; 45*02b8a3d1SWolfgang Grandegger }; 46*02b8a3d1SWolfgang Grandegger }; 47*02b8a3d1SWolfgang Grandegger 48*02b8a3d1SWolfgang Grandegger memory { 49*02b8a3d1SWolfgang Grandegger device_type = "memory"; 50*02b8a3d1SWolfgang Grandegger reg = <0x00000000 0x00000000>; // Filled in by U-Boot 51*02b8a3d1SWolfgang Grandegger }; 52*02b8a3d1SWolfgang Grandegger 53*02b8a3d1SWolfgang Grandegger soc8548@a0000000 { 54*02b8a3d1SWolfgang Grandegger #address-cells = <1>; 55*02b8a3d1SWolfgang Grandegger #size-cells = <1>; 56*02b8a3d1SWolfgang Grandegger device_type = "soc"; 57*02b8a3d1SWolfgang Grandegger ranges = <0x0 0xa0000000 0x100000>; 58*02b8a3d1SWolfgang Grandegger reg = <0xa0000000 0x1000>; // CCSRBAR 59*02b8a3d1SWolfgang Grandegger bus-frequency = <0>; 60*02b8a3d1SWolfgang Grandegger 61*02b8a3d1SWolfgang Grandegger memory-controller@2000 { 62*02b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-memory-controller"; 63*02b8a3d1SWolfgang Grandegger reg = <0x2000 0x1000>; 64*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 65*02b8a3d1SWolfgang Grandegger interrupts = <18 2>; 66*02b8a3d1SWolfgang Grandegger }; 67*02b8a3d1SWolfgang Grandegger 68*02b8a3d1SWolfgang Grandegger L2: l2-cache-controller@20000 { 69*02b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-l2-cache-controller"; 70*02b8a3d1SWolfgang Grandegger reg = <0x20000 0x1000>; 71*02b8a3d1SWolfgang Grandegger cache-line-size = <32>; // 32 bytes 72*02b8a3d1SWolfgang Grandegger cache-size = <0x80000>; // L2, 512K 73*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 74*02b8a3d1SWolfgang Grandegger interrupts = <16 2>; 75*02b8a3d1SWolfgang Grandegger }; 76*02b8a3d1SWolfgang Grandegger 77*02b8a3d1SWolfgang Grandegger i2c@3000 { 78*02b8a3d1SWolfgang Grandegger #address-cells = <1>; 79*02b8a3d1SWolfgang Grandegger #size-cells = <0>; 80*02b8a3d1SWolfgang Grandegger cell-index = <0>; 81*02b8a3d1SWolfgang Grandegger compatible = "fsl-i2c"; 82*02b8a3d1SWolfgang Grandegger reg = <0x3000 0x100>; 83*02b8a3d1SWolfgang Grandegger interrupts = <43 2>; 84*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 85*02b8a3d1SWolfgang Grandegger dfsrr; 86*02b8a3d1SWolfgang Grandegger }; 87*02b8a3d1SWolfgang Grandegger 88*02b8a3d1SWolfgang Grandegger i2c@3100 { 89*02b8a3d1SWolfgang Grandegger #address-cells = <1>; 90*02b8a3d1SWolfgang Grandegger #size-cells = <0>; 91*02b8a3d1SWolfgang Grandegger cell-index = <1>; 92*02b8a3d1SWolfgang Grandegger compatible = "fsl-i2c"; 93*02b8a3d1SWolfgang Grandegger reg = <0x3100 0x100>; 94*02b8a3d1SWolfgang Grandegger interrupts = <43 2>; 95*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 96*02b8a3d1SWolfgang Grandegger dfsrr; 97*02b8a3d1SWolfgang Grandegger }; 98*02b8a3d1SWolfgang Grandegger 99*02b8a3d1SWolfgang Grandegger mdio@24520 { 100*02b8a3d1SWolfgang Grandegger #address-cells = <1>; 101*02b8a3d1SWolfgang Grandegger #size-cells = <0>; 102*02b8a3d1SWolfgang Grandegger compatible = "fsl,gianfar-mdio"; 103*02b8a3d1SWolfgang Grandegger reg = <0x24520 0x20>; 104*02b8a3d1SWolfgang Grandegger 105*02b8a3d1SWolfgang Grandegger phy1: ethernet-phy@0 { 106*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 107*02b8a3d1SWolfgang Grandegger interrupts = <8 1>; 108*02b8a3d1SWolfgang Grandegger reg = <1>; 109*02b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 110*02b8a3d1SWolfgang Grandegger }; 111*02b8a3d1SWolfgang Grandegger phy2: ethernet-phy@1 { 112*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 113*02b8a3d1SWolfgang Grandegger interrupts = <8 1>; 114*02b8a3d1SWolfgang Grandegger reg = <2>; 115*02b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 116*02b8a3d1SWolfgang Grandegger }; 117*02b8a3d1SWolfgang Grandegger phy3: ethernet-phy@3 { 118*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 119*02b8a3d1SWolfgang Grandegger interrupts = <8 1>; 120*02b8a3d1SWolfgang Grandegger reg = <3>; 121*02b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 122*02b8a3d1SWolfgang Grandegger }; 123*02b8a3d1SWolfgang Grandegger phy4: ethernet-phy@4 { 124*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 125*02b8a3d1SWolfgang Grandegger interrupts = <8 1>; 126*02b8a3d1SWolfgang Grandegger reg = <4>; 127*02b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 128*02b8a3d1SWolfgang Grandegger }; 129*02b8a3d1SWolfgang Grandegger phy5: ethernet-phy@5 { 130*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 131*02b8a3d1SWolfgang Grandegger interrupts = <8 1>; 132*02b8a3d1SWolfgang Grandegger reg = <5>; 133*02b8a3d1SWolfgang Grandegger device_type = "ethernet-phy"; 134*02b8a3d1SWolfgang Grandegger }; 135*02b8a3d1SWolfgang Grandegger }; 136*02b8a3d1SWolfgang Grandegger 137*02b8a3d1SWolfgang Grandegger enet0: ethernet@24000 { 138*02b8a3d1SWolfgang Grandegger cell-index = <0>; 139*02b8a3d1SWolfgang Grandegger device_type = "network"; 140*02b8a3d1SWolfgang Grandegger model = "eTSEC"; 141*02b8a3d1SWolfgang Grandegger compatible = "gianfar"; 142*02b8a3d1SWolfgang Grandegger reg = <0x24000 0x1000>; 143*02b8a3d1SWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 144*02b8a3d1SWolfgang Grandegger interrupts = <29 2 30 2 34 2>; 145*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 146*02b8a3d1SWolfgang Grandegger phy-handle = <&phy2>; 147*02b8a3d1SWolfgang Grandegger }; 148*02b8a3d1SWolfgang Grandegger 149*02b8a3d1SWolfgang Grandegger enet1: ethernet@25000 { 150*02b8a3d1SWolfgang Grandegger cell-index = <1>; 151*02b8a3d1SWolfgang Grandegger device_type = "network"; 152*02b8a3d1SWolfgang Grandegger model = "eTSEC"; 153*02b8a3d1SWolfgang Grandegger compatible = "gianfar"; 154*02b8a3d1SWolfgang Grandegger reg = <0x25000 0x1000>; 155*02b8a3d1SWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 156*02b8a3d1SWolfgang Grandegger interrupts = <35 2 36 2 40 2>; 157*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 158*02b8a3d1SWolfgang Grandegger phy-handle = <&phy1>; 159*02b8a3d1SWolfgang Grandegger }; 160*02b8a3d1SWolfgang Grandegger 161*02b8a3d1SWolfgang Grandegger enet2: ethernet@26000 { 162*02b8a3d1SWolfgang Grandegger cell-index = <2>; 163*02b8a3d1SWolfgang Grandegger device_type = "network"; 164*02b8a3d1SWolfgang Grandegger model = "eTSEC"; 165*02b8a3d1SWolfgang Grandegger compatible = "gianfar"; 166*02b8a3d1SWolfgang Grandegger reg = <0x26000 0x1000>; 167*02b8a3d1SWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 168*02b8a3d1SWolfgang Grandegger interrupts = <31 2 32 2 33 2>; 169*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 170*02b8a3d1SWolfgang Grandegger phy-handle = <&phy3>; 171*02b8a3d1SWolfgang Grandegger }; 172*02b8a3d1SWolfgang Grandegger 173*02b8a3d1SWolfgang Grandegger enet3: ethernet@27000 { 174*02b8a3d1SWolfgang Grandegger cell-index = <3>; 175*02b8a3d1SWolfgang Grandegger device_type = "network"; 176*02b8a3d1SWolfgang Grandegger model = "eTSEC"; 177*02b8a3d1SWolfgang Grandegger compatible = "gianfar"; 178*02b8a3d1SWolfgang Grandegger reg = <0x27000 0x1000>; 179*02b8a3d1SWolfgang Grandegger local-mac-address = [ 00 00 00 00 00 00 ]; 180*02b8a3d1SWolfgang Grandegger interrupts = <37 2 38 2 39 2>; 181*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 182*02b8a3d1SWolfgang Grandegger phy-handle = <&phy4>; 183*02b8a3d1SWolfgang Grandegger }; 184*02b8a3d1SWolfgang Grandegger 185*02b8a3d1SWolfgang Grandegger serial0: serial@4500 { 186*02b8a3d1SWolfgang Grandegger cell-index = <0>; 187*02b8a3d1SWolfgang Grandegger device_type = "serial"; 188*02b8a3d1SWolfgang Grandegger compatible = "ns16550"; 189*02b8a3d1SWolfgang Grandegger reg = <0x4500 0x100>; // reg base, size 190*02b8a3d1SWolfgang Grandegger clock-frequency = <0>; // should we fill in in uboot? 191*02b8a3d1SWolfgang Grandegger current-speed = <115200>; 192*02b8a3d1SWolfgang Grandegger interrupts = <42 2>; 193*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 194*02b8a3d1SWolfgang Grandegger }; 195*02b8a3d1SWolfgang Grandegger 196*02b8a3d1SWolfgang Grandegger serial1: serial@4600 { 197*02b8a3d1SWolfgang Grandegger cell-index = <1>; 198*02b8a3d1SWolfgang Grandegger device_type = "serial"; 199*02b8a3d1SWolfgang Grandegger compatible = "ns16550"; 200*02b8a3d1SWolfgang Grandegger reg = <0x4600 0x100>; // reg base, size 201*02b8a3d1SWolfgang Grandegger clock-frequency = <0>; // should we fill in in uboot? 202*02b8a3d1SWolfgang Grandegger current-speed = <115200>; 203*02b8a3d1SWolfgang Grandegger interrupts = <42 2>; 204*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 205*02b8a3d1SWolfgang Grandegger }; 206*02b8a3d1SWolfgang Grandegger 207*02b8a3d1SWolfgang Grandegger global-utilities@e0000 { // global utilities reg 208*02b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-guts"; 209*02b8a3d1SWolfgang Grandegger reg = <0xe0000 0x1000>; 210*02b8a3d1SWolfgang Grandegger fsl,has-rstcr; 211*02b8a3d1SWolfgang Grandegger }; 212*02b8a3d1SWolfgang Grandegger 213*02b8a3d1SWolfgang Grandegger mpic: pic@40000 { 214*02b8a3d1SWolfgang Grandegger interrupt-controller; 215*02b8a3d1SWolfgang Grandegger #address-cells = <0>; 216*02b8a3d1SWolfgang Grandegger #interrupt-cells = <2>; 217*02b8a3d1SWolfgang Grandegger reg = <0x40000 0x40000>; 218*02b8a3d1SWolfgang Grandegger compatible = "chrp,open-pic"; 219*02b8a3d1SWolfgang Grandegger device_type = "open-pic"; 220*02b8a3d1SWolfgang Grandegger }; 221*02b8a3d1SWolfgang Grandegger }; 222*02b8a3d1SWolfgang Grandegger 223*02b8a3d1SWolfgang Grandegger localbus@a0005000 { 224*02b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", 225*02b8a3d1SWolfgang Grandegger "simple-bus"; 226*02b8a3d1SWolfgang Grandegger #address-cells = <2>; 227*02b8a3d1SWolfgang Grandegger #size-cells = <1>; 228*02b8a3d1SWolfgang Grandegger reg = <0xa0005000 0x100>; // BRx, ORx, etc. 229*02b8a3d1SWolfgang Grandegger 230*02b8a3d1SWolfgang Grandegger ranges = < 231*02b8a3d1SWolfgang Grandegger 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1 232*02b8a3d1SWolfgang Grandegger 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0 233*02b8a3d1SWolfgang Grandegger 2 0x0 0xa3000000 0x00008000 // CAN (2 x i82527) 234*02b8a3d1SWolfgang Grandegger 3 0x0 0xa3010000 0x00008000 // NAND FLASH 235*02b8a3d1SWolfgang Grandegger 236*02b8a3d1SWolfgang Grandegger >; 237*02b8a3d1SWolfgang Grandegger 238*02b8a3d1SWolfgang Grandegger flash@1,0 { 239*02b8a3d1SWolfgang Grandegger #address-cells = <1>; 240*02b8a3d1SWolfgang Grandegger #size-cells = <1>; 241*02b8a3d1SWolfgang Grandegger compatible = "cfi-flash"; 242*02b8a3d1SWolfgang Grandegger reg = <1 0x0 0x8000000>; 243*02b8a3d1SWolfgang Grandegger bank-width = <4>; 244*02b8a3d1SWolfgang Grandegger device-width = <1>; 245*02b8a3d1SWolfgang Grandegger 246*02b8a3d1SWolfgang Grandegger partition@0 { 247*02b8a3d1SWolfgang Grandegger label = "kernel"; 248*02b8a3d1SWolfgang Grandegger reg = <0x00000000 0x00200000>; 249*02b8a3d1SWolfgang Grandegger }; 250*02b8a3d1SWolfgang Grandegger partition@200000 { 251*02b8a3d1SWolfgang Grandegger label = "root"; 252*02b8a3d1SWolfgang Grandegger reg = <0x00200000 0x00300000>; 253*02b8a3d1SWolfgang Grandegger }; 254*02b8a3d1SWolfgang Grandegger partition@500000 { 255*02b8a3d1SWolfgang Grandegger label = "user"; 256*02b8a3d1SWolfgang Grandegger reg = <0x00500000 0x07a00000>; 257*02b8a3d1SWolfgang Grandegger }; 258*02b8a3d1SWolfgang Grandegger partition@7f00000 { 259*02b8a3d1SWolfgang Grandegger label = "env1"; 260*02b8a3d1SWolfgang Grandegger reg = <0x07f00000 0x00040000>; 261*02b8a3d1SWolfgang Grandegger }; 262*02b8a3d1SWolfgang Grandegger partition@7f40000 { 263*02b8a3d1SWolfgang Grandegger label = "env2"; 264*02b8a3d1SWolfgang Grandegger reg = <0x07f40000 0x00040000>; 265*02b8a3d1SWolfgang Grandegger }; 266*02b8a3d1SWolfgang Grandegger partition@7f80000 { 267*02b8a3d1SWolfgang Grandegger label = "u-boot"; 268*02b8a3d1SWolfgang Grandegger reg = <0x07f80000 0x00080000>; 269*02b8a3d1SWolfgang Grandegger read-only; 270*02b8a3d1SWolfgang Grandegger }; 271*02b8a3d1SWolfgang Grandegger }; 272*02b8a3d1SWolfgang Grandegger 273*02b8a3d1SWolfgang Grandegger /* Note: CAN support needs be enabled in U-Boot */ 274*02b8a3d1SWolfgang Grandegger can0@2,0 { 275*02b8a3d1SWolfgang Grandegger compatible = "intel,82527"; // Bosch CC770 276*02b8a3d1SWolfgang Grandegger reg = <2 0x0 0x100>; 277*02b8a3d1SWolfgang Grandegger interrupts = <4 0>; 278*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 279*02b8a3d1SWolfgang Grandegger }; 280*02b8a3d1SWolfgang Grandegger 281*02b8a3d1SWolfgang Grandegger can1@2,100 { 282*02b8a3d1SWolfgang Grandegger compatible = "intel,82527"; // Bosch CC770 283*02b8a3d1SWolfgang Grandegger reg = <2 0x100 0x100>; 284*02b8a3d1SWolfgang Grandegger interrupts = <4 0>; 285*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 286*02b8a3d1SWolfgang Grandegger }; 287*02b8a3d1SWolfgang Grandegger 288*02b8a3d1SWolfgang Grandegger /* Note: NAND support needs to be enabled in U-Boot */ 289*02b8a3d1SWolfgang Grandegger upm@3,0 { 290*02b8a3d1SWolfgang Grandegger #address-cells = <0>; 291*02b8a3d1SWolfgang Grandegger #size-cells = <0>; 292*02b8a3d1SWolfgang Grandegger compatible = "fsl,upm-nand"; 293*02b8a3d1SWolfgang Grandegger reg = <3 0x0 0x800>; 294*02b8a3d1SWolfgang Grandegger fsl,upm-addr-offset = <0x10>; 295*02b8a3d1SWolfgang Grandegger fsl,upm-cmd-offset = <0x08>; 296*02b8a3d1SWolfgang Grandegger chip-delay = <25>; // in micro-seconds 297*02b8a3d1SWolfgang Grandegger 298*02b8a3d1SWolfgang Grandegger nand@0 { 299*02b8a3d1SWolfgang Grandegger #address-cells = <1>; 300*02b8a3d1SWolfgang Grandegger #size-cells = <1>; 301*02b8a3d1SWolfgang Grandegger 302*02b8a3d1SWolfgang Grandegger partition@0 { 303*02b8a3d1SWolfgang Grandegger label = "fs"; 304*02b8a3d1SWolfgang Grandegger reg = <0x00000000 0x01000000>; 305*02b8a3d1SWolfgang Grandegger }; 306*02b8a3d1SWolfgang Grandegger }; 307*02b8a3d1SWolfgang Grandegger }; 308*02b8a3d1SWolfgang Grandegger }; 309*02b8a3d1SWolfgang Grandegger 310*02b8a3d1SWolfgang Grandegger pci0: pci@a0008000 { 311*02b8a3d1SWolfgang Grandegger cell-index = <0>; 312*02b8a3d1SWolfgang Grandegger #interrupt-cells = <1>; 313*02b8a3d1SWolfgang Grandegger #size-cells = <2>; 314*02b8a3d1SWolfgang Grandegger #address-cells = <3>; 315*02b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 316*02b8a3d1SWolfgang Grandegger device_type = "pci"; 317*02b8a3d1SWolfgang Grandegger reg = <0xa0008000 0x1000>; 318*02b8a3d1SWolfgang Grandegger clock-frequency = <33333333>; 319*02b8a3d1SWolfgang Grandegger interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 320*02b8a3d1SWolfgang Grandegger interrupt-map = < 321*02b8a3d1SWolfgang Grandegger /* IDSEL 28 */ 322*02b8a3d1SWolfgang Grandegger 0xe000 0 0 1 &mpic 2 1 323*02b8a3d1SWolfgang Grandegger 0xe000 0 0 2 &mpic 3 1>; 324*02b8a3d1SWolfgang Grandegger 325*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 326*02b8a3d1SWolfgang Grandegger interrupts = <24 2>; 327*02b8a3d1SWolfgang Grandegger bus-range = <0 0>; 328*02b8a3d1SWolfgang Grandegger ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 329*02b8a3d1SWolfgang Grandegger 0x01000000 0 0x00000000 0xa2000000 0 0x01000000>; 330*02b8a3d1SWolfgang Grandegger }; 331*02b8a3d1SWolfgang Grandegger 332*02b8a3d1SWolfgang Grandegger pci1: pcie@a000a000 { 333*02b8a3d1SWolfgang Grandegger cell-index = <2>; 334*02b8a3d1SWolfgang Grandegger interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 335*02b8a3d1SWolfgang Grandegger interrupt-map = < 336*02b8a3d1SWolfgang Grandegger /* IDSEL 0x0 (PEX) */ 337*02b8a3d1SWolfgang Grandegger 0x00000 0 0 1 &mpic 0 1 338*02b8a3d1SWolfgang Grandegger 0x00000 0 0 2 &mpic 1 1 339*02b8a3d1SWolfgang Grandegger 0x00000 0 0 3 &mpic 2 1 340*02b8a3d1SWolfgang Grandegger 0x00000 0 0 4 &mpic 3 1>; 341*02b8a3d1SWolfgang Grandegger 342*02b8a3d1SWolfgang Grandegger interrupt-parent = <&mpic>; 343*02b8a3d1SWolfgang Grandegger interrupts = <26 2>; 344*02b8a3d1SWolfgang Grandegger bus-range = <0 0xff>; 345*02b8a3d1SWolfgang Grandegger ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000 346*02b8a3d1SWolfgang Grandegger 0x01000000 0 0x00000000 0xaf000000 0 0x08000000>; 347*02b8a3d1SWolfgang Grandegger clock-frequency = <33333333>; 348*02b8a3d1SWolfgang Grandegger #interrupt-cells = <1>; 349*02b8a3d1SWolfgang Grandegger #size-cells = <2>; 350*02b8a3d1SWolfgang Grandegger #address-cells = <3>; 351*02b8a3d1SWolfgang Grandegger reg = <0xa000a000 0x1000>; 352*02b8a3d1SWolfgang Grandegger compatible = "fsl,mpc8548-pcie"; 353*02b8a3d1SWolfgang Grandegger device_type = "pci"; 354*02b8a3d1SWolfgang Grandegger pcie@0 { 355*02b8a3d1SWolfgang Grandegger reg = <0 0 0 0 0>; 356*02b8a3d1SWolfgang Grandegger #size-cells = <2>; 357*02b8a3d1SWolfgang Grandegger #address-cells = <3>; 358*02b8a3d1SWolfgang Grandegger device_type = "pci"; 359*02b8a3d1SWolfgang Grandegger ranges = <0x02000000 0 0xb0000000 0x02000000 0 360*02b8a3d1SWolfgang Grandegger 0xb0000000 0 0x10000000 361*02b8a3d1SWolfgang Grandegger 0x01000000 0 0x00000000 0x01000000 0 362*02b8a3d1SWolfgang Grandegger 0x00000000 0 0x08000000>; 363*02b8a3d1SWolfgang Grandegger }; 364*02b8a3d1SWolfgang Grandegger }; 365*02b8a3d1SWolfgang Grandegger}; 366