1/* 2 * MPC8313E RDB Device Tree Source 3 * 4 * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/ { 15 model = "MPC8313ERDB"; 16 compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 aliases { 21 ethernet0 = &enet0; 22 ethernet1 = &enet1; 23 serial0 = &serial0; 24 serial1 = &serial1; 25 pci0 = &pci0; 26 }; 27 28 cpus { 29 #address-cells = <1>; 30 #size-cells = <0>; 31 32 PowerPC,8313@0 { 33 device_type = "cpu"; 34 reg = <0x0>; 35 d-cache-line-size = <32>; 36 i-cache-line-size = <32>; 37 d-cache-size = <16384>; 38 i-cache-size = <16384>; 39 timebase-frequency = <0>; // from bootloader 40 bus-frequency = <0>; // from bootloader 41 clock-frequency = <0>; // from bootloader 42 }; 43 }; 44 45 memory { 46 device_type = "memory"; 47 reg = <0x00000000 0x08000000>; // 128MB at 0 48 }; 49 50 localbus@e0005000 { 51 #address-cells = <2>; 52 #size-cells = <1>; 53 compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus"; 54 reg = <0xe0005000 0x1000>; 55 interrupts = <77 0x8>; 56 interrupt-parent = <&ipic>; 57 58 // CS0 and CS1 are swapped when 59 // booting from nand, but the 60 // addresses are the same. 61 ranges = <0x0 0x0 0xfe000000 0x00800000 62 0x1 0x0 0xe2800000 0x00008000 63 0x2 0x0 0xf0000000 0x00020000 64 0x3 0x0 0xfa000000 0x00008000>; 65 66 flash@0,0 { 67 #address-cells = <1>; 68 #size-cells = <1>; 69 compatible = "cfi-flash"; 70 reg = <0x0 0x0 0x800000>; 71 bank-width = <2>; 72 device-width = <1>; 73 }; 74 75 nand@1,0 { 76 #address-cells = <1>; 77 #size-cells = <1>; 78 compatible = "fsl,mpc8313-fcm-nand", 79 "fsl,elbc-fcm-nand"; 80 reg = <0x1 0x0 0x2000>; 81 82 u-boot@0 { 83 reg = <0x0 0x100000>; 84 read-only; 85 }; 86 87 kernel@100000 { 88 reg = <0x100000 0x300000>; 89 }; 90 91 fs@400000 { 92 reg = <0x400000 0x1c00000>; 93 }; 94 }; 95 }; 96 97 soc8313@e0000000 { 98 #address-cells = <1>; 99 #size-cells = <1>; 100 device_type = "soc"; 101 compatible = "simple-bus"; 102 ranges = <0x0 0xe0000000 0x00100000>; 103 reg = <0xe0000000 0x00000200>; 104 bus-frequency = <0>; 105 106 wdt@200 { 107 device_type = "watchdog"; 108 compatible = "mpc83xx_wdt"; 109 reg = <0x200 0x100>; 110 }; 111 112 sleep-nexus { 113 #address-cells = <1>; 114 #size-cells = <1>; 115 compatible = "simple-bus"; 116 sleep = <&pmc 0x03000000>; 117 ranges; 118 119 i2c@3000 { 120 #address-cells = <1>; 121 #size-cells = <0>; 122 cell-index = <0>; 123 compatible = "fsl-i2c"; 124 reg = <0x3000 0x100>; 125 interrupts = <14 0x8>; 126 interrupt-parent = <&ipic>; 127 dfsrr; 128 rtc@68 { 129 compatible = "dallas,ds1339"; 130 reg = <0x68>; 131 }; 132 }; 133 134 crypto@30000 { 135 compatible = "fsl,sec2.2", "fsl,sec2.1", 136 "fsl,sec2.0"; 137 reg = <0x30000 0x10000>; 138 interrupts = <11 0x8>; 139 interrupt-parent = <&ipic>; 140 fsl,num-channels = <1>; 141 fsl,channel-fifo-len = <24>; 142 fsl,exec-units-mask = <0x4c>; 143 fsl,descriptor-types-mask = <0x0122003f>; 144 }; 145 }; 146 147 i2c@3100 { 148 #address-cells = <1>; 149 #size-cells = <0>; 150 cell-index = <1>; 151 compatible = "fsl-i2c"; 152 reg = <0x3100 0x100>; 153 interrupts = <15 0x8>; 154 interrupt-parent = <&ipic>; 155 dfsrr; 156 }; 157 158 spi@7000 { 159 cell-index = <0>; 160 compatible = "fsl,spi"; 161 reg = <0x7000 0x1000>; 162 interrupts = <16 0x8>; 163 interrupt-parent = <&ipic>; 164 mode = "cpu"; 165 }; 166 167 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */ 168 usb@23000 { 169 compatible = "fsl-usb2-dr"; 170 reg = <0x23000 0x1000>; 171 #address-cells = <1>; 172 #size-cells = <0>; 173 interrupt-parent = <&ipic>; 174 interrupts = <38 0x8>; 175 phy_type = "utmi_wide"; 176 sleep = <&pmc 0x00300000>; 177 }; 178 179 enet0: ethernet@24000 { 180 #address-cells = <1>; 181 #size-cells = <1>; 182 sleep = <&pmc 0x20000000>; 183 ranges; 184 185 cell-index = <0>; 186 device_type = "network"; 187 model = "eTSEC"; 188 compatible = "gianfar"; 189 reg = <0x24000 0x1000>; 190 local-mac-address = [ 00 00 00 00 00 00 ]; 191 interrupts = <37 0x8 36 0x8 35 0x8>; 192 interrupt-parent = <&ipic>; 193 tbi-handle = < &tbi0 >; 194 phy-handle = < &phy1 >; 195 fsl,magic-packet; 196 197 mdio@24520 { 198 #address-cells = <1>; 199 #size-cells = <0>; 200 compatible = "fsl,gianfar-mdio"; 201 reg = <0x24520 0x20>; 202 phy1: ethernet-phy@1 { 203 interrupt-parent = <&ipic>; 204 interrupts = <19 0x8>; 205 reg = <0x1>; 206 device_type = "ethernet-phy"; 207 }; 208 phy4: ethernet-phy@4 { 209 interrupt-parent = <&ipic>; 210 interrupts = <20 0x8>; 211 reg = <0x4>; 212 device_type = "ethernet-phy"; 213 }; 214 tbi0: tbi-phy@11 { 215 reg = <0x11>; 216 device_type = "tbi-phy"; 217 }; 218 }; 219 }; 220 221 enet1: ethernet@25000 { 222 cell-index = <1>; 223 device_type = "network"; 224 model = "eTSEC"; 225 compatible = "gianfar"; 226 reg = <0x25000 0x1000>; 227 local-mac-address = [ 00 00 00 00 00 00 ]; 228 interrupts = <34 0x8 33 0x8 32 0x8>; 229 interrupt-parent = <&ipic>; 230 tbi-handle = < &tbi1 >; 231 phy-handle = < &phy4 >; 232 sleep = <&pmc 0x10000000>; 233 fsl,magic-packet; 234 235 mdio@25520 { 236 #address-cells = <1>; 237 #size-cells = <0>; 238 compatible = "fsl,gianfar-tbi"; 239 reg = <0x25520 0x20>; 240 241 tbi1: tbi-phy@11 { 242 reg = <0x11>; 243 device_type = "tbi-phy"; 244 }; 245 }; 246 247 248 }; 249 250 serial0: serial@4500 { 251 cell-index = <0>; 252 device_type = "serial"; 253 compatible = "ns16550"; 254 reg = <0x4500 0x100>; 255 clock-frequency = <0>; 256 interrupts = <9 0x8>; 257 interrupt-parent = <&ipic>; 258 }; 259 260 serial1: serial@4600 { 261 cell-index = <1>; 262 device_type = "serial"; 263 compatible = "ns16550"; 264 reg = <0x4600 0x100>; 265 clock-frequency = <0>; 266 interrupts = <10 0x8>; 267 interrupt-parent = <&ipic>; 268 }; 269 270 /* IPIC 271 * interrupts cell = <intr #, sense> 272 * sense values match linux IORESOURCE_IRQ_* defines: 273 * sense == 8: Level, low assertion 274 * sense == 2: Edge, high-to-low change 275 */ 276 ipic: pic@700 { 277 interrupt-controller; 278 #address-cells = <0>; 279 #interrupt-cells = <2>; 280 reg = <0x700 0x100>; 281 device_type = "ipic"; 282 }; 283 284 pmc: power@b00 { 285 compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; 286 reg = <0xb00 0x100 0xa00 0x100>; 287 interrupts = <80 8>; 288 interrupt-parent = <&ipic>; 289 fsl,mpc8313-wakeup-timer = <>m1>; 290 291 /* Remove this (or change to "okay") if you have 292 * a REVA3 or later board, if you apply one of the 293 * workarounds listed in section 8.5 of the board 294 * manual, or if you are adapting this device tree 295 * to a different board. 296 */ 297 status = "fail"; 298 }; 299 300 gtm1: timer@500 { 301 compatible = "fsl,mpc8313-gtm", "fsl,gtm"; 302 reg = <0x500 0x100>; 303 interrupts = <90 8 78 8 84 8 72 8>; 304 interrupt-parent = <&ipic>; 305 }; 306 307 timer@600 { 308 compatible = "fsl,mpc8313-gtm", "fsl,gtm"; 309 reg = <0x600 0x100>; 310 interrupts = <91 8 79 8 85 8 73 8>; 311 interrupt-parent = <&ipic>; 312 }; 313 }; 314 315 sleep-nexus { 316 #address-cells = <1>; 317 #size-cells = <1>; 318 compatible = "simple-bus"; 319 sleep = <&pmc 0x00010000>; 320 ranges; 321 322 pci0: pci@e0008500 { 323 cell-index = <1>; 324 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 325 interrupt-map = < 326 /* IDSEL 0x0E -mini PCI */ 327 0x7000 0x0 0x0 0x1 &ipic 18 0x8 328 0x7000 0x0 0x0 0x2 &ipic 18 0x8 329 0x7000 0x0 0x0 0x3 &ipic 18 0x8 330 0x7000 0x0 0x0 0x4 &ipic 18 0x8 331 332 /* IDSEL 0x0F - PCI slot */ 333 0x7800 0x0 0x0 0x1 &ipic 17 0x8 334 0x7800 0x0 0x0 0x2 &ipic 18 0x8 335 0x7800 0x0 0x0 0x3 &ipic 17 0x8 336 0x7800 0x0 0x0 0x4 &ipic 18 0x8>; 337 interrupt-parent = <&ipic>; 338 interrupts = <66 0x8>; 339 bus-range = <0x0 0x0>; 340 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 341 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 342 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 343 clock-frequency = <66666666>; 344 #interrupt-cells = <1>; 345 #size-cells = <2>; 346 #address-cells = <3>; 347 reg = <0xe0008500 0x100 /* internal registers */ 348 0xe0008300 0x8>; /* config space access registers */ 349 compatible = "fsl,mpc8349-pci"; 350 device_type = "pci"; 351 }; 352 353 dma@82a8 { 354 #address-cells = <1>; 355 #size-cells = <1>; 356 compatible = "fsl,mpc8313-dma", "fsl,elo-dma"; 357 reg = <0xe00082a8 4>; 358 ranges = <0 0xe0008100 0x1a8>; 359 interrupt-parent = <&ipic>; 360 interrupts = <71 8>; 361 362 dma-channel@0 { 363 compatible = "fsl,mpc8313-dma-channel", 364 "fsl,elo-dma-channel"; 365 reg = <0 0x28>; 366 interrupt-parent = <&ipic>; 367 interrupts = <71 8>; 368 cell-index = <0>; 369 }; 370 371 dma-channel@80 { 372 compatible = "fsl,mpc8313-dma-channel", 373 "fsl,elo-dma-channel"; 374 reg = <0x80 0x28>; 375 interrupt-parent = <&ipic>; 376 interrupts = <71 8>; 377 cell-index = <1>; 378 }; 379 380 dma-channel@100 { 381 compatible = "fsl,mpc8313-dma-channel", 382 "fsl,elo-dma-channel"; 383 reg = <0x100 0x28>; 384 interrupt-parent = <&ipic>; 385 interrupts = <71 8>; 386 cell-index = <2>; 387 }; 388 389 dma-channel@180 { 390 compatible = "fsl,mpc8313-dma-channel", 391 "fsl,elo-dma-channel"; 392 reg = <0x180 0x28>; 393 interrupt-parent = <&ipic>; 394 interrupts = <71 8>; 395 cell-index = <3>; 396 }; 397 }; 398 }; 399}; 400