1*b4e8c8ddSTorez Smith/* 2*b4e8c8ddSTorez Smith * Device Tree Source for IBM Embedded PPC 476 Platform 3*b4e8c8ddSTorez Smith * 4*b4e8c8ddSTorez Smith * Copyright 2010 Torez Smith, IBM Corporation. 5*b4e8c8ddSTorez Smith * 6*b4e8c8ddSTorez Smith * Based on earlier code: 7*b4e8c8ddSTorez Smith * Copyright (c) 2006, 2007 IBM Corp. 8*b4e8c8ddSTorez Smith * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com> 9*b4e8c8ddSTorez Smith * 10*b4e8c8ddSTorez Smith * This file is licensed under the terms of the GNU General Public 11*b4e8c8ddSTorez Smith * License version 2. This program is licensed "as is" without 12*b4e8c8ddSTorez Smith * any warranty of any kind, whether express or implied. 13*b4e8c8ddSTorez Smith */ 14*b4e8c8ddSTorez Smith 15*b4e8c8ddSTorez Smith/dts-v1/; 16*b4e8c8ddSTorez Smith 17*b4e8c8ddSTorez Smith/memreserve/ 0x01f00000 0x00100000; 18*b4e8c8ddSTorez Smith 19*b4e8c8ddSTorez Smith/ { 20*b4e8c8ddSTorez Smith #address-cells = <2>; 21*b4e8c8ddSTorez Smith #size-cells = <1>; 22*b4e8c8ddSTorez Smith model = "ibm,iss-4xx"; 23*b4e8c8ddSTorez Smith compatible = "ibm,iss-4xx"; 24*b4e8c8ddSTorez Smith dcr-parent = <&{/cpus/cpu@0}>; 25*b4e8c8ddSTorez Smith 26*b4e8c8ddSTorez Smith aliases { 27*b4e8c8ddSTorez Smith serial0 = &UART0; 28*b4e8c8ddSTorez Smith }; 29*b4e8c8ddSTorez Smith 30*b4e8c8ddSTorez Smith cpus { 31*b4e8c8ddSTorez Smith #address-cells = <1>; 32*b4e8c8ddSTorez Smith #size-cells = <0>; 33*b4e8c8ddSTorez Smith 34*b4e8c8ddSTorez Smith cpu@0 { 35*b4e8c8ddSTorez Smith device_type = "cpu"; 36*b4e8c8ddSTorez Smith model = "PowerPC,4xx"; // real CPU changed in sim 37*b4e8c8ddSTorez Smith reg = <0>; 38*b4e8c8ddSTorez Smith clock-frequency = <100000000>; // 100Mhz :-) 39*b4e8c8ddSTorez Smith timebase-frequency = <100000000>; 40*b4e8c8ddSTorez Smith i-cache-line-size = <32>; 41*b4e8c8ddSTorez Smith d-cache-line-size = <32>; 42*b4e8c8ddSTorez Smith i-cache-size = <32768>; 43*b4e8c8ddSTorez Smith d-cache-size = <32768>; 44*b4e8c8ddSTorez Smith dcr-controller; 45*b4e8c8ddSTorez Smith dcr-access-method = "native"; 46*b4e8c8ddSTorez Smith status = "ok"; 47*b4e8c8ddSTorez Smith }; 48*b4e8c8ddSTorez Smith cpu@1 { 49*b4e8c8ddSTorez Smith device_type = "cpu"; 50*b4e8c8ddSTorez Smith model = "PowerPC,4xx"; // real CPU changed in sim 51*b4e8c8ddSTorez Smith reg = <1>; 52*b4e8c8ddSTorez Smith clock-frequency = <100000000>; // 100Mhz :-) 53*b4e8c8ddSTorez Smith timebase-frequency = <100000000>; 54*b4e8c8ddSTorez Smith i-cache-line-size = <32>; 55*b4e8c8ddSTorez Smith d-cache-line-size = <32>; 56*b4e8c8ddSTorez Smith i-cache-size = <32768>; 57*b4e8c8ddSTorez Smith d-cache-size = <32768>; 58*b4e8c8ddSTorez Smith dcr-controller; 59*b4e8c8ddSTorez Smith dcr-access-method = "native"; 60*b4e8c8ddSTorez Smith status = "disabled"; 61*b4e8c8ddSTorez Smith enable-method = "spin-table"; 62*b4e8c8ddSTorez Smith cpu-release-addr = <0 0x01f00100>; 63*b4e8c8ddSTorez Smith }; 64*b4e8c8ddSTorez Smith cpu@2 { 65*b4e8c8ddSTorez Smith device_type = "cpu"; 66*b4e8c8ddSTorez Smith model = "PowerPC,4xx"; // real CPU changed in sim 67*b4e8c8ddSTorez Smith reg = <2>; 68*b4e8c8ddSTorez Smith clock-frequency = <100000000>; // 100Mhz :-) 69*b4e8c8ddSTorez Smith timebase-frequency = <100000000>; 70*b4e8c8ddSTorez Smith i-cache-line-size = <32>; 71*b4e8c8ddSTorez Smith d-cache-line-size = <32>; 72*b4e8c8ddSTorez Smith i-cache-size = <32768>; 73*b4e8c8ddSTorez Smith d-cache-size = <32768>; 74*b4e8c8ddSTorez Smith dcr-controller; 75*b4e8c8ddSTorez Smith dcr-access-method = "native"; 76*b4e8c8ddSTorez Smith status = "disabled"; 77*b4e8c8ddSTorez Smith enable-method = "spin-table"; 78*b4e8c8ddSTorez Smith cpu-release-addr = <0 0x01f00200>; 79*b4e8c8ddSTorez Smith }; 80*b4e8c8ddSTorez Smith cpu@3 { 81*b4e8c8ddSTorez Smith device_type = "cpu"; 82*b4e8c8ddSTorez Smith model = "PowerPC,4xx"; // real CPU changed in sim 83*b4e8c8ddSTorez Smith reg = <3>; 84*b4e8c8ddSTorez Smith clock-frequency = <100000000>; // 100Mhz :-) 85*b4e8c8ddSTorez Smith timebase-frequency = <100000000>; 86*b4e8c8ddSTorez Smith i-cache-line-size = <32>; 87*b4e8c8ddSTorez Smith d-cache-line-size = <32>; 88*b4e8c8ddSTorez Smith i-cache-size = <32768>; 89*b4e8c8ddSTorez Smith d-cache-size = <32768>; 90*b4e8c8ddSTorez Smith dcr-controller; 91*b4e8c8ddSTorez Smith dcr-access-method = "native"; 92*b4e8c8ddSTorez Smith status = "disabled"; 93*b4e8c8ddSTorez Smith enable-method = "spin-table"; 94*b4e8c8ddSTorez Smith cpu-release-addr = <0 0x01f00300>; 95*b4e8c8ddSTorez Smith }; 96*b4e8c8ddSTorez Smith }; 97*b4e8c8ddSTorez Smith 98*b4e8c8ddSTorez Smith memory { 99*b4e8c8ddSTorez Smith device_type = "memory"; 100*b4e8c8ddSTorez Smith reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage 101*b4e8c8ddSTorez Smith 102*b4e8c8ddSTorez Smith }; 103*b4e8c8ddSTorez Smith 104*b4e8c8ddSTorez Smith MPIC: interrupt-controller { 105*b4e8c8ddSTorez Smith compatible = "chrp,open-pic"; 106*b4e8c8ddSTorez Smith interrupt-controller; 107*b4e8c8ddSTorez Smith dcr-reg = <0xffc00000 0x00030000>; 108*b4e8c8ddSTorez Smith #address-cells = <0>; 109*b4e8c8ddSTorez Smith #size-cells = <0>; 110*b4e8c8ddSTorez Smith #interrupt-cells = <2>; 111*b4e8c8ddSTorez Smith 112*b4e8c8ddSTorez Smith }; 113*b4e8c8ddSTorez Smith 114*b4e8c8ddSTorez Smith plb { 115*b4e8c8ddSTorez Smith compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */ 116*b4e8c8ddSTorez Smith #address-cells = <2>; 117*b4e8c8ddSTorez Smith #size-cells = <1>; 118*b4e8c8ddSTorez Smith ranges; 119*b4e8c8ddSTorez Smith clock-frequency = <0>; // Filled in by zImage 120*b4e8c8ddSTorez Smith 121*b4e8c8ddSTorez Smith POB0: opb { 122*b4e8c8ddSTorez Smith compatible = "ibm,opb-4xx", "ibm,opb"; 123*b4e8c8ddSTorez Smith #address-cells = <1>; 124*b4e8c8ddSTorez Smith #size-cells = <1>; 125*b4e8c8ddSTorez Smith /* Wish there was a nicer way of specifying a full 32-bit 126*b4e8c8ddSTorez Smith range */ 127*b4e8c8ddSTorez Smith ranges = <0x00000000 0x00000001 0x00000000 0x80000000 128*b4e8c8ddSTorez Smith 0x80000000 0x00000001 0x80000000 0x80000000>; 129*b4e8c8ddSTorez Smith clock-frequency = <0>; // Filled in by zImage 130*b4e8c8ddSTorez Smith UART0: serial@40000200 { 131*b4e8c8ddSTorez Smith device_type = "serial"; 132*b4e8c8ddSTorez Smith compatible = "ns16550a"; 133*b4e8c8ddSTorez Smith reg = <0x40000200 0x00000008>; 134*b4e8c8ddSTorez Smith virtual-reg = <0xe0000200>; 135*b4e8c8ddSTorez Smith clock-frequency = <11059200>; 136*b4e8c8ddSTorez Smith current-speed = <115200>; 137*b4e8c8ddSTorez Smith interrupt-parent = <&MPIC>; 138*b4e8c8ddSTorez Smith interrupts = <0x0 0x2>; 139*b4e8c8ddSTorez Smith }; 140*b4e8c8ddSTorez Smith }; 141*b4e8c8ddSTorez Smith }; 142*b4e8c8ddSTorez Smith 143*b4e8c8ddSTorez Smith nvrtc { 144*b4e8c8ddSTorez Smith compatible = "ds1743-nvram", "ds1743", "rtc-ds1743"; 145*b4e8c8ddSTorez Smith reg = <0 0xEF703000 0x2000>; 146*b4e8c8ddSTorez Smith }; 147*b4e8c8ddSTorez Smith iss-block { 148*b4e8c8ddSTorez Smith compatible = "ibm,iss-sim-block-device"; 149*b4e8c8ddSTorez Smith reg = <0 0xEF701000 0x1000>; 150*b4e8c8ddSTorez Smith }; 151*b4e8c8ddSTorez Smith 152*b4e8c8ddSTorez Smith chosen { 153*b4e8c8ddSTorez Smith linux,stdout-path = "/plb/opb/serial@40000200"; 154*b4e8c8ddSTorez Smith }; 155*b4e8c8ddSTorez Smith}; 156