1*93b834e6SGregory CLEMENT// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*93b834e6SGregory CLEMENT/* Copyright (c) 2020 Microsemi Corporation */ 3*93b834e6SGregory CLEMENT 4*93b834e6SGregory CLEMENT/ { 5*93b834e6SGregory CLEMENT #address-cells = <1>; 6*93b834e6SGregory CLEMENT #size-cells = <1>; 7*93b834e6SGregory CLEMENT compatible = "mscc,luton"; 8*93b834e6SGregory CLEMENT 9*93b834e6SGregory CLEMENT cpus { 10*93b834e6SGregory CLEMENT #address-cells = <1>; 11*93b834e6SGregory CLEMENT #size-cells = <0>; 12*93b834e6SGregory CLEMENT 13*93b834e6SGregory CLEMENT cpu@0 { 14*93b834e6SGregory CLEMENT compatible = "mips,mips24KEc"; 15*93b834e6SGregory CLEMENT device_type = "cpu"; 16*93b834e6SGregory CLEMENT clocks = <&cpu_clk>; 17*93b834e6SGregory CLEMENT reg = <0>; 18*93b834e6SGregory CLEMENT }; 19*93b834e6SGregory CLEMENT }; 20*93b834e6SGregory CLEMENT 21*93b834e6SGregory CLEMENT aliases { 22*93b834e6SGregory CLEMENT serial0 = &uart0; 23*93b834e6SGregory CLEMENT }; 24*93b834e6SGregory CLEMENT 25*93b834e6SGregory CLEMENT cpuintc: interrupt-controller { 26*93b834e6SGregory CLEMENT #address-cells = <0>; 27*93b834e6SGregory CLEMENT #interrupt-cells = <1>; 28*93b834e6SGregory CLEMENT interrupt-controller; 29*93b834e6SGregory CLEMENT compatible = "mti,cpu-interrupt-controller"; 30*93b834e6SGregory CLEMENT }; 31*93b834e6SGregory CLEMENT 32*93b834e6SGregory CLEMENT cpu_clk: cpu-clock { 33*93b834e6SGregory CLEMENT compatible = "fixed-clock"; 34*93b834e6SGregory CLEMENT #clock-cells = <0>; 35*93b834e6SGregory CLEMENT clock-frequency = <416666666>; 36*93b834e6SGregory CLEMENT }; 37*93b834e6SGregory CLEMENT 38*93b834e6SGregory CLEMENT ahb_clk: ahb-clk { 39*93b834e6SGregory CLEMENT compatible = "fixed-factor-clock"; 40*93b834e6SGregory CLEMENT #clock-cells = <0>; 41*93b834e6SGregory CLEMENT clocks = <&cpu_clk>; 42*93b834e6SGregory CLEMENT clock-div = <2>; 43*93b834e6SGregory CLEMENT clock-mult = <1>; 44*93b834e6SGregory CLEMENT }; 45*93b834e6SGregory CLEMENT 46*93b834e6SGregory CLEMENT ahb@60000000 { 47*93b834e6SGregory CLEMENT compatible = "simple-bus"; 48*93b834e6SGregory CLEMENT #address-cells = <1>; 49*93b834e6SGregory CLEMENT #size-cells = <1>; 50*93b834e6SGregory CLEMENT ranges = <0 0x60000000 0x20000000>; 51*93b834e6SGregory CLEMENT 52*93b834e6SGregory CLEMENT interrupt-parent = <&intc>; 53*93b834e6SGregory CLEMENT 54*93b834e6SGregory CLEMENT cpu_ctrl: syscon@10000000 { 55*93b834e6SGregory CLEMENT compatible = "mscc,ocelot-cpu-syscon", "syscon"; 56*93b834e6SGregory CLEMENT reg = <0x10000000 0x2c>; 57*93b834e6SGregory CLEMENT }; 58*93b834e6SGregory CLEMENT 59*93b834e6SGregory CLEMENT intc: interrupt-controller@10000084 { 60*93b834e6SGregory CLEMENT compatible = "mscc,luton-icpu-intr"; 61*93b834e6SGregory CLEMENT reg = <0x10000084 0x70>; 62*93b834e6SGregory CLEMENT #interrupt-cells = <1>; 63*93b834e6SGregory CLEMENT interrupt-controller; 64*93b834e6SGregory CLEMENT interrupt-parent = <&cpuintc>; 65*93b834e6SGregory CLEMENT interrupts = <2>; 66*93b834e6SGregory CLEMENT }; 67*93b834e6SGregory CLEMENT 68*93b834e6SGregory CLEMENT uart0: serial@10100000 { 69*93b834e6SGregory CLEMENT pinctrl-0 = <&uart_pins>; 70*93b834e6SGregory CLEMENT pinctrl-names = "default"; 71*93b834e6SGregory CLEMENT compatible = "ns16550a"; 72*93b834e6SGregory CLEMENT reg = <0x10100000 0x20>; 73*93b834e6SGregory CLEMENT interrupts = <6>; 74*93b834e6SGregory CLEMENT clocks = <&ahb_clk>; 75*93b834e6SGregory CLEMENT reg-io-width = <4>; 76*93b834e6SGregory CLEMENT reg-shift = <2>; 77*93b834e6SGregory CLEMENT 78*93b834e6SGregory CLEMENT status = "disabled"; 79*93b834e6SGregory CLEMENT }; 80*93b834e6SGregory CLEMENT 81*93b834e6SGregory CLEMENT i2c0: i2c@10100400 { 82*93b834e6SGregory CLEMENT compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; 83*93b834e6SGregory CLEMENT pinctrl-0 = <&i2c_pins>; 84*93b834e6SGregory CLEMENT pinctrl-names = "default"; 85*93b834e6SGregory CLEMENT reg = <0x10100400 0x100>, <0x100002a4 0x8>; 86*93b834e6SGregory CLEMENT #address-cells = <1>; 87*93b834e6SGregory CLEMENT #size-cells = <0>; 88*93b834e6SGregory CLEMENT interrupts = <11>; 89*93b834e6SGregory CLEMENT clocks = <&ahb_clk>; 90*93b834e6SGregory CLEMENT 91*93b834e6SGregory CLEMENT status = "disabled"; 92*93b834e6SGregory CLEMENT }; 93*93b834e6SGregory CLEMENT 94*93b834e6SGregory CLEMENT gpio: pinctrl@70068 { 95*93b834e6SGregory CLEMENT compatible = "mscc,luton-pinctrl"; 96*93b834e6SGregory CLEMENT reg = <0x70068 0x28>; 97*93b834e6SGregory CLEMENT gpio-controller; 98*93b834e6SGregory CLEMENT #gpio-cells = <2>; 99*93b834e6SGregory CLEMENT gpio-ranges = <&gpio 0 0 32>; 100*93b834e6SGregory CLEMENT interrupt-controller; 101*93b834e6SGregory CLEMENT interrupts = <13>; 102*93b834e6SGregory CLEMENT #interrupt-cells = <2>; 103*93b834e6SGregory CLEMENT 104*93b834e6SGregory CLEMENT i2c_pins: i2c-pins { 105*93b834e6SGregory CLEMENT pins = "GPIO_5", "GPIO_6"; 106*93b834e6SGregory CLEMENT function = "twi"; 107*93b834e6SGregory CLEMENT }; 108*93b834e6SGregory CLEMENT 109*93b834e6SGregory CLEMENT uart_pins: uart-pins { 110*93b834e6SGregory CLEMENT pins = "GPIO_30", "GPIO_31"; 111*93b834e6SGregory CLEMENT function = "uart"; 112*93b834e6SGregory CLEMENT }; 113*93b834e6SGregory CLEMENT 114*93b834e6SGregory CLEMENT }; 115*93b834e6SGregory CLEMENT }; 116*93b834e6SGregory CLEMENT}; 117