xref: /linux/scripts/dtc/include-prefixes/mips/mscc/jaguar2.dtsi (revision cdd38c5f1ce4398ec58fec95904b75824daab7b5)
1*f84778f7SGregory CLEMENT// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*f84778f7SGregory CLEMENT/*
3*f84778f7SGregory CLEMENT * Copyright (c) 2020 Microsemi Corporation
4*f84778f7SGregory CLEMENT */
5*f84778f7SGregory CLEMENT
6*f84778f7SGregory CLEMENT/ {
7*f84778f7SGregory CLEMENT	#address-cells = <1>;
8*f84778f7SGregory CLEMENT	#size-cells = <1>;
9*f84778f7SGregory CLEMENT	compatible = "mscc,jr2";
10*f84778f7SGregory CLEMENT
11*f84778f7SGregory CLEMENT	aliases {
12*f84778f7SGregory CLEMENT		serial0 = &uart0;
13*f84778f7SGregory CLEMENT		serial1 = &uart2;
14*f84778f7SGregory CLEMENT		gpio0 = &gpio;
15*f84778f7SGregory CLEMENT	};
16*f84778f7SGregory CLEMENT
17*f84778f7SGregory CLEMENT	cpus {
18*f84778f7SGregory CLEMENT		#address-cells = <1>;
19*f84778f7SGregory CLEMENT		#size-cells = <0>;
20*f84778f7SGregory CLEMENT
21*f84778f7SGregory CLEMENT		cpu@0 {
22*f84778f7SGregory CLEMENT			compatible = "mips,mips24KEc";
23*f84778f7SGregory CLEMENT			device_type = "cpu";
24*f84778f7SGregory CLEMENT			clocks = <&cpu_clk>;
25*f84778f7SGregory CLEMENT			reg = <0>;
26*f84778f7SGregory CLEMENT		};
27*f84778f7SGregory CLEMENT	};
28*f84778f7SGregory CLEMENT
29*f84778f7SGregory CLEMENT	cpuintc: interrupt-controller {
30*f84778f7SGregory CLEMENT		#address-cells = <0>;
31*f84778f7SGregory CLEMENT		#interrupt-cells = <1>;
32*f84778f7SGregory CLEMENT		interrupt-controller;
33*f84778f7SGregory CLEMENT		compatible = "mti,cpu-interrupt-controller";
34*f84778f7SGregory CLEMENT	};
35*f84778f7SGregory CLEMENT
36*f84778f7SGregory CLEMENT	cpu_clk: cpu-clock {
37*f84778f7SGregory CLEMENT		compatible = "fixed-clock";
38*f84778f7SGregory CLEMENT		#clock-cells = <0>;
39*f84778f7SGregory CLEMENT		clock-frequency = <500000000>;
40*f84778f7SGregory CLEMENT	};
41*f84778f7SGregory CLEMENT
42*f84778f7SGregory CLEMENT	ahb_clk: ahb-clk {
43*f84778f7SGregory CLEMENT		compatible = "fixed-factor-clock";
44*f84778f7SGregory CLEMENT		#clock-cells = <0>;
45*f84778f7SGregory CLEMENT		clocks = <&cpu_clk>;
46*f84778f7SGregory CLEMENT		clock-div = <2>;
47*f84778f7SGregory CLEMENT		clock-mult = <1>;
48*f84778f7SGregory CLEMENT	};
49*f84778f7SGregory CLEMENT
50*f84778f7SGregory CLEMENT	ahb: ahb {
51*f84778f7SGregory CLEMENT		compatible = "simple-bus";
52*f84778f7SGregory CLEMENT		#address-cells = <1>;
53*f84778f7SGregory CLEMENT		#size-cells = <1>;
54*f84778f7SGregory CLEMENT		ranges;
55*f84778f7SGregory CLEMENT
56*f84778f7SGregory CLEMENT		interrupt-parent = <&intc>;
57*f84778f7SGregory CLEMENT
58*f84778f7SGregory CLEMENT		cpu_ctrl: syscon@70000000 {
59*f84778f7SGregory CLEMENT			compatible = "mscc,ocelot-cpu-syscon", "syscon";
60*f84778f7SGregory CLEMENT			reg = <0x70000000 0x2c>;
61*f84778f7SGregory CLEMENT		};
62*f84778f7SGregory CLEMENT
63*f84778f7SGregory CLEMENT		intc: interrupt-controller@70000070 {
64*f84778f7SGregory CLEMENT			compatible = "mscc,jaguar2-icpu-intr";
65*f84778f7SGregory CLEMENT			reg = <0x70000070 0x94>;
66*f84778f7SGregory CLEMENT			#interrupt-cells = <1>;
67*f84778f7SGregory CLEMENT			interrupt-controller;
68*f84778f7SGregory CLEMENT			interrupt-parent = <&cpuintc>;
69*f84778f7SGregory CLEMENT			interrupts = <2>;
70*f84778f7SGregory CLEMENT		};
71*f84778f7SGregory CLEMENT
72*f84778f7SGregory CLEMENT		uart0: serial@70100000 {
73*f84778f7SGregory CLEMENT			pinctrl-0 = <&uart_pins>;
74*f84778f7SGregory CLEMENT			pinctrl-names = "default";
75*f84778f7SGregory CLEMENT			compatible = "ns16550a";
76*f84778f7SGregory CLEMENT			reg = <0x70100000 0x20>;
77*f84778f7SGregory CLEMENT			interrupts = <6>;
78*f84778f7SGregory CLEMENT			clocks = <&ahb_clk>;
79*f84778f7SGregory CLEMENT			reg-io-width = <4>;
80*f84778f7SGregory CLEMENT			reg-shift = <2>;
81*f84778f7SGregory CLEMENT
82*f84778f7SGregory CLEMENT			status = "disabled";
83*f84778f7SGregory CLEMENT		};
84*f84778f7SGregory CLEMENT
85*f84778f7SGregory CLEMENT		uart2: serial@70100800 {
86*f84778f7SGregory CLEMENT			pinctrl-0 = <&uart2_pins>;
87*f84778f7SGregory CLEMENT			pinctrl-names = "default";
88*f84778f7SGregory CLEMENT			compatible = "ns16550a";
89*f84778f7SGregory CLEMENT			reg = <0x70100800 0x20>;
90*f84778f7SGregory CLEMENT			interrupts = <7>;
91*f84778f7SGregory CLEMENT			clocks = <&ahb_clk>;
92*f84778f7SGregory CLEMENT			reg-io-width = <4>;
93*f84778f7SGregory CLEMENT			reg-shift = <2>;
94*f84778f7SGregory CLEMENT
95*f84778f7SGregory CLEMENT			status = "disabled";
96*f84778f7SGregory CLEMENT		};
97*f84778f7SGregory CLEMENT
98*f84778f7SGregory CLEMENT		gpio: pinctrl@71010038 {
99*f84778f7SGregory CLEMENT			compatible = "mscc,jaguar2-pinctrl";
100*f84778f7SGregory CLEMENT			reg = <0x71010038 0x90>;
101*f84778f7SGregory CLEMENT			gpio-controller;
102*f84778f7SGregory CLEMENT			#gpio-cells = <2>;
103*f84778f7SGregory CLEMENT			gpio-ranges = <&gpio 0 0 64>;
104*f84778f7SGregory CLEMENT
105*f84778f7SGregory CLEMENT			uart_pins: uart-pins {
106*f84778f7SGregory CLEMENT				pins = "GPIO_10", "GPIO_11";
107*f84778f7SGregory CLEMENT				function = "uart";
108*f84778f7SGregory CLEMENT			};
109*f84778f7SGregory CLEMENT
110*f84778f7SGregory CLEMENT			uart2_pins: uart2-pins {
111*f84778f7SGregory CLEMENT				pins = "GPIO_24", "GPIO_25";
112*f84778f7SGregory CLEMENT				function = "uart2";
113*f84778f7SGregory CLEMENT			};
114*f84778f7SGregory CLEMENT
115*f84778f7SGregory CLEMENT			cs1_pins: cs1-pins {
116*f84778f7SGregory CLEMENT				pins = "GPIO_16";
117*f84778f7SGregory CLEMENT				function = "si";
118*f84778f7SGregory CLEMENT			};
119*f84778f7SGregory CLEMENT
120*f84778f7SGregory CLEMENT			cs2_pins: cs2-pins {
121*f84778f7SGregory CLEMENT				pins = "GPIO_17";
122*f84778f7SGregory CLEMENT				function = "si";
123*f84778f7SGregory CLEMENT			};
124*f84778f7SGregory CLEMENT
125*f84778f7SGregory CLEMENT			cs3_pins: cs3-pins {
126*f84778f7SGregory CLEMENT				pins = "GPIO_18";
127*f84778f7SGregory CLEMENT				function = "si";
128*f84778f7SGregory CLEMENT			};
129*f84778f7SGregory CLEMENT
130*f84778f7SGregory CLEMENT			i2c_pins: i2c-pins {
131*f84778f7SGregory CLEMENT				pins = "GPIO_14", "GPIO_15";
132*f84778f7SGregory CLEMENT				function = "twi";
133*f84778f7SGregory CLEMENT			};
134*f84778f7SGregory CLEMENT
135*f84778f7SGregory CLEMENT			i2c2_pins: i2c2-pins {
136*f84778f7SGregory CLEMENT				pins = "GPIO_28", "GPIO_29";
137*f84778f7SGregory CLEMENT				function = "twi2";
138*f84778f7SGregory CLEMENT			};
139*f84778f7SGregory CLEMENT		};
140*f84778f7SGregory CLEMENT
141*f84778f7SGregory CLEMENT		i2c0: i2c@70100400 {
142*f84778f7SGregory CLEMENT			compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
143*f84778f7SGregory CLEMENT			status = "disabled";
144*f84778f7SGregory CLEMENT			pinctrl-0 = <&i2c_pins>;
145*f84778f7SGregory CLEMENT			pinctrl-names = "default";
146*f84778f7SGregory CLEMENT			reg = <0x70100400 0x100>, <0x700001b8 0x8>;
147*f84778f7SGregory CLEMENT			#address-cells = <1>;
148*f84778f7SGregory CLEMENT			#size-cells = <0>;
149*f84778f7SGregory CLEMENT			interrupts = <8>;
150*f84778f7SGregory CLEMENT			clock-frequency = <100000>;
151*f84778f7SGregory CLEMENT			clocks = <&ahb_clk>;
152*f84778f7SGregory CLEMENT		};
153*f84778f7SGregory CLEMENT
154*f84778f7SGregory CLEMENT		i2c2: i2c@70100c00 {
155*f84778f7SGregory CLEMENT			compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
156*f84778f7SGregory CLEMENT			status = "disabled";
157*f84778f7SGregory CLEMENT			pinctrl-0 = <&i2c2_pins>;
158*f84778f7SGregory CLEMENT			pinctrl-names = "default";
159*f84778f7SGregory CLEMENT			reg = <0x70100c00 0x100>;
160*f84778f7SGregory CLEMENT			#address-cells = <1>;
161*f84778f7SGregory CLEMENT			#size-cells = <0>;
162*f84778f7SGregory CLEMENT			interrupts = <8>;
163*f84778f7SGregory CLEMENT			clock-frequency = <100000>;
164*f84778f7SGregory CLEMENT			clocks = <&ahb_clk>;
165*f84778f7SGregory CLEMENT		};
166*f84778f7SGregory CLEMENT	};
167*f84778f7SGregory CLEMENT};
168