1*f8523d0eSHuacai Chen// SPDX-License-Identifier: GPL-2.0 2*f8523d0eSHuacai Chen 3*f8523d0eSHuacai Chen#include <dt-bindings/interrupt-controller/irq.h> 4*f8523d0eSHuacai Chen 5*f8523d0eSHuacai Chen/ { 6*f8523d0eSHuacai Chen #address-cells = <2>; 7*f8523d0eSHuacai Chen #size-cells = <2>; 8*f8523d0eSHuacai Chen 9*f8523d0eSHuacai Chen cpuintc: interrupt-controller { 10*f8523d0eSHuacai Chen #address-cells = <0>; 11*f8523d0eSHuacai Chen #interrupt-cells = <1>; 12*f8523d0eSHuacai Chen interrupt-controller; 13*f8523d0eSHuacai Chen compatible = "mti,cpu-interrupt-controller"; 14*f8523d0eSHuacai Chen }; 15*f8523d0eSHuacai Chen 16*f8523d0eSHuacai Chen package0: bus@1fe00000 { 17*f8523d0eSHuacai Chen compatible = "simple-bus"; 18*f8523d0eSHuacai Chen #address-cells = <2>; 19*f8523d0eSHuacai Chen #size-cells = <1>; 20*f8523d0eSHuacai Chen ranges = <0 0x1fe00000 0 0x1fe00000 0x100000 21*f8523d0eSHuacai Chen 0 0x3ff00000 0 0x3ff00000 0x100000 22*f8523d0eSHuacai Chen /* 3A HT Config Space */ 23*f8523d0eSHuacai Chen 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000 24*f8523d0eSHuacai Chen /* 3B HT Config Space */ 25*f8523d0eSHuacai Chen 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000>; 26*f8523d0eSHuacai Chen 27*f8523d0eSHuacai Chen liointc: interrupt-controller@3ff01400 { 28*f8523d0eSHuacai Chen compatible = "loongson,liointc-1.0"; 29*f8523d0eSHuacai Chen reg = <0 0x3ff01400 0x64>; 30*f8523d0eSHuacai Chen 31*f8523d0eSHuacai Chen interrupt-controller; 32*f8523d0eSHuacai Chen #interrupt-cells = <2>; 33*f8523d0eSHuacai Chen 34*f8523d0eSHuacai Chen interrupt-parent = <&cpuintc>; 35*f8523d0eSHuacai Chen interrupts = <2>, <3>; 36*f8523d0eSHuacai Chen interrupt-names = "int0", "int1"; 37*f8523d0eSHuacai Chen 38*f8523d0eSHuacai Chen loongson,parent_int_map = <0xf0ffffff>, /* int0 */ 39*f8523d0eSHuacai Chen <0x0f000000>, /* int1 */ 40*f8523d0eSHuacai Chen <0x00000000>, /* int2 */ 41*f8523d0eSHuacai Chen <0x00000000>; /* int3 */ 42*f8523d0eSHuacai Chen 43*f8523d0eSHuacai Chen }; 44*f8523d0eSHuacai Chen 45*f8523d0eSHuacai Chen cpu_uart0: serial@1fe001e0 { 46*f8523d0eSHuacai Chen compatible = "ns16550a"; 47*f8523d0eSHuacai Chen reg = <0 0x1fe001e0 0x8>; 48*f8523d0eSHuacai Chen clock-frequency = <33000000>; 49*f8523d0eSHuacai Chen interrupt-parent = <&liointc>; 50*f8523d0eSHuacai Chen interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 51*f8523d0eSHuacai Chen no-loopback-test; 52*f8523d0eSHuacai Chen }; 53*f8523d0eSHuacai Chen 54*f8523d0eSHuacai Chen cpu_uart1: serial@1fe001e8 { 55*f8523d0eSHuacai Chen status = "disabled"; 56*f8523d0eSHuacai Chen compatible = "ns16550a"; 57*f8523d0eSHuacai Chen reg = <0 0x1fe001e8 0x8>; 58*f8523d0eSHuacai Chen clock-frequency = <33000000>; 59*f8523d0eSHuacai Chen interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 60*f8523d0eSHuacai Chen interrupt-parent = <&liointc>; 61*f8523d0eSHuacai Chen no-loopback-test; 62*f8523d0eSHuacai Chen }; 63*f8523d0eSHuacai Chen }; 64*f8523d0eSHuacai Chen}; 65