1*dd240e95SLaura Nao /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*dd240e95SLaura Nao /* 3*dd240e95SLaura Nao * Copyright (c) 2025 Collabora Ltd. 4*dd240e95SLaura Nao * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 5*dd240e95SLaura Nao */ 6*dd240e95SLaura Nao 7*dd240e95SLaura Nao #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8196 8*dd240e95SLaura Nao #define _DT_BINDINGS_RESET_CONTROLLER_MT8196 9*dd240e95SLaura Nao 10*dd240e95SLaura Nao /* PEXTP0 resets */ 11*dd240e95SLaura Nao #define MT8196_PEXTP0_RST0_PCIE0_MAC 0 12*dd240e95SLaura Nao #define MT8196_PEXTP0_RST0_PCIE0_PHY 1 13*dd240e95SLaura Nao 14*dd240e95SLaura Nao /* PEXTP1 resets */ 15*dd240e95SLaura Nao #define MT8196_PEXTP1_RST0_PCIE1_MAC 0 16*dd240e95SLaura Nao #define MT8196_PEXTP1_RST0_PCIE1_PHY 1 17*dd240e95SLaura Nao #define MT8196_PEXTP1_RST0_PCIE2_MAC 2 18*dd240e95SLaura Nao #define MT8196_PEXTP1_RST0_PCIE2_PHY 3 19*dd240e95SLaura Nao 20*dd240e95SLaura Nao /* UFS resets */ 21*dd240e95SLaura Nao #define MT8196_UFSAO_RST0_UFS_MPHY 0 22*dd240e95SLaura Nao #define MT8196_UFSAO_RST1_UFS_UNIPRO 1 23*dd240e95SLaura Nao #define MT8196_UFSAO_RST1_UFS_CRYPTO 2 24*dd240e95SLaura Nao #define MT8196_UFSAO_RST1_UFSHCI 3 25*dd240e95SLaura Nao 26*dd240e95SLaura Nao #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8196 */ 27