1*1dccb5ecSSai Krishna Potthuri /* SPDX-License-Identifier: GPL-2.0 */ 2*1dccb5ecSSai Krishna Potthuri /* 3*1dccb5ecSSai Krishna Potthuri * MIO pin configuration defines for Xilinx ZynqMP 4*1dccb5ecSSai Krishna Potthuri * 5*1dccb5ecSSai Krishna Potthuri * Copyright (C) 2020 Xilinx, Inc. 6*1dccb5ecSSai Krishna Potthuri */ 7*1dccb5ecSSai Krishna Potthuri 8*1dccb5ecSSai Krishna Potthuri #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H 9*1dccb5ecSSai Krishna Potthuri #define _DT_BINDINGS_PINCTRL_ZYNQMP_H 10*1dccb5ecSSai Krishna Potthuri 11*1dccb5ecSSai Krishna Potthuri /* Bit value for different voltage levels */ 12*1dccb5ecSSai Krishna Potthuri #define IO_STANDARD_LVCMOS33 0 13*1dccb5ecSSai Krishna Potthuri #define IO_STANDARD_LVCMOS18 1 14*1dccb5ecSSai Krishna Potthuri 15*1dccb5ecSSai Krishna Potthuri /* Bit values for Slew Rates */ 16*1dccb5ecSSai Krishna Potthuri #define SLEW_RATE_FAST 0 17*1dccb5ecSSai Krishna Potthuri #define SLEW_RATE_SLOW 1 18*1dccb5ecSSai Krishna Potthuri 19*1dccb5ecSSai Krishna Potthuri #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ 20