1*f9a8744dSAnson Huang /* SPDX-License-Identifier: GPL-2.0+ */ 2*f9a8744dSAnson Huang /* 3*f9a8744dSAnson Huang * Copyright 2019~2020 NXP 4*f9a8744dSAnson Huang */ 5*f9a8744dSAnson Huang 6*f9a8744dSAnson Huang #ifndef _IMX8DXL_PADS_H 7*f9a8744dSAnson Huang #define _IMX8DXL_PADS_H 8*f9a8744dSAnson Huang 9*f9a8744dSAnson Huang /* pin id */ 10*f9a8744dSAnson Huang #define IMX8DXL_PCIE_CTRL0_PERST_B 0 11*f9a8744dSAnson Huang #define IMX8DXL_PCIE_CTRL0_CLKREQ_B 1 12*f9a8744dSAnson Huang #define IMX8DXL_PCIE_CTRL0_WAKE_B 2 13*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 14*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC0 4 15*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC1 5 16*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC2 6 17*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC3 7 18*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 8 19*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_CLK 9 20*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_CMD 10 21*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA0 11 22*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA1 12 23*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA2 13 24*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA3 14 25*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA4 15 26*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA5 16 27*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA6 17 28*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA7 18 29*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_STROBE 19 30*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_RESET_B 20 31*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 21 32*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_RESET_B 22 33*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_VSELECT 23 34*f9a8744dSAnson Huang #define IMX8DXL_CTL_NAND_RE_P_N 24 35*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_WP 25 36*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_CD_B 26 37*f9a8744dSAnson Huang #define IMX8DXL_CTL_NAND_DQS_P_N 27 38*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP 28 39*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXC 29 40*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TX_CTL 30 41*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD0 31 42*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD1 32 43*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD2 33 44*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD3 34 45*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 35 46*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXC 36 47*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RX_CTL 37 48*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD0 38 49*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD1 39 50*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD2 40 51*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD3 41 52*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 42 53*f9a8744dSAnson Huang #define IMX8DXL_ENET0_REFCLK_125M_25M 43 54*f9a8744dSAnson Huang #define IMX8DXL_ENET0_MDIO 44 55*f9a8744dSAnson Huang #define IMX8DXL_ENET0_MDC 45 56*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT 46 57*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXC 47 58*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD2 48 59*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TX_CTL 49 60*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD3 50 61*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXC 51 62*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD3 52 63*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD2 53 64*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD1 54 65*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD0 55 66*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD1 56 67*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD0 57 68*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RX_CTL 58 69*f9a8744dSAnson Huang #define IMX8DXL_ENET1_REFCLK_125M_25M 59 70*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB 60 71*f9a8744dSAnson Huang #define IMX8DXL_SPI3_SCK 61 72*f9a8744dSAnson Huang #define IMX8DXL_SPI3_SDO 62 73*f9a8744dSAnson Huang #define IMX8DXL_SPI3_SDI 63 74*f9a8744dSAnson Huang #define IMX8DXL_SPI3_CS0 64 75*f9a8744dSAnson Huang #define IMX8DXL_SPI3_CS1 65 76*f9a8744dSAnson Huang #define IMX8DXL_MCLK_IN1 66 77*f9a8744dSAnson Huang #define IMX8DXL_MCLK_IN0 67 78*f9a8744dSAnson Huang #define IMX8DXL_MCLK_OUT0 68 79*f9a8744dSAnson Huang #define IMX8DXL_UART1_TX 69 80*f9a8744dSAnson Huang #define IMX8DXL_UART1_RX 70 81*f9a8744dSAnson Huang #define IMX8DXL_UART1_RTS_B 71 82*f9a8744dSAnson Huang #define IMX8DXL_UART1_CTS_B 72 83*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK 73 84*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SCK 74 85*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SDI 75 86*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SDO 76 87*f9a8744dSAnson Huang #define IMX8DXL_SPI0_CS1 77 88*f9a8744dSAnson Huang #define IMX8DXL_SPI0_CS0 78 89*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT 79 90*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN1 80 91*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN0 81 92*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN3 82 93*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN2 83 94*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN5 84 95*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN4 85 96*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN0_RX 86 97*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN0_TX 87 98*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN1_RX 88 99*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN1_TX 89 100*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN2_RX 90 101*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN2_TX 91 102*f9a8744dSAnson Huang #define IMX8DXL_UART0_RX 92 103*f9a8744dSAnson Huang #define IMX8DXL_UART0_TX 93 104*f9a8744dSAnson Huang #define IMX8DXL_UART2_TX 94 105*f9a8744dSAnson Huang #define IMX8DXL_UART2_RX 95 106*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH 96 107*f9a8744dSAnson Huang #define IMX8DXL_JTAG_TRST_B 97 108*f9a8744dSAnson Huang #define IMX8DXL_PMIC_I2C_SCL 98 109*f9a8744dSAnson Huang #define IMX8DXL_PMIC_I2C_SDA 99 110*f9a8744dSAnson Huang #define IMX8DXL_PMIC_INT_B 100 111*f9a8744dSAnson Huang #define IMX8DXL_SCU_GPIO0_00 101 112*f9a8744dSAnson Huang #define IMX8DXL_SCU_GPIO0_01 102 113*f9a8744dSAnson Huang #define IMX8DXL_SCU_PMIC_STANDBY 103 114*f9a8744dSAnson Huang #define IMX8DXL_SCU_BOOT_MODE1 104 115*f9a8744dSAnson Huang #define IMX8DXL_SCU_BOOT_MODE0 105 116*f9a8744dSAnson Huang #define IMX8DXL_SCU_BOOT_MODE2 106 117*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_OUT1 107 118*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_OUT2 108 119*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_OUT3 109 120*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_OUT4 110 121*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN0 111 122*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN1 112 123*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN2 113 124*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN3 114 125*f9a8744dSAnson Huang #define IMX8DXL_SPI1_SCK 115 126*f9a8744dSAnson Huang #define IMX8DXL_SPI1_SDO 116 127*f9a8744dSAnson Huang #define IMX8DXL_SPI1_SDI 117 128*f9a8744dSAnson Huang #define IMX8DXL_SPI1_CS0 118 129*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD 119 130*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_DATA1 120 131*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_DATA0 121 132*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_DATA3 122 133*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_DATA2 123 134*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_SS0_B 124 135*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_DQS 125 136*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_SCLK 126 137*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A 127 138*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_SCLK 128 139*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_DQS 129 140*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_DATA1 130 141*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_DATA0 131 142*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_DATA3 132 143*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_DATA2 133 144*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_SS0_B 134 145*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B 135 146*f9a8744dSAnson Huang 147*f9a8744dSAnson Huang /* format: <pin_id mux_mode> */ 148*f9a8744dSAnson Huang #define IMX8DXL_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8DXL_PCIE_CTRL0_PERST_B 0 149*f9a8744dSAnson Huang #define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 4 150*f9a8744dSAnson Huang #define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO7_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 5 151*f9a8744dSAnson Huang #define IMX8DXL_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8DXL_PCIE_CTRL0_CLKREQ_B 0 152*f9a8744dSAnson Huang #define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 4 153*f9a8744dSAnson Huang #define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO7_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 5 154*f9a8744dSAnson Huang #define IMX8DXL_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8DXL_PCIE_CTRL0_WAKE_B 0 155*f9a8744dSAnson Huang #define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 4 156*f9a8744dSAnson Huang #define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO7_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 5 157*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC0_ADMA_I2C1_SCL IMX8DXL_USB_SS3_TC0 0 158*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8DXL_USB_SS3_TC0 1 159*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC0 2 160*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8DXL_USB_SS3_TC0 4 161*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC0_LSIO_GPIO7_IO03 IMX8DXL_USB_SS3_TC0 5 162*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC1_ADMA_I2C1_SCL IMX8DXL_USB_SS3_TC1 0 163*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC1 1 164*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8DXL_USB_SS3_TC1 4 165*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC1_LSIO_GPIO7_IO04 IMX8DXL_USB_SS3_TC1 5 166*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC2_ADMA_I2C1_SDA IMX8DXL_USB_SS3_TC2 0 167*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8DXL_USB_SS3_TC2 1 168*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8DXL_USB_SS3_TC2 2 169*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8DXL_USB_SS3_TC2 4 170*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC2_LSIO_GPIO7_IO05 IMX8DXL_USB_SS3_TC2 5 171*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC3_ADMA_I2C1_SDA IMX8DXL_USB_SS3_TC3 0 172*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8DXL_USB_SS3_TC3 1 173*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8DXL_USB_SS3_TC3 4 174*f9a8744dSAnson Huang #define IMX8DXL_USB_SS3_TC3_LSIO_GPIO7_IO06 IMX8DXL_USB_SS3_TC3 5 175*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK IMX8DXL_EMMC0_CLK 0 176*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_CLK_CONN_NAND_READY_B IMX8DXL_EMMC0_CLK 1 177*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_CLK_LSIO_GPIO4_IO07 IMX8DXL_EMMC0_CLK 4 178*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD IMX8DXL_EMMC0_CMD 0 179*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_CMD_CONN_NAND_DQS IMX8DXL_EMMC0_CMD 1 180*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_CMD_LSIO_GPIO4_IO08 IMX8DXL_EMMC0_CMD 4 181*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8DXL_EMMC0_DATA0 0 182*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA0_CONN_NAND_DATA00 IMX8DXL_EMMC0_DATA0 1 183*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA0_LSIO_GPIO4_IO09 IMX8DXL_EMMC0_DATA0 4 184*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8DXL_EMMC0_DATA1 0 185*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA1_CONN_NAND_DATA01 IMX8DXL_EMMC0_DATA1 1 186*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA1_LSIO_GPIO4_IO10 IMX8DXL_EMMC0_DATA1 4 187*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8DXL_EMMC0_DATA2 0 188*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA2_CONN_NAND_DATA02 IMX8DXL_EMMC0_DATA2 1 189*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA2_LSIO_GPIO4_IO11 IMX8DXL_EMMC0_DATA2 4 190*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8DXL_EMMC0_DATA3 0 191*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA3_CONN_NAND_DATA03 IMX8DXL_EMMC0_DATA3 1 192*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA3_LSIO_GPIO4_IO12 IMX8DXL_EMMC0_DATA3 4 193*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8DXL_EMMC0_DATA4 0 194*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA4_CONN_NAND_DATA04 IMX8DXL_EMMC0_DATA4 1 195*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA4_LSIO_GPIO4_IO13 IMX8DXL_EMMC0_DATA4 4 196*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8DXL_EMMC0_DATA5 0 197*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA5_CONN_NAND_DATA05 IMX8DXL_EMMC0_DATA5 1 198*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA5_LSIO_GPIO4_IO14 IMX8DXL_EMMC0_DATA5 4 199*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8DXL_EMMC0_DATA6 0 200*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA6_CONN_NAND_DATA06 IMX8DXL_EMMC0_DATA6 1 201*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA6_LSIO_GPIO4_IO15 IMX8DXL_EMMC0_DATA6 4 202*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8DXL_EMMC0_DATA7 0 203*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA7_CONN_NAND_DATA07 IMX8DXL_EMMC0_DATA7 1 204*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_DATA7_LSIO_GPIO4_IO16 IMX8DXL_EMMC0_DATA7 4 205*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8DXL_EMMC0_STROBE 0 206*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_STROBE_CONN_NAND_CLE IMX8DXL_EMMC0_STROBE 1 207*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_STROBE_LSIO_GPIO4_IO17 IMX8DXL_EMMC0_STROBE 4 208*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8DXL_EMMC0_RESET_B 0 209*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_RESET_B_CONN_NAND_WP_B IMX8DXL_EMMC0_RESET_B 1 210*f9a8744dSAnson Huang #define IMX8DXL_EMMC0_RESET_B_LSIO_GPIO4_IO18 IMX8DXL_EMMC0_RESET_B 4 211*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8DXL_USDHC1_RESET_B 0 212*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_RESET_B_CONN_NAND_RE_N IMX8DXL_USDHC1_RESET_B 1 213*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK IMX8DXL_USDHC1_RESET_B 2 214*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_RESET_B_CONN_NAND_WE_B IMX8DXL_USDHC1_RESET_B 3 215*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO4_IO19 IMX8DXL_USDHC1_RESET_B 4 216*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO7_IO08 IMX8DXL_USDHC1_RESET_B 5 217*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8DXL_USDHC1_VSELECT 0 218*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_P IMX8DXL_USDHC1_VSELECT 1 219*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO IMX8DXL_USDHC1_VSELECT 2 220*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_B IMX8DXL_USDHC1_VSELECT 3 221*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO4_IO20 IMX8DXL_USDHC1_VSELECT 4 222*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO7_IO09 IMX8DXL_USDHC1_VSELECT 5 223*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_WP_CONN_USDHC1_WP IMX8DXL_USDHC1_WP 0 224*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_WP_CONN_NAND_DQS_N IMX8DXL_USDHC1_WP 1 225*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI IMX8DXL_USDHC1_WP 2 226*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_WP_CONN_NAND_ALE IMX8DXL_USDHC1_WP 3 227*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_WP_LSIO_GPIO4_IO21 IMX8DXL_USDHC1_WP 4 228*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_WP_LSIO_GPIO7_IO10 IMX8DXL_USDHC1_WP 5 229*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_CD_B_CONN_USDHC1_CD_B IMX8DXL_USDHC1_CD_B 0 230*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS_P IMX8DXL_USDHC1_CD_B 1 231*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_CD_B_ADMA_SPI2_CS0 IMX8DXL_USDHC1_CD_B 2 232*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS IMX8DXL_USDHC1_CD_B 3 233*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 IMX8DXL_USDHC1_CD_B 4 234*f9a8744dSAnson Huang #define IMX8DXL_USDHC1_CD_B_LSIO_GPIO7_IO11 IMX8DXL_USDHC1_CD_B 5 235*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8DXL_ENET0_RGMII_TXC 0 236*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8DXL_ENET0_RGMII_TXC 1 237*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8DXL_ENET0_RGMII_TXC 2 238*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXC_CONN_NAND_CE1_B IMX8DXL_ENET0_RGMII_TXC 3 239*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 IMX8DXL_ENET0_RGMII_TXC 4 240*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK IMX8DXL_ENET0_RGMII_TXC 5 241*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8DXL_ENET0_RGMII_TX_CTL 0 242*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B IMX8DXL_ENET0_RGMII_TX_CTL 3 243*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 IMX8DXL_ENET0_RGMII_TX_CTL 4 244*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD IMX8DXL_ENET0_RGMII_TX_CTL 5 245*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8DXL_ENET0_RGMII_TXD0 0 246*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT IMX8DXL_ENET0_RGMII_TXD0 3 247*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 IMX8DXL_ENET0_RGMII_TXD0 4 248*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 IMX8DXL_ENET0_RGMII_TXD0 5 249*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8DXL_ENET0_RGMII_TXD1 0 250*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC1_WP IMX8DXL_ENET0_RGMII_TXD1 3 251*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 IMX8DXL_ENET0_RGMII_TXD1 4 252*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 IMX8DXL_ENET0_RGMII_TXD1 5 253*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8DXL_ENET0_RGMII_TXD2 0 254*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD2_CONN_NAND_CE0_B IMX8DXL_ENET0_RGMII_TXD2 2 255*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B IMX8DXL_ENET0_RGMII_TXD2 3 256*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 IMX8DXL_ENET0_RGMII_TXD2 4 257*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 IMX8DXL_ENET0_RGMII_TXD2 5 258*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8DXL_ENET0_RGMII_TXD3 0 259*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD3_CONN_NAND_RE_B IMX8DXL_ENET0_RGMII_TXD3 2 260*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 IMX8DXL_ENET0_RGMII_TXD3 4 261*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 IMX8DXL_ENET0_RGMII_TXD3 5 262*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8DXL_ENET0_RGMII_RXC 0 263*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXC_CONN_NAND_WE_B IMX8DXL_ENET0_RGMII_RXC 2 264*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK IMX8DXL_ENET0_RGMII_RXC 3 265*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 IMX8DXL_ENET0_RGMII_RXC 4 266*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8DXL_ENET0_RGMII_RX_CTL 0 267*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD IMX8DXL_ENET0_RGMII_RX_CTL 3 268*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 IMX8DXL_ENET0_RGMII_RX_CTL 4 269*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8DXL_ENET0_RGMII_RXD0 0 270*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 IMX8DXL_ENET0_RGMII_RXD0 3 271*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 IMX8DXL_ENET0_RGMII_RXD0 4 272*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8DXL_ENET0_RGMII_RXD1 0 273*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 IMX8DXL_ENET0_RGMII_RXD1 3 274*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 IMX8DXL_ENET0_RGMII_RXD1 4 275*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8DXL_ENET0_RGMII_RXD2 0 276*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8DXL_ENET0_RGMII_RXD2 1 277*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 IMX8DXL_ENET0_RGMII_RXD2 3 278*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 IMX8DXL_ENET0_RGMII_RXD2 4 279*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8DXL_ENET0_RGMII_RXD3 0 280*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD3_CONN_NAND_ALE IMX8DXL_ENET0_RGMII_RXD3 2 281*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 IMX8DXL_ENET0_RGMII_RXD3 3 282*f9a8744dSAnson Huang #define IMX8DXL_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 IMX8DXL_ENET0_RGMII_RXD3 4 283*f9a8744dSAnson Huang #define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8DXL_ENET0_REFCLK_125M_25M 0 284*f9a8744dSAnson Huang #define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8DXL_ENET0_REFCLK_125M_25M 1 285*f9a8744dSAnson Huang #define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_IN IMX8DXL_ENET0_REFCLK_125M_25M 2 286*f9a8744dSAnson Huang #define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_OUT IMX8DXL_ENET0_REFCLK_125M_25M 3 287*f9a8744dSAnson Huang #define IMX8DXL_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 IMX8DXL_ENET0_REFCLK_125M_25M 4 288*f9a8744dSAnson Huang #define IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO IMX8DXL_ENET0_MDIO 0 289*f9a8744dSAnson Huang #define IMX8DXL_ENET0_MDIO_ADMA_I2C3_SDA IMX8DXL_ENET0_MDIO 1 290*f9a8744dSAnson Huang #define IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO IMX8DXL_ENET0_MDIO 2 291*f9a8744dSAnson Huang #define IMX8DXL_ENET0_MDIO_LSIO_GPIO5_IO10 IMX8DXL_ENET0_MDIO 4 292*f9a8744dSAnson Huang #define IMX8DXL_ENET0_MDIO_LSIO_GPIO7_IO16 IMX8DXL_ENET0_MDIO 5 293*f9a8744dSAnson Huang #define IMX8DXL_ENET0_MDC_CONN_ENET0_MDC IMX8DXL_ENET0_MDC 0 294*f9a8744dSAnson Huang #define IMX8DXL_ENET0_MDC_ADMA_I2C3_SCL IMX8DXL_ENET0_MDC 1 295*f9a8744dSAnson Huang #define IMX8DXL_ENET0_MDC_CONN_EQOS_MDC IMX8DXL_ENET0_MDC 2 296*f9a8744dSAnson Huang #define IMX8DXL_ENET0_MDC_LSIO_GPIO5_IO11 IMX8DXL_ENET0_MDC 4 297*f9a8744dSAnson Huang #define IMX8DXL_ENET0_MDC_LSIO_GPIO7_IO17 IMX8DXL_ENET0_MDC 5 298*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXC_LSIO_GPIO0_IO00 IMX8DXL_ENET1_RGMII_TXC 0 299*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_OUT IMX8DXL_ENET1_RGMII_TXC 1 300*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXC_ADMA_LCDIF_D00 IMX8DXL_ENET1_RGMII_TXC 2 301*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC IMX8DXL_ENET1_RGMII_TXC 3 302*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_IN IMX8DXL_ENET1_RGMII_TXC 4 303*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD2_ADMA_LCDIF_D01 IMX8DXL_ENET1_RGMII_TXD2 2 304*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 IMX8DXL_ENET1_RGMII_TXD2 3 305*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD2_LSIO_GPIO0_IO01 IMX8DXL_ENET1_RGMII_TXD2 4 306*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TX_CTL_ADMA_LCDIF_D02 IMX8DXL_ENET1_RGMII_TX_CTL 2 307*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL IMX8DXL_ENET1_RGMII_TX_CTL 3 308*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TX_CTL_LSIO_GPIO0_IO02 IMX8DXL_ENET1_RGMII_TX_CTL 4 309*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD3_ADMA_LCDIF_D03 IMX8DXL_ENET1_RGMII_TXD3 2 310*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 IMX8DXL_ENET1_RGMII_TXD3 3 311*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD3_LSIO_GPIO0_IO03 IMX8DXL_ENET1_RGMII_TXD3 4 312*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXC_ADMA_LCDIF_D04 IMX8DXL_ENET1_RGMII_RXC 2 313*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC IMX8DXL_ENET1_RGMII_RXC 3 314*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXC_LSIO_GPIO0_IO04 IMX8DXL_ENET1_RGMII_RXC 4 315*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD3_ADMA_LCDIF_D05 IMX8DXL_ENET1_RGMII_RXD3 2 316*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 IMX8DXL_ENET1_RGMII_RXD3 3 317*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD3_LSIO_GPIO0_IO05 IMX8DXL_ENET1_RGMII_RXD3 4 318*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD2_ADMA_LCDIF_D06 IMX8DXL_ENET1_RGMII_RXD2 2 319*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 IMX8DXL_ENET1_RGMII_RXD2 3 320*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO0_IO06 IMX8DXL_ENET1_RGMII_RXD2 4 321*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO6_IO00 IMX8DXL_ENET1_RGMII_RXD2 5 322*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD1_ADMA_LCDIF_D07 IMX8DXL_ENET1_RGMII_RXD1 2 323*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 IMX8DXL_ENET1_RGMII_RXD1 3 324*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO0_IO07 IMX8DXL_ENET1_RGMII_RXD1 4 325*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO6_IO01 IMX8DXL_ENET1_RGMII_RXD1 5 326*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD0_ADMA_LCDIF_D08 IMX8DXL_ENET1_RGMII_TXD0 2 327*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 IMX8DXL_ENET1_RGMII_TXD0 3 328*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO0_IO08 IMX8DXL_ENET1_RGMII_TXD0 4 329*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO6_IO02 IMX8DXL_ENET1_RGMII_TXD0 5 330*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD1_ADMA_LCDIF_D09 IMX8DXL_ENET1_RGMII_TXD1 2 331*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 IMX8DXL_ENET1_RGMII_TXD1 3 332*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO0_IO09 IMX8DXL_ENET1_RGMII_TXD1 4 333*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO6_IO03 IMX8DXL_ENET1_RGMII_TXD1 5 334*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD0_ADMA_SPDIF0_RX IMX8DXL_ENET1_RGMII_RXD0 0 335*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD0_ADMA_MQS_R IMX8DXL_ENET1_RGMII_RXD0 1 336*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD0_ADMA_LCDIF_D10 IMX8DXL_ENET1_RGMII_RXD0 2 337*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 IMX8DXL_ENET1_RGMII_RXD0 3 338*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO0_IO10 IMX8DXL_ENET1_RGMII_RXD0 4 339*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO6_IO04 IMX8DXL_ENET1_RGMII_RXD0 5 340*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_SPDIF0_TX IMX8DXL_ENET1_RGMII_RX_CTL 0 341*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_MQS_L IMX8DXL_ENET1_RGMII_RX_CTL 1 342*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_LCDIF_D11 IMX8DXL_ENET1_RGMII_RX_CTL 2 343*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL IMX8DXL_ENET1_RGMII_RX_CTL 3 344*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO0_IO11 IMX8DXL_ENET1_RGMII_RX_CTL 4 345*f9a8744dSAnson Huang #define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO05 IMX8DXL_ENET1_RGMII_RX_CTL 5 346*f9a8744dSAnson Huang #define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_SPDIF0_EXT_CLK IMX8DXL_ENET1_REFCLK_125M_25M 0 347*f9a8744dSAnson Huang #define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_LCDIF_D12 IMX8DXL_ENET1_REFCLK_125M_25M 2 348*f9a8744dSAnson Huang #define IMX8DXL_ENET1_REFCLK_125M_25M_CONN_EQOS_REFCLK_125M_25M IMX8DXL_ENET1_REFCLK_125M_25M 3 349*f9a8744dSAnson Huang #define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPIO0_IO12 IMX8DXL_ENET1_REFCLK_125M_25M 4 350*f9a8744dSAnson Huang #define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPIO6_IO06 IMX8DXL_ENET1_REFCLK_125M_25M 5 351*f9a8744dSAnson Huang #define IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK IMX8DXL_SPI3_SCK 0 352*f9a8744dSAnson Huang #define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D13 IMX8DXL_SPI3_SCK 2 353*f9a8744dSAnson Huang #define IMX8DXL_SPI3_SCK_LSIO_GPIO0_IO13 IMX8DXL_SPI3_SCK 4 354*f9a8744dSAnson Huang #define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D00 IMX8DXL_SPI3_SCK 5 355*f9a8744dSAnson Huang #define IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO IMX8DXL_SPI3_SDO 0 356*f9a8744dSAnson Huang #define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D14 IMX8DXL_SPI3_SDO 2 357*f9a8744dSAnson Huang #define IMX8DXL_SPI3_SDO_LSIO_GPIO0_IO14 IMX8DXL_SPI3_SDO 4 358*f9a8744dSAnson Huang #define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D01 IMX8DXL_SPI3_SDO 5 359*f9a8744dSAnson Huang #define IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI IMX8DXL_SPI3_SDI 0 360*f9a8744dSAnson Huang #define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D15 IMX8DXL_SPI3_SDI 2 361*f9a8744dSAnson Huang #define IMX8DXL_SPI3_SDI_LSIO_GPIO0_IO15 IMX8DXL_SPI3_SDI 4 362*f9a8744dSAnson Huang #define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D02 IMX8DXL_SPI3_SDI 5 363*f9a8744dSAnson Huang #define IMX8DXL_SPI3_CS0_ADMA_SPI3_CS0 IMX8DXL_SPI3_CS0 0 364*f9a8744dSAnson Huang #define IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 IMX8DXL_SPI3_CS0 1 365*f9a8744dSAnson Huang #define IMX8DXL_SPI3_CS0_ADMA_LCDIF_HSYNC IMX8DXL_SPI3_CS0 2 366*f9a8744dSAnson Huang #define IMX8DXL_SPI3_CS0_LSIO_GPIO0_IO16 IMX8DXL_SPI3_CS0 4 367*f9a8744dSAnson Huang #define IMX8DXL_SPI3_CS0_ADMA_LCDIF_CS IMX8DXL_SPI3_CS0 5 368*f9a8744dSAnson Huang #define IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 IMX8DXL_SPI3_CS1 0 369*f9a8744dSAnson Huang #define IMX8DXL_SPI3_CS1_ADMA_I2C3_SCL IMX8DXL_SPI3_CS1 1 370*f9a8744dSAnson Huang #define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RESET IMX8DXL_SPI3_CS1 2 371*f9a8744dSAnson Huang #define IMX8DXL_SPI3_CS1_ADMA_SPI2_CS0 IMX8DXL_SPI3_CS1 3 372*f9a8744dSAnson Huang #define IMX8DXL_SPI3_CS1_ADMA_LCDIF_D16 IMX8DXL_SPI3_CS1 4 373*f9a8744dSAnson Huang #define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RD_E IMX8DXL_SPI3_CS1 5 374*f9a8744dSAnson Huang #define IMX8DXL_MCLK_IN1_ADMA_ACM_MCLK_IN1 IMX8DXL_MCLK_IN1 0 375*f9a8744dSAnson Huang #define IMX8DXL_MCLK_IN1_ADMA_I2C3_SDA IMX8DXL_MCLK_IN1 1 376*f9a8744dSAnson Huang #define IMX8DXL_MCLK_IN1_ADMA_LCDIF_EN IMX8DXL_MCLK_IN1 2 377*f9a8744dSAnson Huang #define IMX8DXL_MCLK_IN1_ADMA_SPI2_SCK IMX8DXL_MCLK_IN1 3 378*f9a8744dSAnson Huang #define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D17 IMX8DXL_MCLK_IN1 4 379*f9a8744dSAnson Huang #define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D03 IMX8DXL_MCLK_IN1 5 380*f9a8744dSAnson Huang #define IMX8DXL_MCLK_IN0_ADMA_ACM_MCLK_IN0 IMX8DXL_MCLK_IN0 0 381*f9a8744dSAnson Huang #define IMX8DXL_MCLK_IN0_ADMA_LCDIF_VSYNC IMX8DXL_MCLK_IN0 2 382*f9a8744dSAnson Huang #define IMX8DXL_MCLK_IN0_ADMA_SPI2_SDI IMX8DXL_MCLK_IN0 3 383*f9a8744dSAnson Huang #define IMX8DXL_MCLK_IN0_LSIO_GPIO0_IO19 IMX8DXL_MCLK_IN0 4 384*f9a8744dSAnson Huang #define IMX8DXL_MCLK_IN0_ADMA_LCDIF_RS IMX8DXL_MCLK_IN0 5 385*f9a8744dSAnson Huang #define IMX8DXL_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 IMX8DXL_MCLK_OUT0 0 386*f9a8744dSAnson Huang #define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_CLK IMX8DXL_MCLK_OUT0 2 387*f9a8744dSAnson Huang #define IMX8DXL_MCLK_OUT0_ADMA_SPI2_SDO IMX8DXL_MCLK_OUT0 3 388*f9a8744dSAnson Huang #define IMX8DXL_MCLK_OUT0_LSIO_GPIO0_IO20 IMX8DXL_MCLK_OUT0 4 389*f9a8744dSAnson Huang #define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_WR_RWN IMX8DXL_MCLK_OUT0 5 390*f9a8744dSAnson Huang #define IMX8DXL_UART1_TX_ADMA_UART1_TX IMX8DXL_UART1_TX 0 391*f9a8744dSAnson Huang #define IMX8DXL_UART1_TX_LSIO_PWM0_OUT IMX8DXL_UART1_TX 1 392*f9a8744dSAnson Huang #define IMX8DXL_UART1_TX_LSIO_GPT0_CAPTURE IMX8DXL_UART1_TX 2 393*f9a8744dSAnson Huang #define IMX8DXL_UART1_TX_LSIO_GPIO0_IO21 IMX8DXL_UART1_TX 4 394*f9a8744dSAnson Huang #define IMX8DXL_UART1_TX_ADMA_LCDIF_D04 IMX8DXL_UART1_TX 5 395*f9a8744dSAnson Huang #define IMX8DXL_UART1_RX_ADMA_UART1_RX IMX8DXL_UART1_RX 0 396*f9a8744dSAnson Huang #define IMX8DXL_UART1_RX_LSIO_PWM1_OUT IMX8DXL_UART1_RX 1 397*f9a8744dSAnson Huang #define IMX8DXL_UART1_RX_LSIO_GPT0_COMPARE IMX8DXL_UART1_RX 2 398*f9a8744dSAnson Huang #define IMX8DXL_UART1_RX_LSIO_GPT1_CLK IMX8DXL_UART1_RX 3 399*f9a8744dSAnson Huang #define IMX8DXL_UART1_RX_LSIO_GPIO0_IO22 IMX8DXL_UART1_RX 4 400*f9a8744dSAnson Huang #define IMX8DXL_UART1_RX_ADMA_LCDIF_D05 IMX8DXL_UART1_RX 5 401*f9a8744dSAnson Huang #define IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B IMX8DXL_UART1_RTS_B 0 402*f9a8744dSAnson Huang #define IMX8DXL_UART1_RTS_B_LSIO_PWM2_OUT IMX8DXL_UART1_RTS_B 1 403*f9a8744dSAnson Huang #define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D16 IMX8DXL_UART1_RTS_B 2 404*f9a8744dSAnson Huang #define IMX8DXL_UART1_RTS_B_LSIO_GPT1_CAPTURE IMX8DXL_UART1_RTS_B 3 405*f9a8744dSAnson Huang #define IMX8DXL_UART1_RTS_B_LSIO_GPT0_CLK IMX8DXL_UART1_RTS_B 4 406*f9a8744dSAnson Huang #define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D06 IMX8DXL_UART1_RTS_B 5 407*f9a8744dSAnson Huang #define IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B IMX8DXL_UART1_CTS_B 0 408*f9a8744dSAnson Huang #define IMX8DXL_UART1_CTS_B_LSIO_PWM3_OUT IMX8DXL_UART1_CTS_B 1 409*f9a8744dSAnson Huang #define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D17 IMX8DXL_UART1_CTS_B 2 410*f9a8744dSAnson Huang #define IMX8DXL_UART1_CTS_B_LSIO_GPT1_COMPARE IMX8DXL_UART1_CTS_B 3 411*f9a8744dSAnson Huang #define IMX8DXL_UART1_CTS_B_LSIO_GPIO0_IO24 IMX8DXL_UART1_CTS_B 4 412*f9a8744dSAnson Huang #define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D07 IMX8DXL_UART1_CTS_B 5 413*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SCK_ADMA_SPI0_SCK IMX8DXL_SPI0_SCK 0 414*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC IMX8DXL_SPI0_SCK 1 415*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SCK_M40_I2C0_SCL IMX8DXL_SPI0_SCK 2 416*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SCK_M40_GPIO0_IO00 IMX8DXL_SPI0_SCK 3 417*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SCK_LSIO_GPIO1_IO04 IMX8DXL_SPI0_SCK 4 418*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SCK_ADMA_LCDIF_D08 IMX8DXL_SPI0_SCK 5 419*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SDI_ADMA_SPI0_SDI IMX8DXL_SPI0_SDI 0 420*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD IMX8DXL_SPI0_SDI 1 421*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SDI_M40_TPM0_CH0 IMX8DXL_SPI0_SDI 2 422*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SDI_M40_GPIO0_IO02 IMX8DXL_SPI0_SDI 3 423*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SDI_LSIO_GPIO1_IO05 IMX8DXL_SPI0_SDI 4 424*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SDI_ADMA_LCDIF_D09 IMX8DXL_SPI0_SDI 5 425*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SDO_ADMA_SPI0_SDO IMX8DXL_SPI0_SDO 0 426*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS IMX8DXL_SPI0_SDO 1 427*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SDO_M40_I2C0_SDA IMX8DXL_SPI0_SDO 2 428*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SDO_M40_GPIO0_IO01 IMX8DXL_SPI0_SDO 3 429*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SDO_LSIO_GPIO1_IO06 IMX8DXL_SPI0_SDO 4 430*f9a8744dSAnson Huang #define IMX8DXL_SPI0_SDO_ADMA_LCDIF_D10 IMX8DXL_SPI0_SDO 5 431*f9a8744dSAnson Huang #define IMX8DXL_SPI0_CS1_ADMA_SPI0_CS1 IMX8DXL_SPI0_CS1 0 432*f9a8744dSAnson Huang #define IMX8DXL_SPI0_CS1_ADMA_SAI0_RXC IMX8DXL_SPI0_CS1 1 433*f9a8744dSAnson Huang #define IMX8DXL_SPI0_CS1_ADMA_SAI1_TXD IMX8DXL_SPI0_CS1 2 434*f9a8744dSAnson Huang #define IMX8DXL_SPI0_CS1_ADMA_LCD_PWM0_OUT IMX8DXL_SPI0_CS1 3 435*f9a8744dSAnson Huang #define IMX8DXL_SPI0_CS1_LSIO_GPIO1_IO07 IMX8DXL_SPI0_CS1 4 436*f9a8744dSAnson Huang #define IMX8DXL_SPI0_CS1_ADMA_LCDIF_D11 IMX8DXL_SPI0_CS1 5 437*f9a8744dSAnson Huang #define IMX8DXL_SPI0_CS0_ADMA_SPI0_CS0 IMX8DXL_SPI0_CS0 0 438*f9a8744dSAnson Huang #define IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD IMX8DXL_SPI0_CS0 1 439*f9a8744dSAnson Huang #define IMX8DXL_SPI0_CS0_M40_TPM0_CH1 IMX8DXL_SPI0_CS0 2 440*f9a8744dSAnson Huang #define IMX8DXL_SPI0_CS0_M40_GPIO0_IO03 IMX8DXL_SPI0_CS0 3 441*f9a8744dSAnson Huang #define IMX8DXL_SPI0_CS0_LSIO_GPIO1_IO08 IMX8DXL_SPI0_CS0 4 442*f9a8744dSAnson Huang #define IMX8DXL_SPI0_CS0_ADMA_LCDIF_D12 IMX8DXL_SPI0_CS0 5 443*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN1_ADMA_ADC_IN1 IMX8DXL_ADC_IN1 0 444*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN1_M40_I2C0_SDA IMX8DXL_ADC_IN1 1 445*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN1_M40_GPIO0_IO01 IMX8DXL_ADC_IN1 2 446*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN1_ADMA_I2C0_SDA IMX8DXL_ADC_IN1 3 447*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09 IMX8DXL_ADC_IN1 4 448*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN1_ADMA_LCDIF_D13 IMX8DXL_ADC_IN1 5 449*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN0_ADMA_ADC_IN0 IMX8DXL_ADC_IN0 0 450*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN0_M40_I2C0_SCL IMX8DXL_ADC_IN0 1 451*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN0_M40_GPIO0_IO00 IMX8DXL_ADC_IN0 2 452*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN0_ADMA_I2C0_SCL IMX8DXL_ADC_IN0 3 453*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10 IMX8DXL_ADC_IN0 4 454*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN0_ADMA_LCDIF_D14 IMX8DXL_ADC_IN0 5 455*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN3_ADMA_ADC_IN3 IMX8DXL_ADC_IN3 0 456*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN3_M40_UART0_TX IMX8DXL_ADC_IN3 1 457*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN3_M40_GPIO0_IO03 IMX8DXL_ADC_IN3 2 458*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN3_ADMA_ACM_MCLK_OUT0 IMX8DXL_ADC_IN3 3 459*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN3_LSIO_GPIO1_IO11 IMX8DXL_ADC_IN3 4 460*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN3_ADMA_LCDIF_D15 IMX8DXL_ADC_IN3 5 461*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN2_ADMA_ADC_IN2 IMX8DXL_ADC_IN2 0 462*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN2_M40_UART0_RX IMX8DXL_ADC_IN2 1 463*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN2_M40_GPIO0_IO02 IMX8DXL_ADC_IN2 2 464*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN2_ADMA_ACM_MCLK_IN0 IMX8DXL_ADC_IN2 3 465*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN2_LSIO_GPIO1_IO12 IMX8DXL_ADC_IN2 4 466*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN2_ADMA_LCDIF_D16 IMX8DXL_ADC_IN2 5 467*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN5_ADMA_ADC_IN5 IMX8DXL_ADC_IN5 0 468*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN5_M40_TPM0_CH1 IMX8DXL_ADC_IN5 1 469*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN5_M40_GPIO0_IO05 IMX8DXL_ADC_IN5 2 470*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN5_ADMA_LCDIF_LCDBUSY IMX8DXL_ADC_IN5 3 471*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13 IMX8DXL_ADC_IN5 4 472*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN5_ADMA_LCDIF_D17 IMX8DXL_ADC_IN5 5 473*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN4_ADMA_ADC_IN4 IMX8DXL_ADC_IN4 0 474*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN4_M40_TPM0_CH0 IMX8DXL_ADC_IN4 1 475*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN4_M40_GPIO0_IO04 IMX8DXL_ADC_IN4 2 476*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN4_ADMA_LCDIF_LCDRESET IMX8DXL_ADC_IN4 3 477*f9a8744dSAnson Huang #define IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14 IMX8DXL_ADC_IN4 4 478*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN0_RX_ADMA_FLEXCAN0_RX IMX8DXL_FLEXCAN0_RX 0 479*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN0_RX_ADMA_SAI2_RXC IMX8DXL_FLEXCAN0_RX 1 480*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN0_RX_ADMA_UART0_RTS_B IMX8DXL_FLEXCAN0_RX 2 481*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC IMX8DXL_FLEXCAN0_RX 3 482*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO1_IO15 IMX8DXL_FLEXCAN0_RX 4 483*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO6_IO08 IMX8DXL_FLEXCAN0_RX 5 484*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN0_TX_ADMA_FLEXCAN0_TX IMX8DXL_FLEXCAN0_TX 0 485*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN0_TX_ADMA_SAI2_RXD IMX8DXL_FLEXCAN0_TX 1 486*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN0_TX_ADMA_UART0_CTS_B IMX8DXL_FLEXCAN0_TX 2 487*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS IMX8DXL_FLEXCAN0_TX 3 488*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO1_IO16 IMX8DXL_FLEXCAN0_TX 4 489*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO6_IO09 IMX8DXL_FLEXCAN0_TX 5 490*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN1_RX_ADMA_FLEXCAN1_RX IMX8DXL_FLEXCAN1_RX 0 491*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN1_RX_ADMA_SAI2_RXFS IMX8DXL_FLEXCAN1_RX 1 492*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN1_RX_ADMA_FTM_CH2 IMX8DXL_FLEXCAN1_RX 2 493*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD IMX8DXL_FLEXCAN1_RX 3 494*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO1_IO17 IMX8DXL_FLEXCAN1_RX 4 495*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO6_IO10 IMX8DXL_FLEXCAN1_RX 5 496*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN1_TX_ADMA_FLEXCAN1_TX IMX8DXL_FLEXCAN1_TX 0 497*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN1_TX_ADMA_SAI3_RXC IMX8DXL_FLEXCAN1_TX 1 498*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 IMX8DXL_FLEXCAN1_TX 2 499*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD IMX8DXL_FLEXCAN1_TX 3 500*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO1_IO18 IMX8DXL_FLEXCAN1_TX 4 501*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO6_IO11 IMX8DXL_FLEXCAN1_TX 5 502*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX IMX8DXL_FLEXCAN2_RX 0 503*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN2_RX_ADMA_SAI3_RXD IMX8DXL_FLEXCAN2_RX 1 504*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN2_RX_ADMA_UART3_RX IMX8DXL_FLEXCAN2_RX 2 505*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN2_RX_ADMA_SAI1_RXFS IMX8DXL_FLEXCAN2_RX 3 506*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO1_IO19 IMX8DXL_FLEXCAN2_RX 4 507*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO6_IO12 IMX8DXL_FLEXCAN2_RX 5 508*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX IMX8DXL_FLEXCAN2_TX 0 509*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN2_TX_ADMA_SAI3_RXFS IMX8DXL_FLEXCAN2_TX 1 510*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN2_TX_ADMA_UART3_TX IMX8DXL_FLEXCAN2_TX 2 511*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN2_TX_ADMA_SAI1_RXC IMX8DXL_FLEXCAN2_TX 3 512*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO1_IO20 IMX8DXL_FLEXCAN2_TX 4 513*f9a8744dSAnson Huang #define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO6_IO13 IMX8DXL_FLEXCAN2_TX 5 514*f9a8744dSAnson Huang #define IMX8DXL_UART0_RX_ADMA_UART0_RX IMX8DXL_UART0_RX 0 515*f9a8744dSAnson Huang #define IMX8DXL_UART0_RX_ADMA_MQS_R IMX8DXL_UART0_RX 1 516*f9a8744dSAnson Huang #define IMX8DXL_UART0_RX_ADMA_FLEXCAN0_RX IMX8DXL_UART0_RX 2 517*f9a8744dSAnson Huang #define IMX8DXL_UART0_RX_SCU_UART0_RX IMX8DXL_UART0_RX 3 518*f9a8744dSAnson Huang #define IMX8DXL_UART0_RX_LSIO_GPIO1_IO21 IMX8DXL_UART0_RX 4 519*f9a8744dSAnson Huang #define IMX8DXL_UART0_RX_LSIO_GPIO6_IO14 IMX8DXL_UART0_RX 5 520*f9a8744dSAnson Huang #define IMX8DXL_UART0_TX_ADMA_UART0_TX IMX8DXL_UART0_TX 0 521*f9a8744dSAnson Huang #define IMX8DXL_UART0_TX_ADMA_MQS_L IMX8DXL_UART0_TX 1 522*f9a8744dSAnson Huang #define IMX8DXL_UART0_TX_ADMA_FLEXCAN0_TX IMX8DXL_UART0_TX 2 523*f9a8744dSAnson Huang #define IMX8DXL_UART0_TX_SCU_UART0_TX IMX8DXL_UART0_TX 3 524*f9a8744dSAnson Huang #define IMX8DXL_UART0_TX_LSIO_GPIO1_IO22 IMX8DXL_UART0_TX 4 525*f9a8744dSAnson Huang #define IMX8DXL_UART0_TX_LSIO_GPIO6_IO15 IMX8DXL_UART0_TX 5 526*f9a8744dSAnson Huang #define IMX8DXL_UART2_TX_ADMA_UART2_TX IMX8DXL_UART2_TX 0 527*f9a8744dSAnson Huang #define IMX8DXL_UART2_TX_ADMA_FTM_CH1 IMX8DXL_UART2_TX 1 528*f9a8744dSAnson Huang #define IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX IMX8DXL_UART2_TX 2 529*f9a8744dSAnson Huang #define IMX8DXL_UART2_TX_LSIO_GPIO1_IO23 IMX8DXL_UART2_TX 4 530*f9a8744dSAnson Huang #define IMX8DXL_UART2_TX_LSIO_GPIO6_IO16 IMX8DXL_UART2_TX 5 531*f9a8744dSAnson Huang #define IMX8DXL_UART2_RX_ADMA_UART2_RX IMX8DXL_UART2_RX 0 532*f9a8744dSAnson Huang #define IMX8DXL_UART2_RX_ADMA_FTM_CH0 IMX8DXL_UART2_RX 1 533*f9a8744dSAnson Huang #define IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX IMX8DXL_UART2_RX 2 534*f9a8744dSAnson Huang #define IMX8DXL_UART2_RX_LSIO_GPIO1_IO24 IMX8DXL_UART2_RX 4 535*f9a8744dSAnson Huang #define IMX8DXL_UART2_RX_LSIO_GPIO6_IO17 IMX8DXL_UART2_RX 5 536*f9a8744dSAnson Huang #define IMX8DXL_JTAG_TRST_B_SCU_JTAG_TRST_B IMX8DXL_JTAG_TRST_B 0 537*f9a8744dSAnson Huang #define IMX8DXL_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT IMX8DXL_JTAG_TRST_B 1 538*f9a8744dSAnson Huang #define IMX8DXL_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8DXL_PMIC_I2C_SCL 0 539*f9a8744dSAnson Huang #define IMX8DXL_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON IMX8DXL_PMIC_I2C_SCL 1 540*f9a8744dSAnson Huang #define IMX8DXL_PMIC_I2C_SCL_LSIO_GPIO2_IO01 IMX8DXL_PMIC_I2C_SCL 4 541*f9a8744dSAnson Huang #define IMX8DXL_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8DXL_PMIC_I2C_SDA 0 542*f9a8744dSAnson Huang #define IMX8DXL_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON IMX8DXL_PMIC_I2C_SDA 1 543*f9a8744dSAnson Huang #define IMX8DXL_PMIC_I2C_SDA_LSIO_GPIO2_IO02 IMX8DXL_PMIC_I2C_SDA 4 544*f9a8744dSAnson Huang #define IMX8DXL_PMIC_INT_B_SCU_DSC_PMIC_INT_B IMX8DXL_PMIC_INT_B 0 545*f9a8744dSAnson Huang #define IMX8DXL_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8DXL_SCU_GPIO0_00 0 546*f9a8744dSAnson Huang #define IMX8DXL_SCU_GPIO0_00_SCU_UART0_RX IMX8DXL_SCU_GPIO0_00 1 547*f9a8744dSAnson Huang #define IMX8DXL_SCU_GPIO0_00_M40_UART0_RX IMX8DXL_SCU_GPIO0_00 2 548*f9a8744dSAnson Huang #define IMX8DXL_SCU_GPIO0_00_ADMA_UART3_RX IMX8DXL_SCU_GPIO0_00 3 549*f9a8744dSAnson Huang #define IMX8DXL_SCU_GPIO0_00_LSIO_GPIO2_IO03 IMX8DXL_SCU_GPIO0_00 4 550*f9a8744dSAnson Huang #define IMX8DXL_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8DXL_SCU_GPIO0_01 0 551*f9a8744dSAnson Huang #define IMX8DXL_SCU_GPIO0_01_SCU_UART0_TX IMX8DXL_SCU_GPIO0_01 1 552*f9a8744dSAnson Huang #define IMX8DXL_SCU_GPIO0_01_M40_UART0_TX IMX8DXL_SCU_GPIO0_01 2 553*f9a8744dSAnson Huang #define IMX8DXL_SCU_GPIO0_01_ADMA_UART3_TX IMX8DXL_SCU_GPIO0_01 3 554*f9a8744dSAnson Huang #define IMX8DXL_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT IMX8DXL_SCU_GPIO0_01 4 555*f9a8744dSAnson Huang #define IMX8DXL_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY IMX8DXL_SCU_PMIC_STANDBY 0 556*f9a8744dSAnson Huang #define IMX8DXL_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8DXL_SCU_BOOT_MODE1 0 557*f9a8744dSAnson Huang #define IMX8DXL_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8DXL_SCU_BOOT_MODE0 0 558*f9a8744dSAnson Huang #define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8DXL_SCU_BOOT_MODE2 0 559*f9a8744dSAnson Huang #define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8DXL_SCU_BOOT_MODE2 1 560*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN IMX8DXL_SNVS_TAMPER_OUT1 4 561*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO6_IO19_IN IMX8DXL_SNVS_TAMPER_OUT1 5 562*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN IMX8DXL_SNVS_TAMPER_OUT2 4 563*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO6_IO20_IN IMX8DXL_SNVS_TAMPER_OUT2 5 564*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC IMX8DXL_SNVS_TAMPER_OUT3 2 565*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO2_IO07_IN IMX8DXL_SNVS_TAMPER_OUT3 4 566*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO6_IO21_IN IMX8DXL_SNVS_TAMPER_OUT3 5 567*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD IMX8DXL_SNVS_TAMPER_OUT4 2 568*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN IMX8DXL_SNVS_TAMPER_OUT4 4 569*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO6_IO22_IN IMX8DXL_SNVS_TAMPER_OUT4 5 570*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS IMX8DXL_SNVS_TAMPER_IN0 2 571*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN IMX8DXL_SNVS_TAMPER_IN0 4 572*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO6_IO23_IN IMX8DXL_SNVS_TAMPER_IN0 5 573*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC IMX8DXL_SNVS_TAMPER_IN1 2 574*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN IMX8DXL_SNVS_TAMPER_IN1 4 575*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO6_IO24_IN IMX8DXL_SNVS_TAMPER_IN1 5 576*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD IMX8DXL_SNVS_TAMPER_IN2 2 577*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN IMX8DXL_SNVS_TAMPER_IN2 4 578*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO6_IO25_IN IMX8DXL_SNVS_TAMPER_IN2 5 579*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS IMX8DXL_SNVS_TAMPER_IN3 2 580*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO2_IO12_IN IMX8DXL_SNVS_TAMPER_IN3 4 581*f9a8744dSAnson Huang #define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO6_IO26_IN IMX8DXL_SNVS_TAMPER_IN3 5 582*f9a8744dSAnson Huang #define IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA IMX8DXL_SPI1_SCK 2 583*f9a8744dSAnson Huang #define IMX8DXL_SPI1_SCK_ADMA_SPI1_SCK IMX8DXL_SPI1_SCK 3 584*f9a8744dSAnson Huang #define IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00 IMX8DXL_SPI1_SCK 4 585*f9a8744dSAnson Huang #define IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL IMX8DXL_SPI1_SDO 2 586*f9a8744dSAnson Huang #define IMX8DXL_SPI1_SDO_ADMA_SPI1_SDO IMX8DXL_SPI1_SDO 3 587*f9a8744dSAnson Huang #define IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01 IMX8DXL_SPI1_SDO 4 588*f9a8744dSAnson Huang #define IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL IMX8DXL_SPI1_SDI 2 589*f9a8744dSAnson Huang #define IMX8DXL_SPI1_SDI_ADMA_SPI1_SDI IMX8DXL_SPI1_SDI 3 590*f9a8744dSAnson Huang #define IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02 IMX8DXL_SPI1_SDI 4 591*f9a8744dSAnson Huang #define IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA IMX8DXL_SPI1_CS0 2 592*f9a8744dSAnson Huang #define IMX8DXL_SPI1_CS0_ADMA_SPI1_CS0 IMX8DXL_SPI1_CS0 3 593*f9a8744dSAnson Huang #define IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 IMX8DXL_SPI1_CS0 4 594*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8DXL_QSPI0A_DATA1 0 595*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_DATA1_LSIO_GPIO3_IO10 IMX8DXL_QSPI0A_DATA1 4 596*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8DXL_QSPI0A_DATA0 0 597*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_DATA0_LSIO_GPIO3_IO09 IMX8DXL_QSPI0A_DATA0 4 598*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8DXL_QSPI0A_DATA3 0 599*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_DATA3_LSIO_GPIO3_IO12 IMX8DXL_QSPI0A_DATA3 4 600*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8DXL_QSPI0A_DATA2 0 601*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_DATA2_LSIO_GPIO3_IO11 IMX8DXL_QSPI0A_DATA2 4 602*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8DXL_QSPI0A_SS0_B 0 603*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_SS0_B_LSIO_GPIO3_IO14 IMX8DXL_QSPI0A_SS0_B 4 604*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8DXL_QSPI0A_DQS 0 605*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_DQS_LSIO_GPIO3_IO13 IMX8DXL_QSPI0A_DQS 4 606*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8DXL_QSPI0A_SCLK 0 607*f9a8744dSAnson Huang #define IMX8DXL_QSPI0A_SCLK_LSIO_GPIO3_IO16 IMX8DXL_QSPI0A_SCLK 4 608*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8DXL_QSPI0B_SCLK 0 609*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_SCLK_LSIO_GPIO3_IO17 IMX8DXL_QSPI0B_SCLK 4 610*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8DXL_QSPI0B_DQS 0 611*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_DQS_LSIO_GPIO3_IO22 IMX8DXL_QSPI0B_DQS 4 612*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8DXL_QSPI0B_DATA1 0 613*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19 IMX8DXL_QSPI0B_DATA1 4 614*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8DXL_QSPI0B_DATA0 0 615*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18 IMX8DXL_QSPI0B_DATA0 4 616*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8DXL_QSPI0B_DATA3 0 617*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21 IMX8DXL_QSPI0B_DATA3 4 618*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8DXL_QSPI0B_DATA2 0 619*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20 IMX8DXL_QSPI0B_DATA2 4 620*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8DXL_QSPI0B_SS0_B 0 621*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_SS0_B_LSIO_GPIO3_IO23 IMX8DXL_QSPI0B_SS0_B 4 622*f9a8744dSAnson Huang #define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0A_SS1_B IMX8DXL_QSPI0B_SS0_B 5 623*f9a8744dSAnson Huang 624*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 625*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO_PAD IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 0 626*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0 627*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 628*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 629*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 630*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 631*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 632*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0 633*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 634*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 635*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0 636*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0 637*f9a8744dSAnson Huang #define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0 638*f9a8744dSAnson Huang 639*f9a8744dSAnson Huang #endif 640