1*956329ecSRohit Agarwal /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ 2*956329ecSRohit Agarwal /* 3*956329ecSRohit Agarwal * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4*956329ecSRohit Agarwal */ 5*956329ecSRohit Agarwal 6*956329ecSRohit Agarwal #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H 7*956329ecSRohit Agarwal #define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H 8*956329ecSRohit Agarwal 9*956329ecSRohit Agarwal #define MASTER_QPIC_CORE 0 10*956329ecSRohit Agarwal #define MASTER_QUP_CORE_0 1 11*956329ecSRohit Agarwal #define SLAVE_QPIC_CORE 2 12*956329ecSRohit Agarwal #define SLAVE_QUP_CORE_0 3 13*956329ecSRohit Agarwal 14*956329ecSRohit Agarwal #define MASTER_LLCC 0 15*956329ecSRohit Agarwal #define SLAVE_EBI1 1 16*956329ecSRohit Agarwal 17*956329ecSRohit Agarwal #define MASTER_CNOC_DC_NOC 0 18*956329ecSRohit Agarwal #define SLAVE_LAGG_CFG 1 19*956329ecSRohit Agarwal #define SLAVE_MCCC_MASTER 2 20*956329ecSRohit Agarwal #define SLAVE_GEM_NOC_CFG 3 21*956329ecSRohit Agarwal #define SLAVE_SNOOP_BWMON 4 22*956329ecSRohit Agarwal 23*956329ecSRohit Agarwal #define MASTER_SYS_TCU 0 24*956329ecSRohit Agarwal #define MASTER_APPSS_PROC 1 25*956329ecSRohit Agarwal #define MASTER_GEM_NOC_CFG 2 26*956329ecSRohit Agarwal #define MASTER_MSS_PROC 3 27*956329ecSRohit Agarwal #define MASTER_ANOC_PCIE_GEM_NOC 4 28*956329ecSRohit Agarwal #define MASTER_SNOC_SF_MEM_NOC 5 29*956329ecSRohit Agarwal #define MASTER_GIC 6 30*956329ecSRohit Agarwal #define MASTER_IPA_PCIE 7 31*956329ecSRohit Agarwal #define SLAVE_GEM_NOC_CNOC 8 32*956329ecSRohit Agarwal #define SLAVE_LLCC 9 33*956329ecSRohit Agarwal #define SLAVE_MEM_NOC_PCIE_SNOC 10 34*956329ecSRohit Agarwal #define SLAVE_SERVICE_GEM_NOC 11 35*956329ecSRohit Agarwal 36*956329ecSRohit Agarwal #define MASTER_PCIE_0 0 37*956329ecSRohit Agarwal #define MASTER_PCIE_1 1 38*956329ecSRohit Agarwal #define MASTER_PCIE_2 2 39*956329ecSRohit Agarwal #define SLAVE_ANOC_PCIE_GEM_NOC 3 40*956329ecSRohit Agarwal 41*956329ecSRohit Agarwal #define MASTER_AUDIO 0 42*956329ecSRohit Agarwal #define MASTER_GIC_AHB 1 43*956329ecSRohit Agarwal #define MASTER_PCIE_RSCC 2 44*956329ecSRohit Agarwal #define MASTER_QDSS_BAM 3 45*956329ecSRohit Agarwal #define MASTER_QPIC 4 46*956329ecSRohit Agarwal #define MASTER_QUP_0 5 47*956329ecSRohit Agarwal #define MASTER_ANOC_SNOC 6 48*956329ecSRohit Agarwal #define MASTER_GEM_NOC_CNOC 7 49*956329ecSRohit Agarwal #define MASTER_GEM_NOC_PCIE_SNOC 8 50*956329ecSRohit Agarwal #define MASTER_SNOC_CFG 9 51*956329ecSRohit Agarwal #define MASTER_PCIE_ANOC_CFG 10 52*956329ecSRohit Agarwal #define MASTER_CRYPTO 11 53*956329ecSRohit Agarwal #define MASTER_IPA 12 54*956329ecSRohit Agarwal #define MASTER_MVMSS 13 55*956329ecSRohit Agarwal #define MASTER_EMAC_0 14 56*956329ecSRohit Agarwal #define MASTER_EMAC_1 15 57*956329ecSRohit Agarwal #define MASTER_QDSS_ETR 16 58*956329ecSRohit Agarwal #define MASTER_QDSS_ETR_1 17 59*956329ecSRohit Agarwal #define MASTER_SDCC_1 18 60*956329ecSRohit Agarwal #define MASTER_SDCC_4 19 61*956329ecSRohit Agarwal #define MASTER_USB3_0 20 62*956329ecSRohit Agarwal #define SLAVE_ETH0_CFG 21 63*956329ecSRohit Agarwal #define SLAVE_ETH1_CFG 22 64*956329ecSRohit Agarwal #define SLAVE_AUDIO 23 65*956329ecSRohit Agarwal #define SLAVE_CLK_CTL 24 66*956329ecSRohit Agarwal #define SLAVE_CRYPTO_0_CFG 25 67*956329ecSRohit Agarwal #define SLAVE_IMEM_CFG 26 68*956329ecSRohit Agarwal #define SLAVE_IPA_CFG 27 69*956329ecSRohit Agarwal #define SLAVE_IPC_ROUTER_CFG 28 70*956329ecSRohit Agarwal #define SLAVE_CNOC_MSS 29 71*956329ecSRohit Agarwal #define SLAVE_ICBDI_MVMSS_CFG 30 72*956329ecSRohit Agarwal #define SLAVE_PCIE_0_CFG 31 73*956329ecSRohit Agarwal #define SLAVE_PCIE_1_CFG 32 74*956329ecSRohit Agarwal #define SLAVE_PCIE_2_CFG 33 75*956329ecSRohit Agarwal #define SLAVE_PCIE_RSC_CFG 34 76*956329ecSRohit Agarwal #define SLAVE_PDM 35 77*956329ecSRohit Agarwal #define SLAVE_PRNG 36 78*956329ecSRohit Agarwal #define SLAVE_QDSS_CFG 37 79*956329ecSRohit Agarwal #define SLAVE_QPIC 38 80*956329ecSRohit Agarwal #define SLAVE_QUP_0 39 81*956329ecSRohit Agarwal #define SLAVE_SDCC_1 40 82*956329ecSRohit Agarwal #define SLAVE_SDCC_4 41 83*956329ecSRohit Agarwal #define SLAVE_SPMI_VGI_COEX 42 84*956329ecSRohit Agarwal #define SLAVE_TCSR 43 85*956329ecSRohit Agarwal #define SLAVE_TLMM 44 86*956329ecSRohit Agarwal #define SLAVE_USB3 45 87*956329ecSRohit Agarwal #define SLAVE_USB3_PHY_CFG 46 88*956329ecSRohit Agarwal #define SLAVE_A1NOC_CFG 47 89*956329ecSRohit Agarwal #define SLAVE_DDRSS_CFG 48 90*956329ecSRohit Agarwal #define SLAVE_SNOC_GEM_NOC_SF 49 91*956329ecSRohit Agarwal #define SLAVE_SNOC_CFG 50 92*956329ecSRohit Agarwal #define SLAVE_PCIE_ANOC_CFG 51 93*956329ecSRohit Agarwal #define SLAVE_IMEM 52 94*956329ecSRohit Agarwal #define SLAVE_SERVICE_PCIE_ANOC 53 95*956329ecSRohit Agarwal #define SLAVE_SERVICE_SNOC 54 96*956329ecSRohit Agarwal #define SLAVE_PCIE_0 55 97*956329ecSRohit Agarwal #define SLAVE_PCIE_1 56 98*956329ecSRohit Agarwal #define SLAVE_PCIE_2 57 99*956329ecSRohit Agarwal #define SLAVE_QDSS_STM 58 100*956329ecSRohit Agarwal #define SLAVE_TCU 59 101*956329ecSRohit Agarwal 102*956329ecSRohit Agarwal #endif 103