1*eef6dcbcSPrathamesh Shete /* SPDX-License-Identifier: GPL-2.0 */ 2*eef6dcbcSPrathamesh Shete /* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ 3*eef6dcbcSPrathamesh Shete 4*eef6dcbcSPrathamesh Shete /* 5*eef6dcbcSPrathamesh Shete * This header provides constants for the nvidia,tegra256-gpio DT binding. 6*eef6dcbcSPrathamesh Shete * 7*eef6dcbcSPrathamesh Shete * The first cell in Tegra's GPIO specifier is the GPIO ID. 8*eef6dcbcSPrathamesh Shete * The macros below provide names for this. 9*eef6dcbcSPrathamesh Shete * 10*eef6dcbcSPrathamesh Shete * The second cell contains standard flag values specified in gpio.h. 11*eef6dcbcSPrathamesh Shete */ 12*eef6dcbcSPrathamesh Shete 13*eef6dcbcSPrathamesh Shete #ifndef _DT_BINDINGS_GPIO_TEGRA256_GPIO_H 14*eef6dcbcSPrathamesh Shete #define _DT_BINDINGS_GPIO_TEGRA256_GPIO_H 15*eef6dcbcSPrathamesh Shete 16*eef6dcbcSPrathamesh Shete #include <dt-bindings/gpio/gpio.h> 17*eef6dcbcSPrathamesh Shete 18*eef6dcbcSPrathamesh Shete /* GPIOs implemented by main GPIO controller */ 19*eef6dcbcSPrathamesh Shete #define TEGRA256_MAIN_GPIO_PORT_A 0 20*eef6dcbcSPrathamesh Shete #define TEGRA256_MAIN_GPIO_PORT_B 1 21*eef6dcbcSPrathamesh Shete #define TEGRA256_MAIN_GPIO_PORT_C 2 22*eef6dcbcSPrathamesh Shete #define TEGRA256_MAIN_GPIO_PORT_D 3 23*eef6dcbcSPrathamesh Shete 24*eef6dcbcSPrathamesh Shete #define TEGRA256_MAIN_GPIO(port, offset) \ 25*eef6dcbcSPrathamesh Shete ((TEGRA256_MAIN_GPIO_PORT_##port * 8) + (offset)) 26*eef6dcbcSPrathamesh Shete 27*eef6dcbcSPrathamesh Shete #endif 28*eef6dcbcSPrathamesh Shete 29