1*94047d97SKrzysztof Kozlowski /* SPDX-License-Identifier: GPL-2.0 */ 206dda9d7STomasz Figa /* 306dda9d7STomasz Figa * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com> 406dda9d7STomasz Figa * 506dda9d7STomasz Figa * Device Tree binding constants for Samsung S3C64xx clock controller. 606dda9d7STomasz Figa */ 706dda9d7STomasz Figa 806dda9d7STomasz Figa #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H 906dda9d7STomasz Figa #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H 1006dda9d7STomasz Figa 1106dda9d7STomasz Figa /* 1206dda9d7STomasz Figa * Let each exported clock get a unique index, which is used on DT-enabled 1306dda9d7STomasz Figa * platforms to lookup the clock from a clock specifier. These indices are 1406dda9d7STomasz Figa * therefore considered an ABI and so must not be changed. This implies 1506dda9d7STomasz Figa * that new clocks should be added either in free spaces between clock groups 1606dda9d7STomasz Figa * or at the end. 1706dda9d7STomasz Figa */ 1806dda9d7STomasz Figa 1906dda9d7STomasz Figa /* Core clocks. */ 2006dda9d7STomasz Figa #define CLK27M 1 2106dda9d7STomasz Figa #define CLK48M 2 2206dda9d7STomasz Figa #define FOUT_APLL 3 2306dda9d7STomasz Figa #define FOUT_MPLL 4 2406dda9d7STomasz Figa #define FOUT_EPLL 5 2506dda9d7STomasz Figa #define ARMCLK 6 2606dda9d7STomasz Figa #define HCLKX2 7 2706dda9d7STomasz Figa #define HCLK 8 2806dda9d7STomasz Figa #define PCLK 9 2906dda9d7STomasz Figa 3006dda9d7STomasz Figa /* HCLK bus clocks. */ 3106dda9d7STomasz Figa #define HCLK_3DSE 16 3206dda9d7STomasz Figa #define HCLK_UHOST 17 3306dda9d7STomasz Figa #define HCLK_SECUR 18 3406dda9d7STomasz Figa #define HCLK_SDMA1 19 3506dda9d7STomasz Figa #define HCLK_SDMA0 20 3606dda9d7STomasz Figa #define HCLK_IROM 21 3706dda9d7STomasz Figa #define HCLK_DDR1 22 3806dda9d7STomasz Figa #define HCLK_MEM1 23 3906dda9d7STomasz Figa #define HCLK_MEM0 24 4006dda9d7STomasz Figa #define HCLK_USB 25 4106dda9d7STomasz Figa #define HCLK_HSMMC2 26 4206dda9d7STomasz Figa #define HCLK_HSMMC1 27 4306dda9d7STomasz Figa #define HCLK_HSMMC0 28 4406dda9d7STomasz Figa #define HCLK_MDP 29 4506dda9d7STomasz Figa #define HCLK_DHOST 30 4606dda9d7STomasz Figa #define HCLK_IHOST 31 4706dda9d7STomasz Figa #define HCLK_DMA1 32 4806dda9d7STomasz Figa #define HCLK_DMA0 33 4906dda9d7STomasz Figa #define HCLK_JPEG 34 5006dda9d7STomasz Figa #define HCLK_CAMIF 35 5106dda9d7STomasz Figa #define HCLK_SCALER 36 5206dda9d7STomasz Figa #define HCLK_2D 37 5306dda9d7STomasz Figa #define HCLK_TV 38 5406dda9d7STomasz Figa #define HCLK_POST0 39 5506dda9d7STomasz Figa #define HCLK_ROT 40 5606dda9d7STomasz Figa #define HCLK_LCD 41 5706dda9d7STomasz Figa #define HCLK_TZIC 42 5806dda9d7STomasz Figa #define HCLK_INTC 43 5906dda9d7STomasz Figa #define HCLK_MFC 44 6006dda9d7STomasz Figa #define HCLK_DDR0 45 6106dda9d7STomasz Figa 6206dda9d7STomasz Figa /* PCLK bus clocks. */ 6306dda9d7STomasz Figa #define PCLK_IIC1 48 6406dda9d7STomasz Figa #define PCLK_IIS2 49 6506dda9d7STomasz Figa #define PCLK_SKEY 50 6606dda9d7STomasz Figa #define PCLK_CHIPID 51 6706dda9d7STomasz Figa #define PCLK_SPI1 52 6806dda9d7STomasz Figa #define PCLK_SPI0 53 6906dda9d7STomasz Figa #define PCLK_HSIRX 54 7006dda9d7STomasz Figa #define PCLK_HSITX 55 7106dda9d7STomasz Figa #define PCLK_GPIO 56 7206dda9d7STomasz Figa #define PCLK_IIC0 57 7306dda9d7STomasz Figa #define PCLK_IIS1 58 7406dda9d7STomasz Figa #define PCLK_IIS0 59 7506dda9d7STomasz Figa #define PCLK_AC97 60 7606dda9d7STomasz Figa #define PCLK_TZPC 61 7706dda9d7STomasz Figa #define PCLK_TSADC 62 7806dda9d7STomasz Figa #define PCLK_KEYPAD 63 7906dda9d7STomasz Figa #define PCLK_IRDA 64 8006dda9d7STomasz Figa #define PCLK_PCM1 65 8106dda9d7STomasz Figa #define PCLK_PCM0 66 8206dda9d7STomasz Figa #define PCLK_PWM 67 8306dda9d7STomasz Figa #define PCLK_RTC 68 8406dda9d7STomasz Figa #define PCLK_WDT 69 8506dda9d7STomasz Figa #define PCLK_UART3 70 8606dda9d7STomasz Figa #define PCLK_UART2 71 8706dda9d7STomasz Figa #define PCLK_UART1 72 8806dda9d7STomasz Figa #define PCLK_UART0 73 8906dda9d7STomasz Figa #define PCLK_MFC 74 9006dda9d7STomasz Figa 9106dda9d7STomasz Figa /* Special clocks. */ 9206dda9d7STomasz Figa #define SCLK_UHOST 80 9306dda9d7STomasz Figa #define SCLK_MMC2_48 81 9406dda9d7STomasz Figa #define SCLK_MMC1_48 82 9506dda9d7STomasz Figa #define SCLK_MMC0_48 83 9606dda9d7STomasz Figa #define SCLK_MMC2 84 9706dda9d7STomasz Figa #define SCLK_MMC1 85 9806dda9d7STomasz Figa #define SCLK_MMC0 86 9906dda9d7STomasz Figa #define SCLK_SPI1_48 87 10006dda9d7STomasz Figa #define SCLK_SPI0_48 88 10106dda9d7STomasz Figa #define SCLK_SPI1 89 10206dda9d7STomasz Figa #define SCLK_SPI0 90 10306dda9d7STomasz Figa #define SCLK_DAC27 91 10406dda9d7STomasz Figa #define SCLK_TV27 92 10506dda9d7STomasz Figa #define SCLK_SCALER27 93 10606dda9d7STomasz Figa #define SCLK_SCALER 94 10706dda9d7STomasz Figa #define SCLK_LCD27 95 10806dda9d7STomasz Figa #define SCLK_LCD 96 10906dda9d7STomasz Figa #define SCLK_FIMC 97 11006dda9d7STomasz Figa #define SCLK_POST0_27 98 11106dda9d7STomasz Figa #define SCLK_AUDIO2 99 11206dda9d7STomasz Figa #define SCLK_POST0 100 11306dda9d7STomasz Figa #define SCLK_AUDIO1 101 11406dda9d7STomasz Figa #define SCLK_AUDIO0 102 11506dda9d7STomasz Figa #define SCLK_SECUR 103 11606dda9d7STomasz Figa #define SCLK_IRDA 104 11706dda9d7STomasz Figa #define SCLK_UART 105 11806dda9d7STomasz Figa #define SCLK_MFC 106 11906dda9d7STomasz Figa #define SCLK_CAM 107 12006dda9d7STomasz Figa #define SCLK_JPEG 108 12106dda9d7STomasz Figa #define SCLK_ONENAND 109 12206dda9d7STomasz Figa 12306dda9d7STomasz Figa /* MEM0 bus clocks - S3C6410-specific. */ 12406dda9d7STomasz Figa #define MEM0_CFCON 112 12506dda9d7STomasz Figa #define MEM0_ONENAND1 113 12606dda9d7STomasz Figa #define MEM0_ONENAND0 114 12706dda9d7STomasz Figa #define MEM0_NFCON 115 12806dda9d7STomasz Figa #define MEM0_SROM 116 12906dda9d7STomasz Figa 13006dda9d7STomasz Figa /* Muxes. */ 13106dda9d7STomasz Figa #define MOUT_APLL 128 13206dda9d7STomasz Figa #define MOUT_MPLL 129 13306dda9d7STomasz Figa #define MOUT_EPLL 130 13406dda9d7STomasz Figa #define MOUT_MFC 131 13506dda9d7STomasz Figa #define MOUT_AUDIO0 132 13606dda9d7STomasz Figa #define MOUT_AUDIO1 133 13706dda9d7STomasz Figa #define MOUT_UART 134 13806dda9d7STomasz Figa #define MOUT_SPI0 135 13906dda9d7STomasz Figa #define MOUT_SPI1 136 14006dda9d7STomasz Figa #define MOUT_MMC0 137 14106dda9d7STomasz Figa #define MOUT_MMC1 138 14206dda9d7STomasz Figa #define MOUT_MMC2 139 14306dda9d7STomasz Figa #define MOUT_UHOST 140 14406dda9d7STomasz Figa #define MOUT_IRDA 141 14506dda9d7STomasz Figa #define MOUT_LCD 142 14606dda9d7STomasz Figa #define MOUT_SCALER 143 14706dda9d7STomasz Figa #define MOUT_DAC27 144 14806dda9d7STomasz Figa #define MOUT_TV27 145 14906dda9d7STomasz Figa #define MOUT_AUDIO2 146 15006dda9d7STomasz Figa 15106dda9d7STomasz Figa /* Dividers. */ 15206dda9d7STomasz Figa #define DOUT_MPLL 160 15306dda9d7STomasz Figa #define DOUT_SECUR 161 15406dda9d7STomasz Figa #define DOUT_CAM 162 15506dda9d7STomasz Figa #define DOUT_JPEG 163 15606dda9d7STomasz Figa #define DOUT_MFC 164 15706dda9d7STomasz Figa #define DOUT_MMC0 165 15806dda9d7STomasz Figa #define DOUT_MMC1 166 15906dda9d7STomasz Figa #define DOUT_MMC2 167 16006dda9d7STomasz Figa #define DOUT_LCD 168 16106dda9d7STomasz Figa #define DOUT_SCALER 169 16206dda9d7STomasz Figa #define DOUT_UHOST 170 16306dda9d7STomasz Figa #define DOUT_SPI0 171 16406dda9d7STomasz Figa #define DOUT_SPI1 172 16506dda9d7STomasz Figa #define DOUT_AUDIO0 173 16606dda9d7STomasz Figa #define DOUT_AUDIO1 174 16706dda9d7STomasz Figa #define DOUT_UART 175 16806dda9d7STomasz Figa #define DOUT_IRDA 176 16906dda9d7STomasz Figa #define DOUT_FIMC 177 17006dda9d7STomasz Figa #define DOUT_AUDIO2 178 17106dda9d7STomasz Figa 17206dda9d7STomasz Figa /* Total number of clocks. */ 17306dda9d7STomasz Figa #define NR_CLKS (DOUT_AUDIO2 + 1) 17406dda9d7STomasz Figa 17506dda9d7STomasz Figa #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H */ 176