1*49502b23SEnric Balletbo i Serra /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*49502b23SEnric Balletbo i Serra 3*49502b23SEnric Balletbo i Serra #ifndef DT_BINDINGS_DDR_H 4*49502b23SEnric Balletbo i Serra #define DT_BINDINGS_DDR_H 5*49502b23SEnric Balletbo i Serra 6*49502b23SEnric Balletbo i Serra /* 7*49502b23SEnric Balletbo i Serra * DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for 8*49502b23SEnric Balletbo i Serra * each corresponding bin. 9*49502b23SEnric Balletbo i Serra */ 10*49502b23SEnric Balletbo i Serra 11*49502b23SEnric Balletbo i Serra /* DDR3-800 (5-5-5) */ 12*49502b23SEnric Balletbo i Serra #define DDR3_800D 0 13*49502b23SEnric Balletbo i Serra /* DDR3-800 (6-6-6) */ 14*49502b23SEnric Balletbo i Serra #define DDR3_800E 1 15*49502b23SEnric Balletbo i Serra /* DDR3-1066 (6-6-6) */ 16*49502b23SEnric Balletbo i Serra #define DDR3_1066E 2 17*49502b23SEnric Balletbo i Serra /* DDR3-1066 (7-7-7) */ 18*49502b23SEnric Balletbo i Serra #define DDR3_1066F 3 19*49502b23SEnric Balletbo i Serra /* DDR3-1066 (8-8-8) */ 20*49502b23SEnric Balletbo i Serra #define DDR3_1066G 4 21*49502b23SEnric Balletbo i Serra /* DDR3-1333 (7-7-7) */ 22*49502b23SEnric Balletbo i Serra #define DDR3_1333F 5 23*49502b23SEnric Balletbo i Serra /* DDR3-1333 (8-8-8) */ 24*49502b23SEnric Balletbo i Serra #define DDR3_1333G 6 25*49502b23SEnric Balletbo i Serra /* DDR3-1333 (9-9-9) */ 26*49502b23SEnric Balletbo i Serra #define DDR3_1333H 7 27*49502b23SEnric Balletbo i Serra /* DDR3-1333 (10-10-10) */ 28*49502b23SEnric Balletbo i Serra #define DDR3_1333J 8 29*49502b23SEnric Balletbo i Serra /* DDR3-1600 (8-8-8) */ 30*49502b23SEnric Balletbo i Serra #define DDR3_1600G 9 31*49502b23SEnric Balletbo i Serra /* DDR3-1600 (9-9-9) */ 32*49502b23SEnric Balletbo i Serra #define DDR3_1600H 10 33*49502b23SEnric Balletbo i Serra /* DDR3-1600 (10-10-10) */ 34*49502b23SEnric Balletbo i Serra #define DDR3_1600J 11 35*49502b23SEnric Balletbo i Serra /* DDR3-1600 (11-11-11) */ 36*49502b23SEnric Balletbo i Serra #define DDR3_1600K 12 37*49502b23SEnric Balletbo i Serra /* DDR3-1600 (10-10-10) */ 38*49502b23SEnric Balletbo i Serra #define DDR3_1866J 13 39*49502b23SEnric Balletbo i Serra /* DDR3-1866 (11-11-11) */ 40*49502b23SEnric Balletbo i Serra #define DDR3_1866K 14 41*49502b23SEnric Balletbo i Serra /* DDR3-1866 (12-12-12) */ 42*49502b23SEnric Balletbo i Serra #define DDR3_1866L 15 43*49502b23SEnric Balletbo i Serra /* DDR3-1866 (13-13-13) */ 44*49502b23SEnric Balletbo i Serra #define DDR3_1866M 16 45*49502b23SEnric Balletbo i Serra /* DDR3-2133 (11-11-11) */ 46*49502b23SEnric Balletbo i Serra #define DDR3_2133K 17 47*49502b23SEnric Balletbo i Serra /* DDR3-2133 (12-12-12) */ 48*49502b23SEnric Balletbo i Serra #define DDR3_2133L 18 49*49502b23SEnric Balletbo i Serra /* DDR3-2133 (13-13-13) */ 50*49502b23SEnric Balletbo i Serra #define DDR3_2133M 19 51*49502b23SEnric Balletbo i Serra /* DDR3-2133 (14-14-14) */ 52*49502b23SEnric Balletbo i Serra #define DDR3_2133N 20 53*49502b23SEnric Balletbo i Serra /* DDR3 ATF default */ 54*49502b23SEnric Balletbo i Serra #define DDR3_DEFAULT 21 55*49502b23SEnric Balletbo i Serra 56*49502b23SEnric Balletbo i Serra #endif 57