1b9e4ba54SHeiko Stübner /* 2b9e4ba54SHeiko Stübner * Copyright (c) 2014 MundoReader S.L. 3b9e4ba54SHeiko Stübner * Author: Heiko Stuebner <heiko@sntech.de> 4b9e4ba54SHeiko Stübner * 5b9e4ba54SHeiko Stübner * This program is free software; you can redistribute it and/or modify 6b9e4ba54SHeiko Stübner * it under the terms of the GNU General Public License as published by 7b9e4ba54SHeiko Stübner * the Free Software Foundation; either version 2 of the License, or 8b9e4ba54SHeiko Stübner * (at your option) any later version. 9b9e4ba54SHeiko Stübner * 10b9e4ba54SHeiko Stübner * This program is distributed in the hope that it will be useful, 11b9e4ba54SHeiko Stübner * but WITHOUT ANY WARRANTY; without even the implied warranty of 12b9e4ba54SHeiko Stübner * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13b9e4ba54SHeiko Stübner * GNU General Public License for more details. 14b9e4ba54SHeiko Stübner */ 15b9e4ba54SHeiko Stübner 16b9e4ba54SHeiko Stübner /* core clocks */ 17b9e4ba54SHeiko Stübner #define PLL_APLL 1 18b9e4ba54SHeiko Stübner #define PLL_DPLL 2 19b9e4ba54SHeiko Stübner #define PLL_CPLL 3 20b9e4ba54SHeiko Stübner #define PLL_GPLL 4 21b9e4ba54SHeiko Stübner #define PLL_NPLL 5 224d742e62SHeiko Stuebner #define ARMCLK 6 23b9e4ba54SHeiko Stübner 24b9e4ba54SHeiko Stübner /* sclk gates (special clocks) */ 25b9e4ba54SHeiko Stübner #define SCLK_GPU 64 26b9e4ba54SHeiko Stübner #define SCLK_SPI0 65 27b9e4ba54SHeiko Stübner #define SCLK_SPI1 66 28b9e4ba54SHeiko Stübner #define SCLK_SPI2 67 29b9e4ba54SHeiko Stübner #define SCLK_SDMMC 68 30b9e4ba54SHeiko Stübner #define SCLK_SDIO0 69 31b9e4ba54SHeiko Stübner #define SCLK_SDIO1 70 32b9e4ba54SHeiko Stübner #define SCLK_EMMC 71 33b9e4ba54SHeiko Stübner #define SCLK_TSADC 72 34b9e4ba54SHeiko Stübner #define SCLK_SARADC 73 35b9e4ba54SHeiko Stübner #define SCLK_PS2C 74 36b9e4ba54SHeiko Stübner #define SCLK_NANDC0 75 37b9e4ba54SHeiko Stübner #define SCLK_NANDC1 76 38b9e4ba54SHeiko Stübner #define SCLK_UART0 77 39b9e4ba54SHeiko Stübner #define SCLK_UART1 78 40b9e4ba54SHeiko Stübner #define SCLK_UART2 79 41b9e4ba54SHeiko Stübner #define SCLK_UART3 80 42b9e4ba54SHeiko Stübner #define SCLK_UART4 81 43b9e4ba54SHeiko Stübner #define SCLK_I2S0 82 44b9e4ba54SHeiko Stübner #define SCLK_SPDIF 83 45b9e4ba54SHeiko Stübner #define SCLK_SPDIF8CH 84 46b9e4ba54SHeiko Stübner #define SCLK_TIMER0 85 47b9e4ba54SHeiko Stübner #define SCLK_TIMER1 86 48b9e4ba54SHeiko Stübner #define SCLK_TIMER2 87 49b9e4ba54SHeiko Stübner #define SCLK_TIMER3 88 50b9e4ba54SHeiko Stübner #define SCLK_TIMER4 89 51b9e4ba54SHeiko Stübner #define SCLK_TIMER5 90 52b9e4ba54SHeiko Stübner #define SCLK_TIMER6 91 53b9e4ba54SHeiko Stübner #define SCLK_HSADC 92 54b9e4ba54SHeiko Stübner #define SCLK_OTGPHY0 93 55b9e4ba54SHeiko Stübner #define SCLK_OTGPHY1 94 56b9e4ba54SHeiko Stübner #define SCLK_OTGPHY2 95 57b9e4ba54SHeiko Stübner #define SCLK_OTG_ADP 96 58b9e4ba54SHeiko Stübner #define SCLK_HSICPHY480M 97 59b9e4ba54SHeiko Stübner #define SCLK_HSICPHY12M 98 60b9e4ba54SHeiko Stübner #define SCLK_MACREF 99 61b9e4ba54SHeiko Stübner #define SCLK_LCDC_PWM0 100 62b9e4ba54SHeiko Stübner #define SCLK_LCDC_PWM1 101 63b9e4ba54SHeiko Stübner #define SCLK_MAC_RX 102 64b9e4ba54SHeiko Stübner #define SCLK_MAC_TX 103 655e9a3d70SKever Yang #define SCLK_EDP_24M 104 665e9a3d70SKever Yang #define SCLK_EDP 105 675e9a3d70SKever Yang #define SCLK_RGA 106 685e9a3d70SKever Yang #define SCLK_ISP 107 695e9a3d70SKever Yang #define SCLK_ISP_JPE 108 705e9a3d70SKever Yang #define SCLK_HDMI_HDCP 109 715e9a3d70SKever Yang #define SCLK_HDMI_CEC 110 725e9a3d70SKever Yang #define SCLK_HEVC_CABAC 111 735e9a3d70SKever Yang #define SCLK_HEVC_CORE 112 746d288b16SSonny Rao #define SCLK_I2S0_OUT 113 75c1c9f2ccSAlexandru M Stan #define SCLK_SDMMC_DRV 114 76c1c9f2ccSAlexandru M Stan #define SCLK_SDIO0_DRV 115 77c1c9f2ccSAlexandru M Stan #define SCLK_SDIO1_DRV 116 78c1c9f2ccSAlexandru M Stan #define SCLK_EMMC_DRV 117 79c1c9f2ccSAlexandru M Stan #define SCLK_SDMMC_SAMPLE 118 80c1c9f2ccSAlexandru M Stan #define SCLK_SDIO0_SAMPLE 119 81c1c9f2ccSAlexandru M Stan #define SCLK_SDIO1_SAMPLE 120 82c1c9f2ccSAlexandru M Stan #define SCLK_EMMC_SAMPLE 121 8319ce828cSKever Yang #define SCLK_USBPHY480M_SRC 122 8419da34b4SHuang Lin #define SCLK_PVTM_CORE 123 8519da34b4SHuang Lin #define SCLK_PVTM_GPU 124 86b9e4ba54SHeiko Stübner 87b9e4ba54SHeiko Stübner #define DCLK_VOP0 190 88b9e4ba54SHeiko Stübner #define DCLK_VOP1 191 89b9e4ba54SHeiko Stübner 90b9e4ba54SHeiko Stübner /* aclk gates */ 91b9e4ba54SHeiko Stübner #define ACLK_GPU 192 92b9e4ba54SHeiko Stübner #define ACLK_DMAC1 193 93b9e4ba54SHeiko Stübner #define ACLK_DMAC2 194 94b9e4ba54SHeiko Stübner #define ACLK_MMU 195 95b9e4ba54SHeiko Stübner #define ACLK_GMAC 196 96b9e4ba54SHeiko Stübner #define ACLK_VOP0 197 97b9e4ba54SHeiko Stübner #define ACLK_VOP1 198 98b9e4ba54SHeiko Stübner #define ACLK_CRYPTO 199 99b9e4ba54SHeiko Stübner #define ACLK_RGA 200 1005e9a3d70SKever Yang #define ACLK_RGA_NIU 201 1015e9a3d70SKever Yang #define ACLK_IEP 202 1025e9a3d70SKever Yang #define ACLK_VIO0_NIU 203 1035e9a3d70SKever Yang #define ACLK_VIP 204 1045e9a3d70SKever Yang #define ACLK_ISP 205 1055e9a3d70SKever Yang #define ACLK_VIO1_NIU 206 1065e9a3d70SKever Yang #define ACLK_HEVC 207 1075e9a3d70SKever Yang #define ACLK_VCODEC 208 1085e9a3d70SKever Yang #define ACLK_CPU 209 1095e9a3d70SKever Yang #define ACLK_PERI 210 110b9e4ba54SHeiko Stübner 111b9e4ba54SHeiko Stübner /* pclk gates */ 112b9e4ba54SHeiko Stübner #define PCLK_GPIO0 320 113b9e4ba54SHeiko Stübner #define PCLK_GPIO1 321 114b9e4ba54SHeiko Stübner #define PCLK_GPIO2 322 115b9e4ba54SHeiko Stübner #define PCLK_GPIO3 323 116b9e4ba54SHeiko Stübner #define PCLK_GPIO4 324 117b9e4ba54SHeiko Stübner #define PCLK_GPIO5 325 118b9e4ba54SHeiko Stübner #define PCLK_GPIO6 326 119b9e4ba54SHeiko Stübner #define PCLK_GPIO7 327 120b9e4ba54SHeiko Stübner #define PCLK_GPIO8 328 121b9e4ba54SHeiko Stübner #define PCLK_GRF 329 122b9e4ba54SHeiko Stübner #define PCLK_SGRF 330 123b9e4ba54SHeiko Stübner #define PCLK_PMU 331 124b9e4ba54SHeiko Stübner #define PCLK_I2C0 332 125b9e4ba54SHeiko Stübner #define PCLK_I2C1 333 126b9e4ba54SHeiko Stübner #define PCLK_I2C2 334 127b9e4ba54SHeiko Stübner #define PCLK_I2C3 335 128b9e4ba54SHeiko Stübner #define PCLK_I2C4 336 129b9e4ba54SHeiko Stübner #define PCLK_I2C5 337 130b9e4ba54SHeiko Stübner #define PCLK_SPI0 338 131b9e4ba54SHeiko Stübner #define PCLK_SPI1 339 132b9e4ba54SHeiko Stübner #define PCLK_SPI2 340 133b9e4ba54SHeiko Stübner #define PCLK_UART0 341 134b9e4ba54SHeiko Stübner #define PCLK_UART1 342 135b9e4ba54SHeiko Stübner #define PCLK_UART2 343 136b9e4ba54SHeiko Stübner #define PCLK_UART3 344 137b9e4ba54SHeiko Stübner #define PCLK_UART4 345 138b9e4ba54SHeiko Stübner #define PCLK_TSADC 346 139b9e4ba54SHeiko Stübner #define PCLK_SARADC 347 140b9e4ba54SHeiko Stübner #define PCLK_SIM 348 141b9e4ba54SHeiko Stübner #define PCLK_GMAC 349 142b9e4ba54SHeiko Stübner #define PCLK_PWM 350 143b9e4ba54SHeiko Stübner #define PCLK_RKPWM 351 144b9e4ba54SHeiko Stübner #define PCLK_PS2C 352 145b9e4ba54SHeiko Stübner #define PCLK_TIMER 353 146b9e4ba54SHeiko Stübner #define PCLK_TZPC 354 1475e9a3d70SKever Yang #define PCLK_EDP_CTRL 355 1485e9a3d70SKever Yang #define PCLK_MIPI_DSI0 356 1495e9a3d70SKever Yang #define PCLK_MIPI_DSI1 357 1505e9a3d70SKever Yang #define PCLK_MIPI_CSI 358 1515e9a3d70SKever Yang #define PCLK_LVDS_PHY 359 1525e9a3d70SKever Yang #define PCLK_HDMI_CTRL 360 1535e9a3d70SKever Yang #define PCLK_VIO2_H2P 361 1545e9a3d70SKever Yang #define PCLK_CPU 362 1555e9a3d70SKever Yang #define PCLK_PERI 363 1561ae2b016SJeff Chen #define PCLK_DDRUPCTL0 364 1571ae2b016SJeff Chen #define PCLK_PUBL0 365 1581ae2b016SJeff Chen #define PCLK_DDRUPCTL1 366 1591ae2b016SJeff Chen #define PCLK_PUBL1 367 160*b82465c9SHeiko Stuebner #define PCLK_WDT 368 161b9e4ba54SHeiko Stübner 162b9e4ba54SHeiko Stübner /* hclk gates */ 163b9e4ba54SHeiko Stübner #define HCLK_GPS 448 164b9e4ba54SHeiko Stübner #define HCLK_OTG0 449 165b9e4ba54SHeiko Stübner #define HCLK_USBHOST0 450 166b9e4ba54SHeiko Stübner #define HCLK_USBHOST1 451 167b9e4ba54SHeiko Stübner #define HCLK_HSIC 452 168b9e4ba54SHeiko Stübner #define HCLK_NANDC0 453 169b9e4ba54SHeiko Stübner #define HCLK_NANDC1 454 170b9e4ba54SHeiko Stübner #define HCLK_TSP 455 171b9e4ba54SHeiko Stübner #define HCLK_SDMMC 456 172b9e4ba54SHeiko Stübner #define HCLK_SDIO0 457 173b9e4ba54SHeiko Stübner #define HCLK_SDIO1 458 174b9e4ba54SHeiko Stübner #define HCLK_EMMC 459 175b9e4ba54SHeiko Stübner #define HCLK_HSADC 460 176b9e4ba54SHeiko Stübner #define HCLK_CRYPTO 461 177b9e4ba54SHeiko Stübner #define HCLK_I2S0 462 178b9e4ba54SHeiko Stübner #define HCLK_SPDIF 463 179b9e4ba54SHeiko Stübner #define HCLK_SPDIF8CH 464 180b9e4ba54SHeiko Stübner #define HCLK_VOP0 465 181b9e4ba54SHeiko Stübner #define HCLK_VOP1 466 182b9e4ba54SHeiko Stübner #define HCLK_ROM 467 183b9e4ba54SHeiko Stübner #define HCLK_IEP 468 184b9e4ba54SHeiko Stübner #define HCLK_ISP 469 185b9e4ba54SHeiko Stübner #define HCLK_RGA 470 1865e9a3d70SKever Yang #define HCLK_VIO_AHB_ARBI 471 1875e9a3d70SKever Yang #define HCLK_VIO_NIU 472 1885e9a3d70SKever Yang #define HCLK_VIP 473 1895e9a3d70SKever Yang #define HCLK_VIO2_H2P 474 1905e9a3d70SKever Yang #define HCLK_HEVC 475 1915e9a3d70SKever Yang #define HCLK_VCODEC 476 1925e9a3d70SKever Yang #define HCLK_CPU 477 1935e9a3d70SKever Yang #define HCLK_PERI 478 194b9e4ba54SHeiko Stübner 1955e9a3d70SKever Yang #define CLK_NR_CLKS (HCLK_PERI + 1) 196b9e4ba54SHeiko Stübner 197b9e4ba54SHeiko Stübner /* soft-reset indices */ 198b9e4ba54SHeiko Stübner #define SRST_CORE0 0 199b9e4ba54SHeiko Stübner #define SRST_CORE1 1 200b9e4ba54SHeiko Stübner #define SRST_CORE2 2 201b9e4ba54SHeiko Stübner #define SRST_CORE3 3 202b9e4ba54SHeiko Stübner #define SRST_CORE0_PO 4 203b9e4ba54SHeiko Stübner #define SRST_CORE1_PO 5 204b9e4ba54SHeiko Stübner #define SRST_CORE2_PO 6 205b9e4ba54SHeiko Stübner #define SRST_CORE3_PO 7 206b9e4ba54SHeiko Stübner #define SRST_PDCORE_STRSYS 8 207b9e4ba54SHeiko Stübner #define SRST_PDBUS_STRSYS 9 208b9e4ba54SHeiko Stübner #define SRST_L2C 10 209b9e4ba54SHeiko Stübner #define SRST_TOPDBG 11 210b9e4ba54SHeiko Stübner #define SRST_CORE0_DBG 12 211b9e4ba54SHeiko Stübner #define SRST_CORE1_DBG 13 212b9e4ba54SHeiko Stübner #define SRST_CORE2_DBG 14 213b9e4ba54SHeiko Stübner #define SRST_CORE3_DBG 15 214b9e4ba54SHeiko Stübner 215b9e4ba54SHeiko Stübner #define SRST_PDBUG_AHB_ARBITOR 16 216b9e4ba54SHeiko Stübner #define SRST_EFUSE256 17 217b9e4ba54SHeiko Stübner #define SRST_DMAC1 18 218b9e4ba54SHeiko Stübner #define SRST_INTMEM 19 219b9e4ba54SHeiko Stübner #define SRST_ROM 20 220b9e4ba54SHeiko Stübner #define SRST_SPDIF8CH 21 221b9e4ba54SHeiko Stübner #define SRST_TIMER 22 222b9e4ba54SHeiko Stübner #define SRST_I2S0 23 223b9e4ba54SHeiko Stübner #define SRST_SPDIF 24 224b9e4ba54SHeiko Stübner #define SRST_TIMER0 25 225b9e4ba54SHeiko Stübner #define SRST_TIMER1 26 226b9e4ba54SHeiko Stübner #define SRST_TIMER2 27 227b9e4ba54SHeiko Stübner #define SRST_TIMER3 28 228b9e4ba54SHeiko Stübner #define SRST_TIMER4 29 229b9e4ba54SHeiko Stübner #define SRST_TIMER5 30 230b9e4ba54SHeiko Stübner #define SRST_EFUSE 31 231b9e4ba54SHeiko Stübner 232b9e4ba54SHeiko Stübner #define SRST_GPIO0 32 233b9e4ba54SHeiko Stübner #define SRST_GPIO1 33 234b9e4ba54SHeiko Stübner #define SRST_GPIO2 34 235b9e4ba54SHeiko Stübner #define SRST_GPIO3 35 236b9e4ba54SHeiko Stübner #define SRST_GPIO4 36 237b9e4ba54SHeiko Stübner #define SRST_GPIO5 37 238b9e4ba54SHeiko Stübner #define SRST_GPIO6 38 239b9e4ba54SHeiko Stübner #define SRST_GPIO7 39 240b9e4ba54SHeiko Stübner #define SRST_GPIO8 40 241b9e4ba54SHeiko Stübner #define SRST_I2C0 42 242b9e4ba54SHeiko Stübner #define SRST_I2C1 43 243b9e4ba54SHeiko Stübner #define SRST_I2C2 44 244b9e4ba54SHeiko Stübner #define SRST_I2C3 45 245b9e4ba54SHeiko Stübner #define SRST_I2C4 46 246b9e4ba54SHeiko Stübner #define SRST_I2C5 47 247b9e4ba54SHeiko Stübner 248b9e4ba54SHeiko Stübner #define SRST_DWPWM 48 249b9e4ba54SHeiko Stübner #define SRST_MMC_PERI 49 250b9e4ba54SHeiko Stübner #define SRST_PERIPH_MMU 50 251b9e4ba54SHeiko Stübner #define SRST_DAP 51 252b9e4ba54SHeiko Stübner #define SRST_DAP_SYS 52 253b9e4ba54SHeiko Stübner #define SRST_TPIU 53 254b9e4ba54SHeiko Stübner #define SRST_PMU_APB 54 255b9e4ba54SHeiko Stübner #define SRST_GRF 55 256b9e4ba54SHeiko Stübner #define SRST_PMU 56 257b9e4ba54SHeiko Stübner #define SRST_PERIPH_AXI 57 258b9e4ba54SHeiko Stübner #define SRST_PERIPH_AHB 58 259b9e4ba54SHeiko Stübner #define SRST_PERIPH_APB 59 260b9e4ba54SHeiko Stübner #define SRST_PERIPH_NIU 60 261b9e4ba54SHeiko Stübner #define SRST_PDPERI_AHB_ARBI 61 262b9e4ba54SHeiko Stübner #define SRST_EMEM 62 263b9e4ba54SHeiko Stübner #define SRST_USB_PERI 63 264b9e4ba54SHeiko Stübner 265b9e4ba54SHeiko Stübner #define SRST_DMAC2 64 266b9e4ba54SHeiko Stübner #define SRST_MAC 66 267b9e4ba54SHeiko Stübner #define SRST_GPS 67 268b9e4ba54SHeiko Stübner #define SRST_RKPWM 69 269b9e4ba54SHeiko Stübner #define SRST_CCP 71 270b9e4ba54SHeiko Stübner #define SRST_USBHOST0 72 271b9e4ba54SHeiko Stübner #define SRST_HSIC 73 272b9e4ba54SHeiko Stübner #define SRST_HSIC_AUX 74 273b9e4ba54SHeiko Stübner #define SRST_HSIC_PHY 75 274b9e4ba54SHeiko Stübner #define SRST_HSADC 76 275b9e4ba54SHeiko Stübner #define SRST_NANDC0 77 276b9e4ba54SHeiko Stübner #define SRST_NANDC1 78 277b9e4ba54SHeiko Stübner 278b9e4ba54SHeiko Stübner #define SRST_TZPC 80 279b9e4ba54SHeiko Stübner #define SRST_SPI0 83 280b9e4ba54SHeiko Stübner #define SRST_SPI1 84 281b9e4ba54SHeiko Stübner #define SRST_SPI2 85 282b9e4ba54SHeiko Stübner #define SRST_SARADC 87 283b9e4ba54SHeiko Stübner #define SRST_PDALIVE_NIU 88 284b9e4ba54SHeiko Stübner #define SRST_PDPMU_INTMEM 89 285b9e4ba54SHeiko Stübner #define SRST_PDPMU_NIU 90 286b9e4ba54SHeiko Stübner #define SRST_SGRF 91 287b9e4ba54SHeiko Stübner 288b9e4ba54SHeiko Stübner #define SRST_VIO_ARBI 96 289b9e4ba54SHeiko Stübner #define SRST_RGA_NIU 97 290b9e4ba54SHeiko Stübner #define SRST_VIO0_NIU_AXI 98 291b9e4ba54SHeiko Stübner #define SRST_VIO_NIU_AHB 99 292b9e4ba54SHeiko Stübner #define SRST_LCDC0_AXI 100 293b9e4ba54SHeiko Stübner #define SRST_LCDC0_AHB 101 294b9e4ba54SHeiko Stübner #define SRST_LCDC0_DCLK 102 295b9e4ba54SHeiko Stübner #define SRST_VIO1_NIU_AXI 103 296b9e4ba54SHeiko Stübner #define SRST_VIP 104 297b9e4ba54SHeiko Stübner #define SRST_RGA_CORE 105 298b9e4ba54SHeiko Stübner #define SRST_IEP_AXI 106 299b9e4ba54SHeiko Stübner #define SRST_IEP_AHB 107 300b9e4ba54SHeiko Stübner #define SRST_RGA_AXI 108 301b9e4ba54SHeiko Stübner #define SRST_RGA_AHB 109 302b9e4ba54SHeiko Stübner #define SRST_ISP 110 303b9e4ba54SHeiko Stübner #define SRST_EDP 111 304b9e4ba54SHeiko Stübner 305b9e4ba54SHeiko Stübner #define SRST_VCODEC_AXI 112 306b9e4ba54SHeiko Stübner #define SRST_VCODEC_AHB 113 307b9e4ba54SHeiko Stübner #define SRST_VIO_H2P 114 308b9e4ba54SHeiko Stübner #define SRST_MIPIDSI0 115 309b9e4ba54SHeiko Stübner #define SRST_MIPIDSI1 116 310b9e4ba54SHeiko Stübner #define SRST_MIPICSI 117 311b9e4ba54SHeiko Stübner #define SRST_LVDS_PHY 118 312b9e4ba54SHeiko Stübner #define SRST_LVDS_CON 119 313b9e4ba54SHeiko Stübner #define SRST_GPU 120 314b9e4ba54SHeiko Stübner #define SRST_HDMI 121 315b9e4ba54SHeiko Stübner #define SRST_CORE_PVTM 124 316b9e4ba54SHeiko Stübner #define SRST_GPU_PVTM 125 317b9e4ba54SHeiko Stübner 318b9e4ba54SHeiko Stübner #define SRST_MMC0 128 319b9e4ba54SHeiko Stübner #define SRST_SDIO0 129 320b9e4ba54SHeiko Stübner #define SRST_SDIO1 130 321b9e4ba54SHeiko Stübner #define SRST_EMMC 131 322b9e4ba54SHeiko Stübner #define SRST_USBOTG_AHB 132 323b9e4ba54SHeiko Stübner #define SRST_USBOTG_PHY 133 324b9e4ba54SHeiko Stübner #define SRST_USBOTG_CON 134 325b9e4ba54SHeiko Stübner #define SRST_USBHOST0_AHB 135 326b9e4ba54SHeiko Stübner #define SRST_USBHOST0_PHY 136 327b9e4ba54SHeiko Stübner #define SRST_USBHOST0_CON 137 328b9e4ba54SHeiko Stübner #define SRST_USBHOST1_AHB 138 329b9e4ba54SHeiko Stübner #define SRST_USBHOST1_PHY 139 330b9e4ba54SHeiko Stübner #define SRST_USBHOST1_CON 140 331b9e4ba54SHeiko Stübner #define SRST_USB_ADP 141 332b9e4ba54SHeiko Stübner #define SRST_ACC_EFUSE 142 3334b47c3f5SMark yao 3344b47c3f5SMark yao #define SRST_CORESIGHT 144 3354b47c3f5SMark yao #define SRST_PD_CORE_AHB_NOC 145 3364b47c3f5SMark yao #define SRST_PD_CORE_APB_NOC 146 3374b47c3f5SMark yao #define SRST_PD_CORE_MP_AXI 147 3384b47c3f5SMark yao #define SRST_GIC 148 3394b47c3f5SMark yao #define SRST_LCDC_PWM0 149 3404b47c3f5SMark yao #define SRST_LCDC_PWM1 150 3414b47c3f5SMark yao #define SRST_VIO0_H2P_BRG 151 3424b47c3f5SMark yao #define SRST_VIO1_H2P_BRG 152 3434b47c3f5SMark yao #define SRST_RGA_H2P_BRG 153 3444b47c3f5SMark yao #define SRST_HEVC 154 3454b47c3f5SMark yao #define SRST_TSADC 159 3464b47c3f5SMark yao 3474b47c3f5SMark yao #define SRST_DDRPHY0 160 3484b47c3f5SMark yao #define SRST_DDRPHY0_APB 161 3494b47c3f5SMark yao #define SRST_DDRCTRL0 162 3504b47c3f5SMark yao #define SRST_DDRCTRL0_APB 163 3514b47c3f5SMark yao #define SRST_DDRPHY0_CTRL 164 3524b47c3f5SMark yao #define SRST_DDRPHY1 165 3534b47c3f5SMark yao #define SRST_DDRPHY1_APB 166 3544b47c3f5SMark yao #define SRST_DDRCTRL1 167 3554b47c3f5SMark yao #define SRST_DDRCTRL1_APB 168 3564b47c3f5SMark yao #define SRST_DDRPHY1_CTRL 169 3574b47c3f5SMark yao #define SRST_DDRMSCH0 170 3584b47c3f5SMark yao #define SRST_DDRMSCH1 171 3594b47c3f5SMark yao #define SRST_CRYPTO 174 3604b47c3f5SMark yao #define SRST_C2C_HOST 175 3614b47c3f5SMark yao 3624b47c3f5SMark yao #define SRST_LCDC1_AXI 176 3634b47c3f5SMark yao #define SRST_LCDC1_AHB 177 3644b47c3f5SMark yao #define SRST_LCDC1_DCLK 178 3654b47c3f5SMark yao #define SRST_UART0 179 3664b47c3f5SMark yao #define SRST_UART1 180 3674b47c3f5SMark yao #define SRST_UART2 181 3684b47c3f5SMark yao #define SRST_UART3 182 3694b47c3f5SMark yao #define SRST_UART4 183 3704b47c3f5SMark yao #define SRST_SIMC 186 3714b47c3f5SMark yao #define SRST_PS2C 187 3724b47c3f5SMark yao #define SRST_TSP 188 3734b47c3f5SMark yao #define SRST_TSP_CLKIN0 189 3744b47c3f5SMark yao #define SRST_TSP_CLKIN1 190 3754b47c3f5SMark yao #define SRST_TSP_27M 191 376