1*afec1abaSLad Prabhakar /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*afec1abaSLad Prabhakar * 3*afec1abaSLad Prabhakar * Copyright (C) 2024 Renesas Electronics Corp. 4*afec1abaSLad Prabhakar */ 5*afec1abaSLad Prabhakar #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ 6*afec1abaSLad Prabhakar #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ 7*afec1abaSLad Prabhakar 8*afec1abaSLad Prabhakar #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*afec1abaSLad Prabhakar 10*afec1abaSLad Prabhakar /* Core Clock list */ 11*afec1abaSLad Prabhakar #define R9A09G057_SYS_0_PCLK 0 12*afec1abaSLad Prabhakar #define R9A09G057_CA55_0_CORE_CLK0 1 13*afec1abaSLad Prabhakar #define R9A09G057_CA55_0_CORE_CLK1 2 14*afec1abaSLad Prabhakar #define R9A09G057_CA55_0_CORE_CLK2 3 15*afec1abaSLad Prabhakar #define R9A09G057_CA55_0_CORE_CLK3 4 16*afec1abaSLad Prabhakar #define R9A09G057_CA55_0_PERIPHCLK 5 17*afec1abaSLad Prabhakar #define R9A09G057_CM33_CLK0 6 18*afec1abaSLad Prabhakar #define R9A09G057_CST_0_SWCLKTCK 7 19*afec1abaSLad Prabhakar #define R9A09G057_IOTOP_0_SHCLK 8 20*afec1abaSLad Prabhakar 21*afec1abaSLad Prabhakar #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */ 22