1*25458fddSBiju Das /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*25458fddSBiju Das * 3*25458fddSBiju Das * Copyright (C) 2024 Renesas Electronics Corp. 4*25458fddSBiju Das */ 5*25458fddSBiju Das #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ 6*25458fddSBiju Das #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ 7*25458fddSBiju Das 8*25458fddSBiju Das #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*25458fddSBiju Das 10*25458fddSBiju Das /* Core Clock list */ 11*25458fddSBiju Das #define R9A09G047_SYS_0_PCLK 0 12*25458fddSBiju Das #define R9A09G047_CA55_0_CORECLK0 1 13*25458fddSBiju Das #define R9A09G047_CA55_0_CORECLK1 2 14*25458fddSBiju Das #define R9A09G047_CA55_0_CORECLK2 3 15*25458fddSBiju Das #define R9A09G047_CA55_0_CORECLK3 4 16*25458fddSBiju Das #define R9A09G047_CA55_0_PERIPHCLK 5 17*25458fddSBiju Das #define R9A09G047_CM33_CLK0 6 18*25458fddSBiju Das #define R9A09G047_CST_0_SWCLKTCK 7 19*25458fddSBiju Das #define R9A09G047_IOTOP_0_SHCLK 8 20*25458fddSBiju Das 21*25458fddSBiju Das #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ 22