1*440b075bSKrzysztof Kozlowski /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 281c16558SYoshihiro Shimoda /* 381c16558SYoshihiro Shimoda * Copyright (C) 2021 Renesas Electronics Corp. 481c16558SYoshihiro Shimoda */ 581c16558SYoshihiro Shimoda #ifndef __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ 681c16558SYoshihiro Shimoda #define __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ 781c16558SYoshihiro Shimoda 881c16558SYoshihiro Shimoda #include <dt-bindings/clock/renesas-cpg-mssr.h> 981c16558SYoshihiro Shimoda 1081c16558SYoshihiro Shimoda /* r8a779f0 CPG Core Clocks */ 1181c16558SYoshihiro Shimoda 1281c16558SYoshihiro Shimoda #define R8A779F0_CLK_ZX 0 1381c16558SYoshihiro Shimoda #define R8A779F0_CLK_ZS 1 1481c16558SYoshihiro Shimoda #define R8A779F0_CLK_ZT 2 1581c16558SYoshihiro Shimoda #define R8A779F0_CLK_ZTR 3 1681c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D2 4 1781c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D3 5 1881c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D4 6 1981c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D2_MM 7 2081c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D3_MM 8 2181c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D4_MM 9 2281c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D2_RT 10 2381c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D3_RT 11 2481c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D4_RT 12 2581c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D6_RT 13 2681c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D3_PER 14 2781c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D6_PER 15 2881c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D12_PER 16 2981c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D24_PER 17 3081c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D2_HSC 18 3181c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D3_HSC 19 3281c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D4_HSC 20 3381c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D6_HSC 21 3481c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D12_HSC 22 3581c16558SYoshihiro Shimoda #define R8A779F0_CLK_S0D2_CC 23 3681c16558SYoshihiro Shimoda #define R8A779F0_CLK_CL 24 3781c16558SYoshihiro Shimoda #define R8A779F0_CLK_CL16M 25 3881c16558SYoshihiro Shimoda #define R8A779F0_CLK_CL16M_MM 26 3981c16558SYoshihiro Shimoda #define R8A779F0_CLK_CL16M_RT 27 4081c16558SYoshihiro Shimoda #define R8A779F0_CLK_CL16M_PER 28 4181c16558SYoshihiro Shimoda #define R8A779F0_CLK_CL16M_HSC 29 4281c16558SYoshihiro Shimoda #define R8A779F0_CLK_Z0 30 4381c16558SYoshihiro Shimoda #define R8A779F0_CLK_Z1 31 4481c16558SYoshihiro Shimoda #define R8A779F0_CLK_ZB3 32 4581c16558SYoshihiro Shimoda #define R8A779F0_CLK_ZB3D2 33 4681c16558SYoshihiro Shimoda #define R8A779F0_CLK_ZB3D4 34 4781c16558SYoshihiro Shimoda #define R8A779F0_CLK_SD0H 35 4881c16558SYoshihiro Shimoda #define R8A779F0_CLK_SD0 36 4981c16558SYoshihiro Shimoda #define R8A779F0_CLK_RPC 37 5081c16558SYoshihiro Shimoda #define R8A779F0_CLK_RPCD2 38 5181c16558SYoshihiro Shimoda #define R8A779F0_CLK_MSO 39 5281c16558SYoshihiro Shimoda #define R8A779F0_CLK_SASYNCRT 40 5381c16558SYoshihiro Shimoda #define R8A779F0_CLK_SASYNCPERD1 41 5481c16558SYoshihiro Shimoda #define R8A779F0_CLK_SASYNCPERD2 42 5581c16558SYoshihiro Shimoda #define R8A779F0_CLK_SASYNCPERD4 43 5681c16558SYoshihiro Shimoda #define R8A779F0_CLK_DBGSOC_HSC 44 5781c16558SYoshihiro Shimoda #define R8A779F0_CLK_RSW2 45 5881c16558SYoshihiro Shimoda #define R8A779F0_CLK_OSC 46 5981c16558SYoshihiro Shimoda #define R8A779F0_CLK_ZR 47 6081c16558SYoshihiro Shimoda #define R8A779F0_CLK_CPEX 48 6181c16558SYoshihiro Shimoda #define R8A779F0_CLK_CBFUSA 49 6281c16558SYoshihiro Shimoda #define R8A779F0_CLK_R 50 6381c16558SYoshihiro Shimoda 6481c16558SYoshihiro Shimoda #endif /* __DT_BINDINGS_CLOCK_R8A779F0_CPG_MSSR_H__ */ 65