1*fa2d185fSYoshihiro Shimoda /* SPDX-License-Identifier: GPL-2.0-only */ 2*fa2d185fSYoshihiro Shimoda /* 3*fa2d185fSYoshihiro Shimoda * Copyright (C) 2020 Renesas Electronics Corp. 4*fa2d185fSYoshihiro Shimoda */ 5*fa2d185fSYoshihiro Shimoda #ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ 6*fa2d185fSYoshihiro Shimoda #define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ 7*fa2d185fSYoshihiro Shimoda 8*fa2d185fSYoshihiro Shimoda #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*fa2d185fSYoshihiro Shimoda 10*fa2d185fSYoshihiro Shimoda /* r8a779A0 CPG Core Clocks */ 11*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_Z0 0 12*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_ZX 1 13*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_Z1 2 14*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_ZR 3 15*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_ZS 4 16*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_ZT 5 17*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_ZTR 6 18*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_S1D1 7 19*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_S1D2 8 20*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_S1D4 9 21*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_S1D8 10 22*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_S1D12 11 23*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_S3D1 12 24*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_S3D2 13 25*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_S3D4 14 26*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_LB 15 27*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_CP 16 28*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_CL 17 29*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_CL16MCK 18 30*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_ZB30 19 31*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_ZB30D2 20 32*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_ZB30D4 21 33*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_ZB31 22 34*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_ZB31D2 23 35*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_ZB31D4 24 36*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_SD0H 25 37*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_SD0 26 38*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_RPC 27 39*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_RPCD2 28 40*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_MSO 29 41*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_CANFD 30 42*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_CSI0 31 43*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_FRAY 32 44*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_DSI 33 45*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_VIP 34 46*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_ADGH 35 47*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_CNNDSP 36 48*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_ICU 37 49*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_ICUD2 38 50*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_VCBUS 39 51*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_CBFUSA 40 52*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_R 41 53*fa2d185fSYoshihiro Shimoda #define R8A779A0_CLK_OSC 42 54*fa2d185fSYoshihiro Shimoda 55*fa2d185fSYoshihiro Shimoda #endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */ 56