1*35b3c462SSergei Shtylyov /* SPDX-License-Identifier: GPL-2.0+ */ 2*35b3c462SSergei Shtylyov /* 3*35b3c462SSergei Shtylyov * Copyright (C) 2018 Renesas Electronics Corp. 4*35b3c462SSergei Shtylyov * Copyright (C) 2018 Cogent Embedded, Inc. 5*35b3c462SSergei Shtylyov */ 6*35b3c462SSergei Shtylyov #ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ 7*35b3c462SSergei Shtylyov #define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ 8*35b3c462SSergei Shtylyov 9*35b3c462SSergei Shtylyov #include <dt-bindings/clock/renesas-cpg-mssr.h> 10*35b3c462SSergei Shtylyov 11*35b3c462SSergei Shtylyov /* r8a77980 CPG Core Clocks */ 12*35b3c462SSergei Shtylyov #define R8A77980_CLK_Z2 0 13*35b3c462SSergei Shtylyov #define R8A77980_CLK_ZR 1 14*35b3c462SSergei Shtylyov #define R8A77980_CLK_ZTR 2 15*35b3c462SSergei Shtylyov #define R8A77980_CLK_ZTRD2 3 16*35b3c462SSergei Shtylyov #define R8A77980_CLK_ZT 4 17*35b3c462SSergei Shtylyov #define R8A77980_CLK_ZX 5 18*35b3c462SSergei Shtylyov #define R8A77980_CLK_S0D1 6 19*35b3c462SSergei Shtylyov #define R8A77980_CLK_S0D2 7 20*35b3c462SSergei Shtylyov #define R8A77980_CLK_S0D3 8 21*35b3c462SSergei Shtylyov #define R8A77980_CLK_S0D4 9 22*35b3c462SSergei Shtylyov #define R8A77980_CLK_S0D6 10 23*35b3c462SSergei Shtylyov #define R8A77980_CLK_S0D12 11 24*35b3c462SSergei Shtylyov #define R8A77980_CLK_S0D24 12 25*35b3c462SSergei Shtylyov #define R8A77980_CLK_S1D1 13 26*35b3c462SSergei Shtylyov #define R8A77980_CLK_S1D2 14 27*35b3c462SSergei Shtylyov #define R8A77980_CLK_S1D4 15 28*35b3c462SSergei Shtylyov #define R8A77980_CLK_S2D1 16 29*35b3c462SSergei Shtylyov #define R8A77980_CLK_S2D2 17 30*35b3c462SSergei Shtylyov #define R8A77980_CLK_S2D4 18 31*35b3c462SSergei Shtylyov #define R8A77980_CLK_S3D1 19 32*35b3c462SSergei Shtylyov #define R8A77980_CLK_S3D2 20 33*35b3c462SSergei Shtylyov #define R8A77980_CLK_S3D4 21 34*35b3c462SSergei Shtylyov #define R8A77980_CLK_LB 22 35*35b3c462SSergei Shtylyov #define R8A77980_CLK_CL 23 36*35b3c462SSergei Shtylyov #define R8A77980_CLK_ZB3 24 37*35b3c462SSergei Shtylyov #define R8A77980_CLK_ZB3D2 25 38*35b3c462SSergei Shtylyov #define R8A77980_CLK_ZB3D4 26 39*35b3c462SSergei Shtylyov #define R8A77980_CLK_SD0H 27 40*35b3c462SSergei Shtylyov #define R8A77980_CLK_SD0 28 41*35b3c462SSergei Shtylyov #define R8A77980_CLK_RPC 29 42*35b3c462SSergei Shtylyov #define R8A77980_CLK_RPCD2 30 43*35b3c462SSergei Shtylyov #define R8A77980_CLK_MSO 31 44*35b3c462SSergei Shtylyov #define R8A77980_CLK_CANFD 32 45*35b3c462SSergei Shtylyov #define R8A77980_CLK_CSI0 33 46*35b3c462SSergei Shtylyov #define R8A77980_CLK_CP 34 47*35b3c462SSergei Shtylyov #define R8A77980_CLK_CPEX 35 48*35b3c462SSergei Shtylyov #define R8A77980_CLK_R 36 49*35b3c462SSergei Shtylyov #define R8A77980_CLK_OSC 37 50*35b3c462SSergei Shtylyov 51*35b3c462SSergei Shtylyov #endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */ 52