1*5d169ce7SKuninori Morimoto /* SPDX-License-Identifier: GPL-2.0+ 2*5d169ce7SKuninori Morimoto * 3ecadea00SSergei Shtylyov * Copyright (C) 2016 Renesas Electronics Corp. 4ecadea00SSergei Shtylyov * Copyright (C) 2017 Cogent Embedded, Inc. 5ecadea00SSergei Shtylyov */ 6ecadea00SSergei Shtylyov #ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ 7ecadea00SSergei Shtylyov #define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ 8ecadea00SSergei Shtylyov 9ecadea00SSergei Shtylyov #include <dt-bindings/clock/renesas-cpg-mssr.h> 10ecadea00SSergei Shtylyov 11ecadea00SSergei Shtylyov /* r8a77970 CPG Core Clocks */ 12ecadea00SSergei Shtylyov #define R8A77970_CLK_Z2 0 13ecadea00SSergei Shtylyov #define R8A77970_CLK_ZR 1 14ecadea00SSergei Shtylyov #define R8A77970_CLK_ZTR 2 15ecadea00SSergei Shtylyov #define R8A77970_CLK_ZTRD2 3 16ecadea00SSergei Shtylyov #define R8A77970_CLK_ZT 4 17ecadea00SSergei Shtylyov #define R8A77970_CLK_ZX 5 18ecadea00SSergei Shtylyov #define R8A77970_CLK_S1D1 6 19ecadea00SSergei Shtylyov #define R8A77970_CLK_S1D2 7 20ecadea00SSergei Shtylyov #define R8A77970_CLK_S1D4 8 21ecadea00SSergei Shtylyov #define R8A77970_CLK_S2D1 9 22ecadea00SSergei Shtylyov #define R8A77970_CLK_S2D2 10 23ecadea00SSergei Shtylyov #define R8A77970_CLK_S2D4 11 24ecadea00SSergei Shtylyov #define R8A77970_CLK_LB 12 25ecadea00SSergei Shtylyov #define R8A77970_CLK_CL 13 26ecadea00SSergei Shtylyov #define R8A77970_CLK_ZB3 14 27ecadea00SSergei Shtylyov #define R8A77970_CLK_ZB3D2 15 28ecadea00SSergei Shtylyov #define R8A77970_CLK_DDR 16 29ecadea00SSergei Shtylyov #define R8A77970_CLK_CR 17 30ecadea00SSergei Shtylyov #define R8A77970_CLK_CRD2 18 31ecadea00SSergei Shtylyov #define R8A77970_CLK_SD0H 19 32ecadea00SSergei Shtylyov #define R8A77970_CLK_SD0 20 33ecadea00SSergei Shtylyov #define R8A77970_CLK_RPC 21 34ecadea00SSergei Shtylyov #define R8A77970_CLK_RPCD2 22 35ecadea00SSergei Shtylyov #define R8A77970_CLK_MSO 23 36ecadea00SSergei Shtylyov #define R8A77970_CLK_CANFD 24 37ecadea00SSergei Shtylyov #define R8A77970_CLK_CSI0 25 38ecadea00SSergei Shtylyov #define R8A77970_CLK_FRAY 26 39ecadea00SSergei Shtylyov #define R8A77970_CLK_CP 27 40ecadea00SSergei Shtylyov #define R8A77970_CLK_CPEX 28 41ecadea00SSergei Shtylyov #define R8A77970_CLK_R 29 42ecadea00SSergei Shtylyov #define R8A77970_CLK_OSC 30 43ecadea00SSergei Shtylyov 44ecadea00SSergei Shtylyov #endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */ 45