12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2bdba0101SUlrich Hecht /* 3bdba0101SUlrich Hecht * Copyright 2014 Ulrich Hecht 4bdba0101SUlrich Hecht */ 5bdba0101SUlrich Hecht 6bdba0101SUlrich Hecht #ifndef __DT_BINDINGS_CLOCK_R8A73A4_H__ 7bdba0101SUlrich Hecht #define __DT_BINDINGS_CLOCK_R8A73A4_H__ 8bdba0101SUlrich Hecht 9bdba0101SUlrich Hecht /* CPG */ 10bdba0101SUlrich Hecht #define R8A73A4_CLK_MAIN 0 11bdba0101SUlrich Hecht #define R8A73A4_CLK_PLL0 1 12bdba0101SUlrich Hecht #define R8A73A4_CLK_PLL1 2 13bdba0101SUlrich Hecht #define R8A73A4_CLK_PLL2 3 14bdba0101SUlrich Hecht #define R8A73A4_CLK_PLL2S 4 15bdba0101SUlrich Hecht #define R8A73A4_CLK_PLL2H 5 16bdba0101SUlrich Hecht #define R8A73A4_CLK_Z 6 17bdba0101SUlrich Hecht #define R8A73A4_CLK_Z2 7 18bdba0101SUlrich Hecht #define R8A73A4_CLK_I 8 19bdba0101SUlrich Hecht #define R8A73A4_CLK_M3 9 20bdba0101SUlrich Hecht #define R8A73A4_CLK_B 10 21bdba0101SUlrich Hecht #define R8A73A4_CLK_M1 11 22bdba0101SUlrich Hecht #define R8A73A4_CLK_M2 12 23bdba0101SUlrich Hecht #define R8A73A4_CLK_ZX 13 24bdba0101SUlrich Hecht #define R8A73A4_CLK_ZS 14 25bdba0101SUlrich Hecht #define R8A73A4_CLK_HP 15 26bdba0101SUlrich Hecht 27*ecc79ab9SGeert Uytterhoeven /* MSTP1 */ 28*ecc79ab9SGeert Uytterhoeven #define R8A73A4_CLK_TMU0 25 29*ecc79ab9SGeert Uytterhoeven #define R8A73A4_CLK_TMU3 21 30*ecc79ab9SGeert Uytterhoeven 31bdba0101SUlrich Hecht /* MSTP2 */ 32bdba0101SUlrich Hecht #define R8A73A4_CLK_DMAC 18 33bdba0101SUlrich Hecht #define R8A73A4_CLK_SCIFB3 17 34bdba0101SUlrich Hecht #define R8A73A4_CLK_SCIFB2 16 35bdba0101SUlrich Hecht #define R8A73A4_CLK_SCIFB1 7 36bdba0101SUlrich Hecht #define R8A73A4_CLK_SCIFB0 6 37bdba0101SUlrich Hecht #define R8A73A4_CLK_SCIFA0 4 38bdba0101SUlrich Hecht #define R8A73A4_CLK_SCIFA1 3 39bdba0101SUlrich Hecht 40bdba0101SUlrich Hecht /* MSTP3 */ 41bdba0101SUlrich Hecht #define R8A73A4_CLK_CMT1 29 42bdba0101SUlrich Hecht #define R8A73A4_CLK_IIC1 23 43bdba0101SUlrich Hecht #define R8A73A4_CLK_IIC0 18 44bdba0101SUlrich Hecht #define R8A73A4_CLK_IIC7 17 45bdba0101SUlrich Hecht #define R8A73A4_CLK_IIC6 16 46bdba0101SUlrich Hecht #define R8A73A4_CLK_MMCIF0 15 47bdba0101SUlrich Hecht #define R8A73A4_CLK_SDHI0 14 48bdba0101SUlrich Hecht #define R8A73A4_CLK_SDHI1 13 49bdba0101SUlrich Hecht #define R8A73A4_CLK_SDHI2 12 50bdba0101SUlrich Hecht #define R8A73A4_CLK_MMCIF1 5 51bdba0101SUlrich Hecht #define R8A73A4_CLK_IIC2 0 52bdba0101SUlrich Hecht 53bdba0101SUlrich Hecht /* MSTP4 */ 54bdba0101SUlrich Hecht #define R8A73A4_CLK_IIC3 11 55bdba0101SUlrich Hecht #define R8A73A4_CLK_IIC4 10 56bdba0101SUlrich Hecht #define R8A73A4_CLK_IIC5 9 57c11333ccSGeert Uytterhoeven #define R8A73A4_CLK_INTC_SYS 8 581c2a7eb7SGeert Uytterhoeven #define R8A73A4_CLK_IRQC 7 59bdba0101SUlrich Hecht 60bdba0101SUlrich Hecht /* MSTP5 */ 61bdba0101SUlrich Hecht #define R8A73A4_CLK_THERMAL 22 62bdba0101SUlrich Hecht #define R8A73A4_CLK_IIC8 15 63bdba0101SUlrich Hecht 64bdba0101SUlrich Hecht #endif /* __DT_BINDINGS_CLOCK_R8A73A4_H__ */ 65