1bb213e13SRajendra Nayak /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2bb213e13SRajendra Nayak /* 3bb213e13SRajendra Nayak * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4bb213e13SRajendra Nayak */ 5bb213e13SRajendra Nayak 6bb213e13SRajendra Nayak #ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H 7bb213e13SRajendra Nayak #define _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H 8bb213e13SRajendra Nayak 9bb213e13SRajendra Nayak /* GPU_CC clocks */ 10bb213e13SRajendra Nayak #define GPU_CC_AHB_CLK 0 11bb213e13SRajendra Nayak #define GPU_CC_CB_CLK 1 12bb213e13SRajendra Nayak #define GPU_CC_CRC_AHB_CLK 2 13bb213e13SRajendra Nayak #define GPU_CC_CX_FF_CLK 3 14bb213e13SRajendra Nayak #define GPU_CC_CX_GMU_CLK 4 15bb213e13SRajendra Nayak #define GPU_CC_CXO_AON_CLK 5 16bb213e13SRajendra Nayak #define GPU_CC_CXO_CLK 6 17bb213e13SRajendra Nayak #define GPU_CC_DEMET_CLK 7 18bb213e13SRajendra Nayak #define GPU_CC_DEMET_DIV_CLK_SRC 8 19bb213e13SRajendra Nayak #define GPU_CC_FF_CLK_SRC 9 20bb213e13SRajendra Nayak #define GPU_CC_FREQ_MEASURE_CLK 10 21bb213e13SRajendra Nayak #define GPU_CC_GMU_CLK_SRC 11 22bb213e13SRajendra Nayak #define GPU_CC_GX_GMU_CLK 12 23bb213e13SRajendra Nayak #define GPU_CC_GX_VSENSE_CLK 13 24bb213e13SRajendra Nayak #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 25bb213e13SRajendra Nayak #define GPU_CC_HUB_AON_CLK 15 26bb213e13SRajendra Nayak #define GPU_CC_HUB_CLK_SRC 16 27bb213e13SRajendra Nayak #define GPU_CC_HUB_CX_INT_CLK 17 28bb213e13SRajendra Nayak #define GPU_CC_MEMNOC_GFX_CLK 18 29bb213e13SRajendra Nayak #define GPU_CC_MND1X_0_GFX3D_CLK 19 30bb213e13SRajendra Nayak #define GPU_CC_MND1X_1_GFX3D_CLK 20 31bb213e13SRajendra Nayak #define GPU_CC_PLL0 21 32bb213e13SRajendra Nayak #define GPU_CC_PLL1 22 33bb213e13SRajendra Nayak #define GPU_CC_SLEEP_CLK 23 34bb213e13SRajendra Nayak #define GPU_CC_XO_CLK_SRC 24 35bb213e13SRajendra Nayak #define GPU_CC_XO_DIV_CLK_SRC 25 36*e8f81b56SKonrad Dybcio #define GPU_CC_CX_ACCU_SHIFT_CLK 26 37*e8f81b56SKonrad Dybcio #define GPU_CC_GX_ACCU_SHIFT_CLK 27 38bb213e13SRajendra Nayak 39bb213e13SRajendra Nayak /* GDSCs */ 40bb213e13SRajendra Nayak #define GPU_CX_GDSC 0 41bb213e13SRajendra Nayak #define GPU_GX_GDSC 1 42bb213e13SRajendra Nayak 43*e8f81b56SKonrad Dybcio /* GPU_CC resets */ 44*e8f81b56SKonrad Dybcio #define GPU_CC_ACD_BCR 0 45*e8f81b56SKonrad Dybcio #define GPU_CC_CB_BCR 1 46*e8f81b56SKonrad Dybcio #define GPU_CC_CX_BCR 2 47*e8f81b56SKonrad Dybcio #define GPU_CC_FAST_HUB_BCR 3 48*e8f81b56SKonrad Dybcio #define GPU_CC_FF_BCR 4 49*e8f81b56SKonrad Dybcio #define GPU_CC_GFX3D_AON_BCR 5 50*e8f81b56SKonrad Dybcio #define GPU_CC_GMU_BCR 6 51*e8f81b56SKonrad Dybcio #define GPU_CC_GX_BCR 7 52*e8f81b56SKonrad Dybcio #define GPU_CC_XO_BCR 8 53*e8f81b56SKonrad Dybcio 54bb213e13SRajendra Nayak #endif 55