1*b69d9321SNeil Armstrong /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*b69d9321SNeil Armstrong /* 3*b69d9321SNeil Armstrong * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4*b69d9321SNeil Armstrong * Copyright (c) 2023, Linaro Limited 5*b69d9321SNeil Armstrong */ 6*b69d9321SNeil Armstrong 7*b69d9321SNeil Armstrong #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8650_H 8*b69d9321SNeil Armstrong #define _DT_BINDINGS_CLK_QCOM_GCC_SM8650_H 9*b69d9321SNeil Armstrong 10*b69d9321SNeil Armstrong /* GCC clocks */ 11*b69d9321SNeil Armstrong #define GCC_AGGRE_NOC_PCIE_AXI_CLK 0 12*b69d9321SNeil Armstrong #define GCC_AGGRE_UFS_PHY_AXI_CLK 1 13*b69d9321SNeil Armstrong #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 2 14*b69d9321SNeil Armstrong #define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 15*b69d9321SNeil Armstrong #define GCC_BOOT_ROM_AHB_CLK 4 16*b69d9321SNeil Armstrong #define GCC_CAMERA_AHB_CLK 5 17*b69d9321SNeil Armstrong #define GCC_CAMERA_HF_AXI_CLK 6 18*b69d9321SNeil Armstrong #define GCC_CAMERA_SF_AXI_CLK 7 19*b69d9321SNeil Armstrong #define GCC_CAMERA_XO_CLK 8 20*b69d9321SNeil Armstrong #define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9 21*b69d9321SNeil Armstrong #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10 22*b69d9321SNeil Armstrong #define GCC_CNOC_PCIE_SF_AXI_CLK 11 23*b69d9321SNeil Armstrong #define GCC_DDRSS_GPU_AXI_CLK 12 24*b69d9321SNeil Armstrong #define GCC_DDRSS_PCIE_SF_QTB_CLK 13 25*b69d9321SNeil Armstrong #define GCC_DISP_AHB_CLK 14 26*b69d9321SNeil Armstrong #define GCC_DISP_HF_AXI_CLK 15 27*b69d9321SNeil Armstrong #define GCC_DISP_XO_CLK 16 28*b69d9321SNeil Armstrong #define GCC_GP1_CLK 17 29*b69d9321SNeil Armstrong #define GCC_GP1_CLK_SRC 18 30*b69d9321SNeil Armstrong #define GCC_GP2_CLK 19 31*b69d9321SNeil Armstrong #define GCC_GP2_CLK_SRC 20 32*b69d9321SNeil Armstrong #define GCC_GP3_CLK 21 33*b69d9321SNeil Armstrong #define GCC_GP3_CLK_SRC 22 34*b69d9321SNeil Armstrong #define GCC_GPLL0 23 35*b69d9321SNeil Armstrong #define GCC_GPLL0_OUT_EVEN 24 36*b69d9321SNeil Armstrong #define GCC_GPLL1 25 37*b69d9321SNeil Armstrong #define GCC_GPLL3 26 38*b69d9321SNeil Armstrong #define GCC_GPLL4 27 39*b69d9321SNeil Armstrong #define GCC_GPLL6 28 40*b69d9321SNeil Armstrong #define GCC_GPLL7 29 41*b69d9321SNeil Armstrong #define GCC_GPLL9 30 42*b69d9321SNeil Armstrong #define GCC_GPU_CFG_AHB_CLK 31 43*b69d9321SNeil Armstrong #define GCC_GPU_GPLL0_CLK_SRC 32 44*b69d9321SNeil Armstrong #define GCC_GPU_GPLL0_DIV_CLK_SRC 33 45*b69d9321SNeil Armstrong #define GCC_GPU_MEMNOC_GFX_CLK 34 46*b69d9321SNeil Armstrong #define GCC_GPU_SNOC_DVM_GFX_CLK 35 47*b69d9321SNeil Armstrong #define GCC_PCIE_0_AUX_CLK 36 48*b69d9321SNeil Armstrong #define GCC_PCIE_0_AUX_CLK_SRC 37 49*b69d9321SNeil Armstrong #define GCC_PCIE_0_CFG_AHB_CLK 38 50*b69d9321SNeil Armstrong #define GCC_PCIE_0_MSTR_AXI_CLK 39 51*b69d9321SNeil Armstrong #define GCC_PCIE_0_PHY_RCHNG_CLK 40 52*b69d9321SNeil Armstrong #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 41 53*b69d9321SNeil Armstrong #define GCC_PCIE_0_PIPE_CLK 42 54*b69d9321SNeil Armstrong #define GCC_PCIE_0_PIPE_CLK_SRC 43 55*b69d9321SNeil Armstrong #define GCC_PCIE_0_SLV_AXI_CLK 44 56*b69d9321SNeil Armstrong #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45 57*b69d9321SNeil Armstrong #define GCC_PCIE_1_AUX_CLK 46 58*b69d9321SNeil Armstrong #define GCC_PCIE_1_AUX_CLK_SRC 47 59*b69d9321SNeil Armstrong #define GCC_PCIE_1_CFG_AHB_CLK 48 60*b69d9321SNeil Armstrong #define GCC_PCIE_1_MSTR_AXI_CLK 49 61*b69d9321SNeil Armstrong #define GCC_PCIE_1_PHY_AUX_CLK 50 62*b69d9321SNeil Armstrong #define GCC_PCIE_1_PHY_AUX_CLK_SRC 51 63*b69d9321SNeil Armstrong #define GCC_PCIE_1_PHY_RCHNG_CLK 52 64*b69d9321SNeil Armstrong #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 53 65*b69d9321SNeil Armstrong #define GCC_PCIE_1_PIPE_CLK 54 66*b69d9321SNeil Armstrong #define GCC_PCIE_1_PIPE_CLK_SRC 55 67*b69d9321SNeil Armstrong #define GCC_PCIE_1_SLV_AXI_CLK 56 68*b69d9321SNeil Armstrong #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 57 69*b69d9321SNeil Armstrong #define GCC_PDM2_CLK 58 70*b69d9321SNeil Armstrong #define GCC_PDM2_CLK_SRC 59 71*b69d9321SNeil Armstrong #define GCC_PDM_AHB_CLK 60 72*b69d9321SNeil Armstrong #define GCC_PDM_XO4_CLK 61 73*b69d9321SNeil Armstrong #define GCC_QMIP_CAMERA_NRT_AHB_CLK 62 74*b69d9321SNeil Armstrong #define GCC_QMIP_CAMERA_RT_AHB_CLK 63 75*b69d9321SNeil Armstrong #define GCC_QMIP_DISP_AHB_CLK 64 76*b69d9321SNeil Armstrong #define GCC_QMIP_GPU_AHB_CLK 65 77*b69d9321SNeil Armstrong #define GCC_QMIP_PCIE_AHB_CLK 66 78*b69d9321SNeil Armstrong #define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 67 79*b69d9321SNeil Armstrong #define GCC_QMIP_VIDEO_CVP_AHB_CLK 68 80*b69d9321SNeil Armstrong #define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 69 81*b69d9321SNeil Armstrong #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 70 82*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_CORE_CLK 71 83*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S0_CLK 72 84*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S0_CLK_SRC 73 85*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S1_CLK 74 86*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S1_CLK_SRC 75 87*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S2_CLK 76 88*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S2_CLK_SRC 77 89*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S3_CLK 78 90*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S3_CLK_SRC 79 91*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S4_CLK 80 92*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S4_CLK_SRC 81 93*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S5_CLK 82 94*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S5_CLK_SRC 83 95*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S6_CLK 84 96*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S6_CLK_SRC 85 97*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S7_CLK 86 98*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S7_CLK_SRC 87 99*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S8_CLK 88 100*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S8_CLK_SRC 89 101*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S9_CLK 90 102*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S9_CLK_SRC 91 103*b69d9321SNeil Armstrong #define GCC_QUPV3_I2C_S_AHB_CLK 92 104*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_CORE_2X_CLK 93 105*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_CORE_CLK 94 106*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_QSPI_REF_CLK 95 107*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 96 108*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S0_CLK 97 109*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S0_CLK_SRC 98 110*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S1_CLK 99 111*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S1_CLK_SRC 100 112*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S2_CLK 101 113*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S2_CLK_SRC 102 114*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S3_CLK 103 115*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S3_CLK_SRC 104 116*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S4_CLK 105 117*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S4_CLK_SRC 106 118*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S5_CLK 107 119*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S5_CLK_SRC 108 120*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S6_CLK 109 121*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S6_CLK_SRC 110 122*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S7_CLK 111 123*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP1_S7_CLK_SRC 112 124*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_CORE_2X_CLK 113 125*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_CORE_CLK 114 126*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_IBI_CTRL_0_CLK_SRC 115 127*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_IBI_CTRL_2_CLK 116 128*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_IBI_CTRL_3_CLK 117 129*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S0_CLK 118 130*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S0_CLK_SRC 119 131*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S1_CLK 120 132*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S1_CLK_SRC 121 133*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S2_CLK 122 134*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S2_CLK_SRC 123 135*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S3_CLK 124 136*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S3_CLK_SRC 125 137*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S4_CLK 126 138*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S4_CLK_SRC 127 139*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S5_CLK 128 140*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S5_CLK_SRC 129 141*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S6_CLK 130 142*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S6_CLK_SRC 131 143*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S7_CLK 132 144*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP2_S7_CLK_SRC 133 145*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP3_CORE_2X_CLK 134 146*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP3_CORE_CLK 135 147*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP3_QSPI_REF_CLK 136 148*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 137 149*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP3_S0_CLK 138 150*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP3_S0_CLK_SRC 139 151*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP_1_M_AHB_CLK 140 152*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP_1_S_AHB_CLK 141 153*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP_2_IBI_2_AHB_CLK 142 154*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP_2_IBI_3_AHB_CLK 143 155*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP_2_M_AHB_CLK 144 156*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP_2_S_AHB_CLK 145 157*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP_3_M_AHB_CLK 146 158*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAP_3_S_AHB_CLK 147 159*b69d9321SNeil Armstrong #define GCC_SDCC2_AHB_CLK 148 160*b69d9321SNeil Armstrong #define GCC_SDCC2_APPS_CLK 149 161*b69d9321SNeil Armstrong #define GCC_SDCC2_APPS_CLK_SRC 150 162*b69d9321SNeil Armstrong #define GCC_SDCC4_AHB_CLK 151 163*b69d9321SNeil Armstrong #define GCC_SDCC4_APPS_CLK 152 164*b69d9321SNeil Armstrong #define GCC_SDCC4_APPS_CLK_SRC 153 165*b69d9321SNeil Armstrong #define GCC_UFS_PHY_AHB_CLK 154 166*b69d9321SNeil Armstrong #define GCC_UFS_PHY_AXI_CLK 155 167*b69d9321SNeil Armstrong #define GCC_UFS_PHY_AXI_CLK_SRC 156 168*b69d9321SNeil Armstrong #define GCC_UFS_PHY_AXI_HW_CTL_CLK 157 169*b69d9321SNeil Armstrong #define GCC_UFS_PHY_ICE_CORE_CLK 158 170*b69d9321SNeil Armstrong #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 159 171*b69d9321SNeil Armstrong #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 160 172*b69d9321SNeil Armstrong #define GCC_UFS_PHY_PHY_AUX_CLK 161 173*b69d9321SNeil Armstrong #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 162 174*b69d9321SNeil Armstrong #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 163 175*b69d9321SNeil Armstrong #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164 176*b69d9321SNeil Armstrong #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 165 177*b69d9321SNeil Armstrong #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 166 178*b69d9321SNeil Armstrong #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 167 179*b69d9321SNeil Armstrong #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168 180*b69d9321SNeil Armstrong #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 169 181*b69d9321SNeil Armstrong #define GCC_UFS_PHY_UNIPRO_CORE_CLK 170 182*b69d9321SNeil Armstrong #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 171 183*b69d9321SNeil Armstrong #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 172 184*b69d9321SNeil Armstrong #define GCC_USB30_PRIM_MASTER_CLK 173 185*b69d9321SNeil Armstrong #define GCC_USB30_PRIM_MASTER_CLK_SRC 174 186*b69d9321SNeil Armstrong #define GCC_USB30_PRIM_MOCK_UTMI_CLK 175 187*b69d9321SNeil Armstrong #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176 188*b69d9321SNeil Armstrong #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177 189*b69d9321SNeil Armstrong #define GCC_USB30_PRIM_SLEEP_CLK 178 190*b69d9321SNeil Armstrong #define GCC_USB3_PRIM_PHY_AUX_CLK 179 191*b69d9321SNeil Armstrong #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 180 192*b69d9321SNeil Armstrong #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 181 193*b69d9321SNeil Armstrong #define GCC_USB3_PRIM_PHY_PIPE_CLK 182 194*b69d9321SNeil Armstrong #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 183 195*b69d9321SNeil Armstrong #define GCC_VIDEO_AHB_CLK 184 196*b69d9321SNeil Armstrong #define GCC_VIDEO_AXI0_CLK 185 197*b69d9321SNeil Armstrong #define GCC_VIDEO_AXI1_CLK 186 198*b69d9321SNeil Armstrong #define GCC_VIDEO_XO_CLK 187 199*b69d9321SNeil Armstrong #define GCC_GPLL0_AO 188 200*b69d9321SNeil Armstrong #define GCC_GPLL0_OUT_EVEN_AO 189 201*b69d9321SNeil Armstrong #define GCC_GPLL1_AO 190 202*b69d9321SNeil Armstrong #define GCC_GPLL3_AO 191 203*b69d9321SNeil Armstrong #define GCC_GPLL4_AO 192 204*b69d9321SNeil Armstrong #define GCC_GPLL6_AO 193 205*b69d9321SNeil Armstrong 206*b69d9321SNeil Armstrong /* GCC resets */ 207*b69d9321SNeil Armstrong #define GCC_CAMERA_BCR 0 208*b69d9321SNeil Armstrong #define GCC_DISPLAY_BCR 1 209*b69d9321SNeil Armstrong #define GCC_GPU_BCR 2 210*b69d9321SNeil Armstrong #define GCC_PCIE_0_BCR 3 211*b69d9321SNeil Armstrong #define GCC_PCIE_0_LINK_DOWN_BCR 4 212*b69d9321SNeil Armstrong #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 213*b69d9321SNeil Armstrong #define GCC_PCIE_0_PHY_BCR 6 214*b69d9321SNeil Armstrong #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 215*b69d9321SNeil Armstrong #define GCC_PCIE_1_BCR 8 216*b69d9321SNeil Armstrong #define GCC_PCIE_1_LINK_DOWN_BCR 9 217*b69d9321SNeil Armstrong #define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10 218*b69d9321SNeil Armstrong #define GCC_PCIE_1_PHY_BCR 11 219*b69d9321SNeil Armstrong #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12 220*b69d9321SNeil Armstrong #define GCC_PCIE_PHY_BCR 13 221*b69d9321SNeil Armstrong #define GCC_PCIE_PHY_CFG_AHB_BCR 14 222*b69d9321SNeil Armstrong #define GCC_PCIE_PHY_COM_BCR 15 223*b69d9321SNeil Armstrong #define GCC_PDM_BCR 16 224*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAPPER_1_BCR 17 225*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAPPER_2_BCR 18 226*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAPPER_3_BCR 19 227*b69d9321SNeil Armstrong #define GCC_QUPV3_WRAPPER_I2C_BCR 20 228*b69d9321SNeil Armstrong #define GCC_QUSB2PHY_PRIM_BCR 21 229*b69d9321SNeil Armstrong #define GCC_QUSB2PHY_SEC_BCR 22 230*b69d9321SNeil Armstrong #define GCC_SDCC2_BCR 23 231*b69d9321SNeil Armstrong #define GCC_SDCC4_BCR 24 232*b69d9321SNeil Armstrong #define GCC_UFS_PHY_BCR 25 233*b69d9321SNeil Armstrong #define GCC_USB30_PRIM_BCR 26 234*b69d9321SNeil Armstrong #define GCC_USB3_DP_PHY_PRIM_BCR 27 235*b69d9321SNeil Armstrong #define GCC_USB3_DP_PHY_SEC_BCR 28 236*b69d9321SNeil Armstrong #define GCC_USB3_PHY_PRIM_BCR 29 237*b69d9321SNeil Armstrong #define GCC_USB3_PHY_SEC_BCR 30 238*b69d9321SNeil Armstrong #define GCC_USB3PHY_PHY_PRIM_BCR 31 239*b69d9321SNeil Armstrong #define GCC_USB3PHY_PHY_SEC_BCR 32 240*b69d9321SNeil Armstrong #define GCC_VIDEO_AXI0_CLK_ARES 33 241*b69d9321SNeil Armstrong #define GCC_VIDEO_AXI1_CLK_ARES 34 242*b69d9321SNeil Armstrong #define GCC_VIDEO_BCR 35 243*b69d9321SNeil Armstrong 244*b69d9321SNeil Armstrong /* GCC power domains */ 245*b69d9321SNeil Armstrong #define PCIE_0_GDSC 0 246*b69d9321SNeil Armstrong #define PCIE_0_PHY_GDSC 1 247*b69d9321SNeil Armstrong #define PCIE_1_GDSC 2 248*b69d9321SNeil Armstrong #define PCIE_1_PHY_GDSC 3 249*b69d9321SNeil Armstrong #define UFS_PHY_GDSC 4 250*b69d9321SNeil Armstrong #define UFS_MEM_PHY_GDSC 5 251*b69d9321SNeil Armstrong #define USB30_PRIM_GDSC 6 252*b69d9321SNeil Armstrong #define USB3_PHY_GDSC 7 253*b69d9321SNeil Armstrong 254*b69d9321SNeil Armstrong #endif 255