1*bad27783SDanila Tikhonov /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*bad27783SDanila Tikhonov /* 3*bad27783SDanila Tikhonov * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 4*bad27783SDanila Tikhonov * Copyright (c) 2023, Danila Tikhonov <danila@jiaxyga.com> 5*bad27783SDanila Tikhonov * Copyright (c) 2023, David Wronek <davidwronek@gmail.com> 6*bad27783SDanila Tikhonov */ 7*bad27783SDanila Tikhonov 8*bad27783SDanila Tikhonov #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM7150_H 9*bad27783SDanila Tikhonov #define _DT_BINDINGS_CLK_QCOM_GCC_SM7150_H 10*bad27783SDanila Tikhonov 11*bad27783SDanila Tikhonov /* GCC clock registers */ 12*bad27783SDanila Tikhonov #define GCC_GPLL0_MAIN_DIV_CDIV 0 13*bad27783SDanila Tikhonov #define GPLL0 1 14*bad27783SDanila Tikhonov #define GPLL0_OUT_EVEN 2 15*bad27783SDanila Tikhonov #define GPLL6 3 16*bad27783SDanila Tikhonov #define GPLL7 4 17*bad27783SDanila Tikhonov #define GCC_AGGRE_NOC_PCIE_TBU_CLK 5 18*bad27783SDanila Tikhonov #define GCC_AGGRE_UFS_PHY_AXI_CLK 6 19*bad27783SDanila Tikhonov #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 7 20*bad27783SDanila Tikhonov #define GCC_AGGRE_USB3_PRIM_AXI_CLK 8 21*bad27783SDanila Tikhonov #define GCC_APC_VS_CLK 9 22*bad27783SDanila Tikhonov #define GCC_BOOT_ROM_AHB_CLK 10 23*bad27783SDanila Tikhonov #define GCC_CAMERA_HF_AXI_CLK 11 24*bad27783SDanila Tikhonov #define GCC_CAMERA_SF_AXI_CLK 12 25*bad27783SDanila Tikhonov #define GCC_CE1_AHB_CLK 13 26*bad27783SDanila Tikhonov #define GCC_CE1_AXI_CLK 14 27*bad27783SDanila Tikhonov #define GCC_CE1_CLK 15 28*bad27783SDanila Tikhonov #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 16 29*bad27783SDanila Tikhonov #define GCC_CPUSS_AHB_CLK 17 30*bad27783SDanila Tikhonov #define GCC_CPUSS_AHB_CLK_SRC 18 31*bad27783SDanila Tikhonov #define GCC_CPUSS_RBCPR_CLK 19 32*bad27783SDanila Tikhonov #define GCC_CPUSS_RBCPR_CLK_SRC 20 33*bad27783SDanila Tikhonov #define GCC_DDRSS_GPU_AXI_CLK 21 34*bad27783SDanila Tikhonov #define GCC_DISP_GPLL0_CLK_SRC 22 35*bad27783SDanila Tikhonov #define GCC_DISP_GPLL0_DIV_CLK_SRC 23 36*bad27783SDanila Tikhonov #define GCC_DISP_HF_AXI_CLK 24 37*bad27783SDanila Tikhonov #define GCC_DISP_SF_AXI_CLK 25 38*bad27783SDanila Tikhonov #define GCC_GP1_CLK 26 39*bad27783SDanila Tikhonov #define GCC_GP1_CLK_SRC 27 40*bad27783SDanila Tikhonov #define GCC_GP2_CLK 28 41*bad27783SDanila Tikhonov #define GCC_GP2_CLK_SRC 29 42*bad27783SDanila Tikhonov #define GCC_GP3_CLK 30 43*bad27783SDanila Tikhonov #define GCC_GP3_CLK_SRC 31 44*bad27783SDanila Tikhonov #define GCC_GPU_GPLL0_CLK_SRC 32 45*bad27783SDanila Tikhonov #define GCC_GPU_GPLL0_DIV_CLK_SRC 33 46*bad27783SDanila Tikhonov #define GCC_GPU_MEMNOC_GFX_CLK 34 47*bad27783SDanila Tikhonov #define GCC_GPU_SNOC_DVM_GFX_CLK 35 48*bad27783SDanila Tikhonov #define GCC_GPU_VS_CLK 36 49*bad27783SDanila Tikhonov #define GCC_NPU_AXI_CLK 37 50*bad27783SDanila Tikhonov #define GCC_NPU_CFG_AHB_CLK 38 51*bad27783SDanila Tikhonov #define GCC_NPU_GPLL0_CLK_SRC 39 52*bad27783SDanila Tikhonov #define GCC_NPU_GPLL0_DIV_CLK_SRC 40 53*bad27783SDanila Tikhonov #define GCC_PCIE_0_AUX_CLK 41 54*bad27783SDanila Tikhonov #define GCC_PCIE_0_AUX_CLK_SRC 42 55*bad27783SDanila Tikhonov #define GCC_PCIE_0_CFG_AHB_CLK 43 56*bad27783SDanila Tikhonov #define GCC_PCIE_0_CLKREF_CLK 44 57*bad27783SDanila Tikhonov #define GCC_PCIE_0_MSTR_AXI_CLK 45 58*bad27783SDanila Tikhonov #define GCC_PCIE_0_PIPE_CLK 46 59*bad27783SDanila Tikhonov #define GCC_PCIE_0_SLV_AXI_CLK 47 60*bad27783SDanila Tikhonov #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 61*bad27783SDanila Tikhonov #define GCC_PCIE_PHY_AUX_CLK 49 62*bad27783SDanila Tikhonov #define GCC_PCIE_PHY_REFGEN_CLK 50 63*bad27783SDanila Tikhonov #define GCC_PCIE_PHY_REFGEN_CLK_SRC 51 64*bad27783SDanila Tikhonov #define GCC_PDM2_CLK 52 65*bad27783SDanila Tikhonov #define GCC_PDM2_CLK_SRC 53 66*bad27783SDanila Tikhonov #define GCC_PDM_AHB_CLK 54 67*bad27783SDanila Tikhonov #define GCC_PDM_XO4_CLK 55 68*bad27783SDanila Tikhonov #define GCC_PRNG_AHB_CLK 56 69*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_CORE_2X_CLK 57 70*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_CORE_CLK 58 71*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S0_CLK 59 72*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S0_CLK_SRC 60 73*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S1_CLK 61 74*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S1_CLK_SRC 62 75*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S2_CLK 63 76*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S2_CLK_SRC 64 77*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S3_CLK 65 78*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S3_CLK_SRC 66 79*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S4_CLK 67 80*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S4_CLK_SRC 68 81*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S5_CLK 69 82*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S5_CLK_SRC 70 83*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S6_CLK 71 84*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S6_CLK_SRC 72 85*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S7_CLK 73 86*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP0_S7_CLK_SRC 74 87*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_CORE_2X_CLK 75 88*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_CORE_CLK 76 89*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S0_CLK 77 90*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S0_CLK_SRC 78 91*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S1_CLK 79 92*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S1_CLK_SRC 80 93*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S2_CLK 81 94*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S2_CLK_SRC 82 95*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S3_CLK 83 96*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S3_CLK_SRC 84 97*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S4_CLK 85 98*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S4_CLK_SRC 86 99*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S5_CLK 87 100*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S5_CLK_SRC 88 101*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S6_CLK 89 102*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S6_CLK_SRC 90 103*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S7_CLK 91 104*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP1_S7_CLK_SRC 92 105*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP_0_M_AHB_CLK 93 106*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP_0_S_AHB_CLK 94 107*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP_1_M_AHB_CLK 95 108*bad27783SDanila Tikhonov #define GCC_QUPV3_WRAP_1_S_AHB_CLK 96 109*bad27783SDanila Tikhonov #define GCC_SDCC1_AHB_CLK 97 110*bad27783SDanila Tikhonov #define GCC_SDCC1_APPS_CLK 98 111*bad27783SDanila Tikhonov #define GCC_SDCC1_APPS_CLK_SRC 99 112*bad27783SDanila Tikhonov #define GCC_SDCC1_ICE_CORE_CLK 100 113*bad27783SDanila Tikhonov #define GCC_SDCC1_ICE_CORE_CLK_SRC 101 114*bad27783SDanila Tikhonov #define GCC_SDCC2_AHB_CLK 102 115*bad27783SDanila Tikhonov #define GCC_SDCC2_APPS_CLK 103 116*bad27783SDanila Tikhonov #define GCC_SDCC2_APPS_CLK_SRC 104 117*bad27783SDanila Tikhonov #define GCC_SDCC4_AHB_CLK 105 118*bad27783SDanila Tikhonov #define GCC_SDCC4_APPS_CLK 106 119*bad27783SDanila Tikhonov #define GCC_SDCC4_APPS_CLK_SRC 107 120*bad27783SDanila Tikhonov #define GCC_SYS_NOC_CPUSS_AHB_CLK 108 121*bad27783SDanila Tikhonov #define GCC_TSIF_AHB_CLK 109 122*bad27783SDanila Tikhonov #define GCC_TSIF_INACTIVITY_TIMERS_CLK 110 123*bad27783SDanila Tikhonov #define GCC_TSIF_REF_CLK 111 124*bad27783SDanila Tikhonov #define GCC_TSIF_REF_CLK_SRC 112 125*bad27783SDanila Tikhonov #define GCC_UFS_MEM_CLKREF_CLK 113 126*bad27783SDanila Tikhonov #define GCC_UFS_PHY_AHB_CLK 114 127*bad27783SDanila Tikhonov #define GCC_UFS_PHY_AXI_CLK 115 128*bad27783SDanila Tikhonov #define GCC_UFS_PHY_AXI_CLK_SRC 116 129*bad27783SDanila Tikhonov #define GCC_UFS_PHY_AXI_HW_CTL_CLK 117 130*bad27783SDanila Tikhonov #define GCC_UFS_PHY_ICE_CORE_CLK 118 131*bad27783SDanila Tikhonov #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 119 132*bad27783SDanila Tikhonov #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 120 133*bad27783SDanila Tikhonov #define GCC_UFS_PHY_PHY_AUX_CLK 121 134*bad27783SDanila Tikhonov #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 122 135*bad27783SDanila Tikhonov #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 123 136*bad27783SDanila Tikhonov #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 124 137*bad27783SDanila Tikhonov #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 125 138*bad27783SDanila Tikhonov #define GCC_UFS_PHY_UNIPRO_CORE_CLK 126 139*bad27783SDanila Tikhonov #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 127 140*bad27783SDanila Tikhonov #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 128 141*bad27783SDanila Tikhonov #define GCC_USB30_PRIM_MASTER_CLK 129 142*bad27783SDanila Tikhonov #define GCC_USB30_PRIM_MASTER_CLK_SRC 130 143*bad27783SDanila Tikhonov #define GCC_USB30_PRIM_MOCK_UTMI_CLK 131 144*bad27783SDanila Tikhonov #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 132 145*bad27783SDanila Tikhonov #define GCC_USB30_PRIM_SLEEP_CLK 133 146*bad27783SDanila Tikhonov #define GCC_USB3_PRIM_CLKREF_CLK 134 147*bad27783SDanila Tikhonov #define GCC_USB3_PRIM_PHY_AUX_CLK 135 148*bad27783SDanila Tikhonov #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 136 149*bad27783SDanila Tikhonov #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 137 150*bad27783SDanila Tikhonov #define GCC_USB3_PRIM_PHY_PIPE_CLK 138 151*bad27783SDanila Tikhonov #define GCC_USB_PHY_CFG_AHB2PHY_CLK 139 152*bad27783SDanila Tikhonov #define GCC_VDDA_VS_CLK 140 153*bad27783SDanila Tikhonov #define GCC_VDDCX_VS_CLK 141 154*bad27783SDanila Tikhonov #define GCC_VDDMX_VS_CLK 142 155*bad27783SDanila Tikhonov #define GCC_VIDEO_AXI_CLK 143 156*bad27783SDanila Tikhonov #define GCC_VS_CTRL_AHB_CLK 144 157*bad27783SDanila Tikhonov #define GCC_VS_CTRL_CLK 145 158*bad27783SDanila Tikhonov #define GCC_VS_CTRL_CLK_SRC 146 159*bad27783SDanila Tikhonov #define GCC_VSENSOR_CLK_SRC 147 160*bad27783SDanila Tikhonov 161*bad27783SDanila Tikhonov /* GCC Resets */ 162*bad27783SDanila Tikhonov #define GCC_PCIE_0_BCR 0 163*bad27783SDanila Tikhonov #define GCC_PCIE_PHY_BCR 1 164*bad27783SDanila Tikhonov #define GCC_PCIE_PHY_COM_BCR 2 165*bad27783SDanila Tikhonov #define GCC_UFS_PHY_BCR 3 166*bad27783SDanila Tikhonov #define GCC_USB30_PRIM_BCR 4 167*bad27783SDanila Tikhonov #define GCC_USB3_DP_PHY_PRIM_BCR 5 168*bad27783SDanila Tikhonov #define GCC_USB3_DP_PHY_SEC_BCR 6 169*bad27783SDanila Tikhonov #define GCC_USB3_PHY_PRIM_BCR 7 170*bad27783SDanila Tikhonov #define GCC_USB3_PHY_SEC_BCR 8 171*bad27783SDanila Tikhonov #define GCC_QUSB2PHY_PRIM_BCR 9 172*bad27783SDanila Tikhonov #define GCC_VIDEO_AXI_CLK_BCR 10 173*bad27783SDanila Tikhonov 174*bad27783SDanila Tikhonov /* GCC GDSCRs */ 175*bad27783SDanila Tikhonov #define PCIE_0_GDSC 0 176*bad27783SDanila Tikhonov #define UFS_PHY_GDSC 1 177*bad27783SDanila Tikhonov #define USB30_PRIM_GDSC 2 178*bad27783SDanila Tikhonov #define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 3 179*bad27783SDanila Tikhonov #define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 4 180*bad27783SDanila Tikhonov #define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 5 181*bad27783SDanila Tikhonov #define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 6 182*bad27783SDanila Tikhonov #define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 7 183*bad27783SDanila Tikhonov #define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 8 184*bad27783SDanila Tikhonov #define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 9 185*bad27783SDanila Tikhonov 186*bad27783SDanila Tikhonov #endif 187