xref: /linux/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,ipq5332-gcc.h (revision 9f3a2ba62c7226a6604b8aaeb92b5ff906fa4e6b)
1*f99cdbd8SKathiravan T /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2*f99cdbd8SKathiravan T /*
3*f99cdbd8SKathiravan T  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4*f99cdbd8SKathiravan T  */
5*f99cdbd8SKathiravan T 
6*f99cdbd8SKathiravan T #ifndef _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H
7*f99cdbd8SKathiravan T #define _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H
8*f99cdbd8SKathiravan T 
9*f99cdbd8SKathiravan T #define GPLL0_MAIN					0
10*f99cdbd8SKathiravan T #define GPLL0						1
11*f99cdbd8SKathiravan T #define GPLL2_MAIN					2
12*f99cdbd8SKathiravan T #define GPLL2						3
13*f99cdbd8SKathiravan T #define GPLL4_MAIN					4
14*f99cdbd8SKathiravan T #define GPLL4						5
15*f99cdbd8SKathiravan T #define GCC_ADSS_PWM_CLK				6
16*f99cdbd8SKathiravan T #define GCC_ADSS_PWM_CLK_SRC				7
17*f99cdbd8SKathiravan T #define GCC_AHB_CLK					8
18*f99cdbd8SKathiravan T #define GCC_APSS_AXI_CLK_SRC				9
19*f99cdbd8SKathiravan T #define GCC_BLSP1_AHB_CLK				10
20*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP1_I2C_APPS_CLK			11
21*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP1_SPI_APPS_CLK			12
22*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC			13
23*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP2_I2C_APPS_CLK			14
24*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP2_SPI_APPS_CLK			15
25*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC			16
26*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP3_I2C_APPS_CLK			17
27*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP3_SPI_APPS_CLK			18
28*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC			19
29*f99cdbd8SKathiravan T #define GCC_BLSP1_SLEEP_CLK				20
30*f99cdbd8SKathiravan T #define GCC_BLSP1_UART1_APPS_CLK			21
31*f99cdbd8SKathiravan T #define GCC_BLSP1_UART1_APPS_CLK_SRC			22
32*f99cdbd8SKathiravan T #define GCC_BLSP1_UART2_APPS_CLK			23
33*f99cdbd8SKathiravan T #define GCC_BLSP1_UART2_APPS_CLK_SRC			24
34*f99cdbd8SKathiravan T #define GCC_BLSP1_UART3_APPS_CLK			25
35*f99cdbd8SKathiravan T #define GCC_BLSP1_UART3_APPS_CLK_SRC			26
36*f99cdbd8SKathiravan T #define GCC_CE_AHB_CLK					27
37*f99cdbd8SKathiravan T #define GCC_CE_AXI_CLK					28
38*f99cdbd8SKathiravan T #define GCC_CE_PCNOC_AHB_CLK				29
39*f99cdbd8SKathiravan T #define GCC_CMN_12GPLL_AHB_CLK				30
40*f99cdbd8SKathiravan T #define GCC_CMN_12GPLL_APU_CLK				31
41*f99cdbd8SKathiravan T #define GCC_CMN_12GPLL_SYS_CLK				32
42*f99cdbd8SKathiravan T #define GCC_GP1_CLK					33
43*f99cdbd8SKathiravan T #define GCC_GP1_CLK_SRC					34
44*f99cdbd8SKathiravan T #define GCC_GP2_CLK					35
45*f99cdbd8SKathiravan T #define GCC_GP2_CLK_SRC					36
46*f99cdbd8SKathiravan T #define GCC_LPASS_CORE_AXIM_CLK				37
47*f99cdbd8SKathiravan T #define GCC_LPASS_SWAY_CLK				38
48*f99cdbd8SKathiravan T #define GCC_LPASS_SWAY_CLK_SRC				39
49*f99cdbd8SKathiravan T #define GCC_MDIO_AHB_CLK				40
50*f99cdbd8SKathiravan T #define GCC_MDIO_SLAVE_AHB_CLK				41
51*f99cdbd8SKathiravan T #define GCC_MEM_NOC_Q6_AXI_CLK				42
52*f99cdbd8SKathiravan T #define GCC_MEM_NOC_TS_CLK				43
53*f99cdbd8SKathiravan T #define GCC_NSS_TS_CLK					44
54*f99cdbd8SKathiravan T #define GCC_NSS_TS_CLK_SRC				45
55*f99cdbd8SKathiravan T #define GCC_NSSCC_CLK					46
56*f99cdbd8SKathiravan T #define GCC_NSSCFG_CLK					47
57*f99cdbd8SKathiravan T #define GCC_NSSNOC_ATB_CLK				48
58*f99cdbd8SKathiravan T #define GCC_NSSNOC_NSSCC_CLK				49
59*f99cdbd8SKathiravan T #define GCC_NSSNOC_QOSGEN_REF_CLK			50
60*f99cdbd8SKathiravan T #define GCC_NSSNOC_SNOC_1_CLK				51
61*f99cdbd8SKathiravan T #define GCC_NSSNOC_SNOC_CLK				52
62*f99cdbd8SKathiravan T #define GCC_NSSNOC_TIMEOUT_REF_CLK			53
63*f99cdbd8SKathiravan T #define GCC_NSSNOC_XO_DCD_CLK				54
64*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AHB_CLK				55
65*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AUX_CLK				56
66*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_CLK_SRC			57
67*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_M_CLK				58
68*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK			59
69*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_S_CLK				60
70*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_PIPE_CLK				61
71*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_RCHG_CLK				62
72*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_RCHG_CLK_SRC			63
73*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AHB_CLK				64
74*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AUX_CLK				65
75*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_CLK_SRC			66
76*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_M_CLK				67
77*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK			68
78*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_S_CLK				69
79*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_PIPE_CLK				70
80*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_RCHG_CLK				71
81*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_RCHG_CLK_SRC			72
82*f99cdbd8SKathiravan T #define GCC_PCIE3X1_PHY_AHB_CLK				73
83*f99cdbd8SKathiravan T #define GCC_PCIE3X2_AHB_CLK				74
84*f99cdbd8SKathiravan T #define GCC_PCIE3X2_AUX_CLK				75
85*f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_M_CLK				76
86*f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_M_CLK_SRC			77
87*f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_S_BRIDGE_CLK			78
88*f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_S_CLK				79
89*f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_S_CLK_SRC			80
90*f99cdbd8SKathiravan T #define GCC_PCIE3X2_PHY_AHB_CLK				81
91*f99cdbd8SKathiravan T #define GCC_PCIE3X2_PIPE_CLK				82
92*f99cdbd8SKathiravan T #define GCC_PCIE3X2_RCHG_CLK				83
93*f99cdbd8SKathiravan T #define GCC_PCIE3X2_RCHG_CLK_SRC			84
94*f99cdbd8SKathiravan T #define GCC_PCIE_AUX_CLK_SRC				85
95*f99cdbd8SKathiravan T #define GCC_PCNOC_AT_CLK				86
96*f99cdbd8SKathiravan T #define GCC_PCNOC_BFDCD_CLK_SRC				87
97*f99cdbd8SKathiravan T #define GCC_PCNOC_LPASS_CLK				88
98*f99cdbd8SKathiravan T #define GCC_PRNG_AHB_CLK				89
99*f99cdbd8SKathiravan T #define GCC_Q6_AXIM_CLK_SRC				93
100*f99cdbd8SKathiravan T #define GCC_QDSS_AT_CLK					99
101*f99cdbd8SKathiravan T #define GCC_QDSS_AT_CLK_SRC				100
102*f99cdbd8SKathiravan T #define GCC_QDSS_CFG_AHB_CLK				101
103*f99cdbd8SKathiravan T #define GCC_QDSS_DAP_AHB_CLK				102
104*f99cdbd8SKathiravan T #define GCC_QDSS_DAP_CLK				103
105*f99cdbd8SKathiravan T #define GCC_QDSS_DAP_DIV_CLK_SRC			104
106*f99cdbd8SKathiravan T #define GCC_QDSS_ETR_USB_CLK				105
107*f99cdbd8SKathiravan T #define GCC_QDSS_EUD_AT_CLK				106
108*f99cdbd8SKathiravan T #define GCC_QDSS_TSCTR_CLK_SRC				107
109*f99cdbd8SKathiravan T #define GCC_QPIC_AHB_CLK				108
110*f99cdbd8SKathiravan T #define GCC_QPIC_CLK					109
111*f99cdbd8SKathiravan T #define GCC_QPIC_IO_MACRO_CLK				110
112*f99cdbd8SKathiravan T #define GCC_QPIC_IO_MACRO_CLK_SRC			111
113*f99cdbd8SKathiravan T #define GCC_QPIC_SLEEP_CLK				112
114*f99cdbd8SKathiravan T #define GCC_SDCC1_AHB_CLK				113
115*f99cdbd8SKathiravan T #define GCC_SDCC1_APPS_CLK				114
116*f99cdbd8SKathiravan T #define GCC_SDCC1_APPS_CLK_SRC				115
117*f99cdbd8SKathiravan T #define GCC_SLEEP_CLK_SRC				116
118*f99cdbd8SKathiravan T #define GCC_SNOC_LPASS_CFG_CLK				117
119*f99cdbd8SKathiravan T #define GCC_SNOC_NSSNOC_1_CLK				118
120*f99cdbd8SKathiravan T #define GCC_SNOC_NSSNOC_CLK				119
121*f99cdbd8SKathiravan T #define GCC_SNOC_PCIE3_1LANE_1_M_CLK			120
122*f99cdbd8SKathiravan T #define GCC_SNOC_PCIE3_1LANE_1_S_CLK			121
123*f99cdbd8SKathiravan T #define GCC_SNOC_PCIE3_1LANE_M_CLK			122
124*f99cdbd8SKathiravan T #define GCC_SNOC_PCIE3_1LANE_S_CLK			123
125*f99cdbd8SKathiravan T #define GCC_SNOC_PCIE3_2LANE_M_CLK			124
126*f99cdbd8SKathiravan T #define GCC_SNOC_PCIE3_2LANE_S_CLK			125
127*f99cdbd8SKathiravan T #define GCC_SNOC_USB_CLK				126
128*f99cdbd8SKathiravan T #define GCC_SYS_NOC_AT_CLK				127
129*f99cdbd8SKathiravan T #define GCC_SYSTEM_NOC_BFDCD_CLK_SRC			129
130*f99cdbd8SKathiravan T #define GCC_UNIPHY0_AHB_CLK				130
131*f99cdbd8SKathiravan T #define GCC_UNIPHY0_SYS_CLK				131
132*f99cdbd8SKathiravan T #define GCC_UNIPHY1_AHB_CLK				132
133*f99cdbd8SKathiravan T #define GCC_UNIPHY1_SYS_CLK				133
134*f99cdbd8SKathiravan T #define GCC_UNIPHY_SYS_CLK_SRC				134
135*f99cdbd8SKathiravan T #define GCC_USB0_AUX_CLK				135
136*f99cdbd8SKathiravan T #define GCC_USB0_AUX_CLK_SRC				136
137*f99cdbd8SKathiravan T #define GCC_USB0_EUD_AT_CLK				137
138*f99cdbd8SKathiravan T #define GCC_USB0_LFPS_CLK				138
139*f99cdbd8SKathiravan T #define GCC_USB0_LFPS_CLK_SRC				139
140*f99cdbd8SKathiravan T #define GCC_USB0_MASTER_CLK				140
141*f99cdbd8SKathiravan T #define GCC_USB0_MASTER_CLK_SRC				141
142*f99cdbd8SKathiravan T #define GCC_USB0_MOCK_UTMI_CLK				142
143*f99cdbd8SKathiravan T #define GCC_USB0_MOCK_UTMI_CLK_SRC			143
144*f99cdbd8SKathiravan T #define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC			144
145*f99cdbd8SKathiravan T #define GCC_USB0_PHY_CFG_AHB_CLK			145
146*f99cdbd8SKathiravan T #define GCC_USB0_PIPE_CLK				146
147*f99cdbd8SKathiravan T #define GCC_USB0_SLEEP_CLK				147
148*f99cdbd8SKathiravan T #define GCC_WCSS_AHB_CLK_SRC				148
149*f99cdbd8SKathiravan T #define GCC_XO_CLK					160
150*f99cdbd8SKathiravan T #define GCC_XO_CLK_SRC					161
151*f99cdbd8SKathiravan T #define GCC_XO_DIV4_CLK					162
152*f99cdbd8SKathiravan T #define GCC_IM_SLEEP_CLK				163
153*f99cdbd8SKathiravan T #define GCC_NSSNOC_PCNOC_1_CLK				164
154*f99cdbd8SKathiravan T #define GCC_MEM_NOC_AHB_CLK				165
155*f99cdbd8SKathiravan T #define GCC_MEM_NOC_APSS_AXI_CLK			166
156*f99cdbd8SKathiravan T #define GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC		167
157*f99cdbd8SKathiravan T #define GCC_MEM_NOC_QOSGEN_EXTREF_CLK			168
158*f99cdbd8SKathiravan T #define GCC_PCIE3X2_PIPE_CLK_SRC			169
159*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_PIPE_CLK_SRC			170
160*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_PIPE_CLK_SRC			171
161*f99cdbd8SKathiravan T #define GCC_USB0_PIPE_CLK_SRC				172
162*f99cdbd8SKathiravan T 
163*f99cdbd8SKathiravan T #define GCC_ADSS_BCR					0
164*f99cdbd8SKathiravan T #define GCC_ADSS_PWM_CLK_ARES				1
165*f99cdbd8SKathiravan T #define GCC_AHB_CLK_ARES				2
166*f99cdbd8SKathiravan T #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR		3
167*f99cdbd8SKathiravan T #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES	4
168*f99cdbd8SKathiravan T #define GCC_APSS_AHB_CLK_ARES				5
169*f99cdbd8SKathiravan T #define GCC_APSS_AXI_CLK_ARES				6
170*f99cdbd8SKathiravan T #define GCC_BLSP1_AHB_CLK_ARES				7
171*f99cdbd8SKathiravan T #define GCC_BLSP1_BCR					8
172*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP1_BCR				9
173*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES		10
174*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES		11
175*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP2_BCR				12
176*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES		13
177*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES		14
178*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP3_BCR				15
179*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES		16
180*f99cdbd8SKathiravan T #define GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES		17
181*f99cdbd8SKathiravan T #define GCC_BLSP1_SLEEP_CLK_ARES			18
182*f99cdbd8SKathiravan T #define GCC_BLSP1_UART1_APPS_CLK_ARES			19
183*f99cdbd8SKathiravan T #define GCC_BLSP1_UART1_BCR				20
184*f99cdbd8SKathiravan T #define GCC_BLSP1_UART2_APPS_CLK_ARES			21
185*f99cdbd8SKathiravan T #define GCC_BLSP1_UART2_BCR				22
186*f99cdbd8SKathiravan T #define GCC_BLSP1_UART3_APPS_CLK_ARES			23
187*f99cdbd8SKathiravan T #define GCC_BLSP1_UART3_BCR				24
188*f99cdbd8SKathiravan T #define GCC_CE_BCR					25
189*f99cdbd8SKathiravan T #define GCC_CMN_BLK_BCR					26
190*f99cdbd8SKathiravan T #define GCC_CMN_LDO0_BCR				27
191*f99cdbd8SKathiravan T #define GCC_CMN_LDO1_BCR				28
192*f99cdbd8SKathiravan T #define GCC_DCC_BCR					29
193*f99cdbd8SKathiravan T #define GCC_GP1_CLK_ARES				30
194*f99cdbd8SKathiravan T #define GCC_GP2_CLK_ARES				31
195*f99cdbd8SKathiravan T #define GCC_LPASS_BCR					32
196*f99cdbd8SKathiravan T #define GCC_LPASS_CORE_AXIM_CLK_ARES			33
197*f99cdbd8SKathiravan T #define GCC_LPASS_SWAY_CLK_ARES				34
198*f99cdbd8SKathiravan T #define GCC_MDIOM_BCR					35
199*f99cdbd8SKathiravan T #define GCC_MDIOS_BCR					36
200*f99cdbd8SKathiravan T #define GCC_NSS_BCR					37
201*f99cdbd8SKathiravan T #define GCC_NSS_TS_CLK_ARES				38
202*f99cdbd8SKathiravan T #define GCC_NSSCC_CLK_ARES				39
203*f99cdbd8SKathiravan T #define GCC_NSSCFG_CLK_ARES				40
204*f99cdbd8SKathiravan T #define GCC_NSSNOC_ATB_CLK_ARES				41
205*f99cdbd8SKathiravan T #define GCC_NSSNOC_NSSCC_CLK_ARES			42
206*f99cdbd8SKathiravan T #define GCC_NSSNOC_QOSGEN_REF_CLK_ARES			43
207*f99cdbd8SKathiravan T #define GCC_NSSNOC_SNOC_1_CLK_ARES			44
208*f99cdbd8SKathiravan T #define GCC_NSSNOC_SNOC_CLK_ARES			45
209*f99cdbd8SKathiravan T #define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES			46
210*f99cdbd8SKathiravan T #define GCC_NSSNOC_XO_DCD_CLK_ARES			47
211*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AHB_CLK_ARES			48
212*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AUX_CLK_ARES			49
213*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_M_CLK_ARES			50
214*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES		51
215*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_S_CLK_ARES			52
216*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_BCR				53
217*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_LINK_DOWN_BCR			54
218*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_PHY_BCR				55
219*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_PHY_PHY_BCR			56
220*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AHB_CLK_ARES			57
221*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AUX_CLK_ARES			58
222*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_M_CLK_ARES			59
223*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES		60
224*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_S_CLK_ARES			61
225*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_BCR				62
226*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_LINK_DOWN_BCR			63
227*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_PHY_BCR				64
228*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_PHY_PHY_BCR			65
229*f99cdbd8SKathiravan T #define GCC_PCIE3X1_PHY_AHB_CLK_ARES			66
230*f99cdbd8SKathiravan T #define GCC_PCIE3X2_AHB_CLK_ARES			67
231*f99cdbd8SKathiravan T #define GCC_PCIE3X2_AUX_CLK_ARES			68
232*f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_M_CLK_ARES			69
233*f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES		70
234*f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_S_CLK_ARES			71
235*f99cdbd8SKathiravan T #define GCC_PCIE3X2_BCR					72
236*f99cdbd8SKathiravan T #define GCC_PCIE3X2_LINK_DOWN_BCR			73
237*f99cdbd8SKathiravan T #define GCC_PCIE3X2_PHY_AHB_CLK_ARES			74
238*f99cdbd8SKathiravan T #define GCC_PCIE3X2_PHY_BCR				75
239*f99cdbd8SKathiravan T #define GCC_PCIE3X2PHY_PHY_BCR				76
240*f99cdbd8SKathiravan T #define GCC_PCNOC_BCR					77
241*f99cdbd8SKathiravan T #define GCC_PCNOC_LPASS_CLK_ARES			78
242*f99cdbd8SKathiravan T #define GCC_PRNG_AHB_CLK_ARES				79
243*f99cdbd8SKathiravan T #define GCC_PRNG_BCR					80
244*f99cdbd8SKathiravan T #define GCC_Q6_AHB_CLK_ARES				81
245*f99cdbd8SKathiravan T #define GCC_Q6_AHB_S_CLK_ARES				82
246*f99cdbd8SKathiravan T #define GCC_Q6_AXIM_CLK_ARES				83
247*f99cdbd8SKathiravan T #define GCC_Q6_AXIS_CLK_ARES				84
248*f99cdbd8SKathiravan T #define GCC_Q6_TSCTR_1TO2_CLK_ARES			85
249*f99cdbd8SKathiravan T #define GCC_Q6SS_ATBM_CLK_ARES				86
250*f99cdbd8SKathiravan T #define GCC_Q6SS_PCLKDBG_CLK_ARES			87
251*f99cdbd8SKathiravan T #define GCC_Q6SS_TRIG_CLK_ARES				88
252*f99cdbd8SKathiravan T #define GCC_QDSS_APB2JTAG_CLK_ARES			89
253*f99cdbd8SKathiravan T #define GCC_QDSS_AT_CLK_ARES				90
254*f99cdbd8SKathiravan T #define GCC_QDSS_BCR					91
255*f99cdbd8SKathiravan T #define GCC_QDSS_CFG_AHB_CLK_ARES			92
256*f99cdbd8SKathiravan T #define GCC_QDSS_DAP_AHB_CLK_ARES			93
257*f99cdbd8SKathiravan T #define GCC_QDSS_DAP_CLK_ARES				94
258*f99cdbd8SKathiravan T #define GCC_QDSS_ETR_USB_CLK_ARES			95
259*f99cdbd8SKathiravan T #define GCC_QDSS_EUD_AT_CLK_ARES			96
260*f99cdbd8SKathiravan T #define GCC_QDSS_STM_CLK_ARES				97
261*f99cdbd8SKathiravan T #define GCC_QDSS_TRACECLKIN_CLK_ARES			98
262*f99cdbd8SKathiravan T #define GCC_QDSS_TS_CLK_ARES				99
263*f99cdbd8SKathiravan T #define GCC_QDSS_TSCTR_DIV16_CLK_ARES			100
264*f99cdbd8SKathiravan T #define GCC_QDSS_TSCTR_DIV2_CLK_ARES			101
265*f99cdbd8SKathiravan T #define GCC_QDSS_TSCTR_DIV3_CLK_ARES			102
266*f99cdbd8SKathiravan T #define GCC_QDSS_TSCTR_DIV4_CLK_ARES			103
267*f99cdbd8SKathiravan T #define GCC_QDSS_TSCTR_DIV8_CLK_ARES			104
268*f99cdbd8SKathiravan T #define GCC_QPIC_AHB_CLK_ARES				105
269*f99cdbd8SKathiravan T #define GCC_QPIC_CLK_ARES				106
270*f99cdbd8SKathiravan T #define GCC_QPIC_BCR					107
271*f99cdbd8SKathiravan T #define GCC_QPIC_IO_MACRO_CLK_ARES			108
272*f99cdbd8SKathiravan T #define GCC_QPIC_SLEEP_CLK_ARES				109
273*f99cdbd8SKathiravan T #define GCC_QUSB2_0_PHY_BCR				110
274*f99cdbd8SKathiravan T #define GCC_SDCC1_AHB_CLK_ARES				111
275*f99cdbd8SKathiravan T #define GCC_SDCC1_APPS_CLK_ARES				112
276*f99cdbd8SKathiravan T #define GCC_SDCC_BCR					113
277*f99cdbd8SKathiravan T #define GCC_SNOC_BCR					114
278*f99cdbd8SKathiravan T #define GCC_SNOC_LPASS_CFG_CLK_ARES			115
279*f99cdbd8SKathiravan T #define GCC_SNOC_NSSNOC_1_CLK_ARES			116
280*f99cdbd8SKathiravan T #define GCC_SNOC_NSSNOC_CLK_ARES			117
281*f99cdbd8SKathiravan T #define GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES		118
282*f99cdbd8SKathiravan T #define GCC_SYS_NOC_WCSS_AHB_CLK_ARES			119
283*f99cdbd8SKathiravan T #define GCC_UNIPHY0_AHB_CLK_ARES			120
284*f99cdbd8SKathiravan T #define GCC_UNIPHY0_BCR					121
285*f99cdbd8SKathiravan T #define GCC_UNIPHY0_SYS_CLK_ARES			122
286*f99cdbd8SKathiravan T #define GCC_UNIPHY1_AHB_CLK_ARES			123
287*f99cdbd8SKathiravan T #define GCC_UNIPHY1_BCR					124
288*f99cdbd8SKathiravan T #define GCC_UNIPHY1_SYS_CLK_ARES			125
289*f99cdbd8SKathiravan T #define GCC_USB0_AUX_CLK_ARES				126
290*f99cdbd8SKathiravan T #define GCC_USB0_EUD_AT_CLK_ARES			127
291*f99cdbd8SKathiravan T #define GCC_USB0_LFPS_CLK_ARES				128
292*f99cdbd8SKathiravan T #define GCC_USB0_MASTER_CLK_ARES			129
293*f99cdbd8SKathiravan T #define GCC_USB0_MOCK_UTMI_CLK_ARES			130
294*f99cdbd8SKathiravan T #define GCC_USB0_PHY_BCR				131
295*f99cdbd8SKathiravan T #define GCC_USB0_PHY_CFG_AHB_CLK_ARES			132
296*f99cdbd8SKathiravan T #define GCC_USB0_SLEEP_CLK_ARES				133
297*f99cdbd8SKathiravan T #define GCC_USB3PHY_0_PHY_BCR				134
298*f99cdbd8SKathiravan T #define GCC_USB_BCR					135
299*f99cdbd8SKathiravan T #define GCC_WCSS_AXIM_CLK_ARES				136
300*f99cdbd8SKathiravan T #define GCC_WCSS_AXIS_CLK_ARES				137
301*f99cdbd8SKathiravan T #define GCC_WCSS_BCR					138
302*f99cdbd8SKathiravan T #define GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES		139
303*f99cdbd8SKathiravan T #define GCC_WCSS_DBG_IFC_APB_CLK_ARES			140
304*f99cdbd8SKathiravan T #define GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES		141
305*f99cdbd8SKathiravan T #define GCC_WCSS_DBG_IFC_ATB_CLK_ARES			142
306*f99cdbd8SKathiravan T #define GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES		143
307*f99cdbd8SKathiravan T #define GCC_WCSS_DBG_IFC_NTS_CLK_ARES			144
308*f99cdbd8SKathiravan T #define GCC_WCSS_ECAHB_CLK_ARES				145
309*f99cdbd8SKathiravan T #define GCC_WCSS_MST_ASYNC_BDG_CLK_ARES			146
310*f99cdbd8SKathiravan T #define GCC_WCSS_Q6_BCR					147
311*f99cdbd8SKathiravan T #define GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES			148
312*f99cdbd8SKathiravan T #define GCC_XO_CLK_ARES					149
313*f99cdbd8SKathiravan T #define GCC_XO_DIV4_CLK_ARES				150
314*f99cdbd8SKathiravan T #define GCC_Q6SS_DBG_ARES				151
315*f99cdbd8SKathiravan T #define GCC_WCSS_DBG_BDG_ARES				152
316*f99cdbd8SKathiravan T #define GCC_WCSS_DBG_ARES				153
317*f99cdbd8SKathiravan T #define GCC_WCSS_AXI_S_ARES				154
318*f99cdbd8SKathiravan T #define GCC_WCSS_AXI_M_ARES				155
319*f99cdbd8SKathiravan T #define GCC_WCSSAON_ARES				156
320*f99cdbd8SKathiravan T #define GCC_PCIE3X2_PIPE_ARES				157
321*f99cdbd8SKathiravan T #define GCC_PCIE3X2_CORE_STICKY_ARES			158
322*f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_S_STICKY_ARES			159
323*f99cdbd8SKathiravan T #define GCC_PCIE3X2_AXI_M_STICKY_ARES			160
324*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_PIPE_ARES				161
325*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_CORE_STICKY_ARES			162
326*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_S_STICKY_ARES			163
327*f99cdbd8SKathiravan T #define GCC_PCIE3X1_0_AXI_M_STICKY_ARES			164
328*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_PIPE_ARES				165
329*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_CORE_STICKY_ARES			166
330*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_S_STICKY_ARES			167
331*f99cdbd8SKathiravan T #define GCC_PCIE3X1_1_AXI_M_STICKY_ARES			168
332*f99cdbd8SKathiravan T #define GCC_IM_SLEEP_CLK_ARES				169
333*f99cdbd8SKathiravan T #define GCC_NSSNOC_PCNOC_1_CLK_ARES			170
334*f99cdbd8SKathiravan T #define GCC_UNIPHY0_XPCS_ARES				171
335*f99cdbd8SKathiravan T #define GCC_UNIPHY1_XPCS_ARES				172
336*f99cdbd8SKathiravan T #endif
337